Gotowe bibliografie tematyczne / Sequential logic circuits

Gotowa bibliografia na temat „Sequential logic circuits”

Autor: Grafiati
Data publikacji: 4 czerwca 2021
Data aktualizacji: 20 lutego 2023

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Artykuły w czasopismach na temat "Sequential logic circuits"

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JAHANIRAD, HADI, i KARIM MOHAMMADI. "SEQUENTIAL LOGIC CIRCUITS RELIABILITY ANALYSIS". Journal of Circuits, Systems and Computers 21, nr 05 (sierpień 2012): 1250040. http://dx.doi.org/10.1142/s0218126612500405.

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Reliability analysis using error probabilities for combinational logic circuits has been investigated widely in the literature. Reliability analysis for sequential logic circuits using these methods would be inaccurate because of existence of loops in their architecture. In this paper a new method based on conversion of sequential circuit to combinational one and applying an iterative reliability analysis is developed. A Monte Carlo method-based reliability analysis is introduced for sequential circuits, which is used for first method validation. Experimental results demonstrate good accuracy of the method.
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Watt, A. "Astables and sequential logic circuits". Electronics Education 1990, nr 2 (1990): 7–8. http://dx.doi.org/10.1049/ee.1990.0021.

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Andrews, Lauren B., Alec A. K. Nielsen i Christopher A. Voigt. "Cellular checkpoint control using programmable sequential logic". Science 361, nr 6408 (20.09.2018): eaap8987. http://dx.doi.org/10.1126/science.aap8987.

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Biological processes that require orderly progression, such as growth and differentiation, proceed via regulatory checkpoints where the cell waits for signals before continuing to the next state. Implementing such control would allow genetic engineers to divide complex tasks into stages. We present genetic circuits that encode sequential logic to instructEscherichia colito proceed through a linear or cyclical sequence of states. These are built with 11 set-reset latches, designed with repressor-based NOR gates, which can connect to each other and sensors. The performance of circuits with up to three latches and four sensors, including a gated D latch, closely match predictions made by using nonlinear dynamics. Checkpoint control is demonstrated by switching cells between multiple circuit states in response to external signals over days.
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Upadhyay, Shipra, R. A. Mishra, R. K. Nagaria i S. P. Singh. "DFAL: Diode-Free Adiabatic Logic Circuits". ISRN Electronics 2013 (10.02.2013): 1–12. http://dx.doi.org/10.1155/2013/673601.

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The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been developed to explain the energy dissipation in the proposed circuit. Performance of the proposed logic is analyzed and compared with CMOS and reported adiabatic logic styles. Also the layout of proposed inverter circuit has been drawn. Subsequently proposed topology-based various logic gates, combinational and sequential circuits and multiplier circuit are designed and simulated. The simulations were performed by VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In proposed inverter the energy efficiency has been improved to almost 60% up to 100 MHz in comparison to conventional CMOS circuits. The present research provides low power high speed results up to 100 MHz, and proposal has proven to be used in power aware high-performance VLSI circuitry.
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Basu, Shaunak, i Subhashree Basu. "Reversible Logic Synthesis of Sequential Circuits". International Journal of Computer Applications 129, nr 11 (17.11.2015): 29–32. http://dx.doi.org/10.5120/ijca2015906999.

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Zhang, Li Min, Zhi Wei Yang, Yao Kun Pang, Tao Zhou, Chi Zhang i Zhong Lin Wang. "Tribotronic triggers and sequential logic circuits". Nano Research 10, nr 10 (14.06.2017): 3534–42. http://dx.doi.org/10.1007/s12274-017-1564-9.

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Levin, Iliya, Osnat Keren i Vladimir Ostrovsky. "Synthesis of sequential circuits by using linearization". Facta universitatis - series: Electronics and Energetics 20, nr 3 (2007): 461–77. http://dx.doi.org/10.2298/fuee0703461l.

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The paper deals with synthesis of sequential circuits defined by their algorithmic state machine notation. Such circuits have a number of specific properties which enable efficient design of the circuits by utilizing so-called linearization techniques. A typical linearization technique includes calculation of autocorrelation values for a system of logic functions corresponding to the circuit. For the mentioned sequential circuits, the calculations which usually require massive computational recourses may be significantly reduced and thus low-overhead implementations of the circuits can be obtained relatively easy. The paper introduces a novel architecture of so-called linearized sequential circuits, and a piece-wise linearization approach for synthesis of sequential circuits. Results are evaluated both analytically and by using a number of standard benchmarks.
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Jagadeesan, Neeraja, B. Saman, M. Lingalugari, P. Gogna i F. Jain. "Sequential Logic Circuits Using Spatial Wavefunction Switched (SWS) FETs". International Journal of High Speed Electronics and Systems 24, nr 03n04 (wrzesień 2015): 1550011. http://dx.doi.org/10.1142/s0129156415500111.

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The spatial wavefunction-switched field-effect transistor (SWSFET) is one of the promising quantum well devices that transfers electrons from one quantum well channel to the other channel based on the applied gate voltage. This eliminates the use of more transistors as we have coupled channels in the same device operating at different threshold voltages. This feature can be exploited in many digital integrated circuits thus reducing the count of transistors which translates to less die area. The simulations of basic sequential circuits like SR latch, D latch and flip flop are presented here using SWSFET based logic gates. The circuit model of a SWSFET was developed using Berkeley short channel IGFET model (BSIM 3).
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MONTEIRO, JOSÉ, SRINIVAS DEVADAS i ABHIJIT GHOSH. "RETIMING SEQUENTIAL CIRCUITS FOR LOW POWER". International Journal of High Speed Electronics and Systems 07, nr 02 (czerwiec 1996): 323–40. http://dx.doi.org/10.1142/s0129156496000141.

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Switching activity is a primary cause of power dissipation in combinational and sequential circuits. In this paper, we present a retiming method that targets the power dissipation of a sequential circuit by reducing the switching activity of nodes driving large capacitive loads. We explore the implications of the observation that the switching activity at flip-flop outputs in a synchronous sequential circuit can be significantly less than the activity at the flip-flop inputs. The method automatically determines positions of flip-flops in the circuit so as to heuristically minimize weighted switching activities summed over all the gates and flip-flops in the circuit. We extend this method to minimize power dissipation with a specified clock period. For this work we need to obtain efficiently an estimation of the switching activity of every node in the circuit. We give an exact method of estimating power in pipelined sequential circuits that accurately models the correlation between the vectors applied to the combinational logic of the circuit. This method is significantly more efficient than methods based on solving Chapman–Kolmogorov equations. Experimental results are presented on a variety of circuits.
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Hudli, Anand V., i Raghu V. Hudli. "Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits". VLSI Design 2, nr 1 (1.01.1994): 69–80. http://dx.doi.org/10.1155/1994/94514.

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Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises because of reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits. Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. A hierarchical test generation algorithm is proposed.
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Rozprawy doktorskie na temat "Sequential logic circuits"

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Thulasi, Raman Sudheer Ram. "Logic Encryption of Sequential Circuits". University of Cincinnati / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1553251689992143.

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Kasarabada, Yasaswy V. "Efficient Logic Encryption Techniques for Sequential Circuits". University of Cincinnati / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1613752483402656.

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Ali, Belgasem. "Evolutionary algorithms for synthesis and optimisation of sequential logic circuits". Thesis, Edinburgh Napier University, 2003. http://researchrepository.napier.ac.uk/Output/4338.

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Considerable progress has been made recently 1n the understanding of combinational logic optimization. Consequently a large number of university and industrial Electric Computing Aided Design (ECAD) programs are now available for optimal logic synthesis of combinational circuits. The progress with sequential logic synthesis and optimization, on the other hand, is considerably less mature. In recent years, evolutionary algorithms have been found to be remarkably effective way of using computers for solving difficult problems. This thesis is, in large part, a concentrated effort to apply this philosophy to the synthesis and optimization of sequential circuits. A state assignment based on the use of a Genetic Algorithm (GA) for the optimal synthesis of sequential circuits is presented. The state assignment determines the structure of the sequential circuit realizing the state machine and therefore its area and performances. The synthesis based on the GA approach produced designs with the smallest area to date. Test results on standard fmite state machine (FS:M) benchmarks show that the GA could generate state assignments, which required on average 15.44% fewer gates and 13.47% fewer literals compared with alternative techniques. Hardware evolution is performed through a succeSSlOn of changes/reconfigurations of elementary components, inter-connectivity and selection of the fittest configurations until the target functionality is reached. The thesis presents new approaches, which combine both genetic algorithm for state assignment and extrinsic Evolvable Hardware (EHW) to design sequential logic circuits. The implemented evolutionary algorithms are able to design logic circuits with size and complexity, which have not been demonstrated in published work. There are still plenty of opportunities to develop this new line of research for the synthesis, optimization and test of novel digital, analogue and mixed circuits. This should lead to a new generation of Electronic Design Automation tools.
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Hacker, Charles Hilton, i n/a. "WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design". Griffith University. School of Engineering, 2001. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20050915.172404.

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This thesis presents an interactive computerised teaching suite developed for the design of combinatorial and sequential logic circuits. This suite fills a perceived gap in the currently available computer-based teaching software for digital logic design. Several existing digital logic educational software are available, however these existing programs were found to be unsuitable for our use in providing alternative mode subject delivery. This prompted the development of a Microsoft Windows TM tutorial suite, called WinLogiLab. WinLogiLab comprises of a set of tutorials that uses student provided input data, to perform the initial design steps for digital Combinatorial and Sequential logic circuits. The combinatorial tutorials are designed to show the link between Boolean Algebra and Digital Logic circuits, and follows the initial design steps: from Boolean algebra, truth tables, to Exact and the Heuristic minimisation techniques, to finally produce the combinatorial circuit. Similarly, the sequential tutorials can design simple State Machine Counters, and can model more complex Finite State Automata.
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Hacker, Charles. "WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design". Thesis, Griffith University, 2001. http://hdl.handle.net/10072/367209.

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This thesis presents an interactive computerised teaching suite developed for the design of combinatorial and sequential logic circuits. This suite fills a perceived gap in the currently available computer-based teaching software for digital logic design. Several existing digital logic educational software are available, however these existing programs were found to be unsuitable for our use in providing alternative mode subject delivery. This prompted the development of a Microsoft Windows TM tutorial suite, called WinLogiLab. WinLogiLab comprises of a set of tutorials that uses student provided input data, to perform the initial design steps for digital Combinatorial and Sequential logic circuits. The combinatorial tutorials are designed to show the link between Boolean Algebra and Digital Logic circuits, and follows the initial design steps: from Boolean algebra, truth tables, to Exact and the Heuristic minimisation techniques, to finally produce the combinatorial circuit. Similarly, the sequential tutorials can design simple State Machine Counters, and can model more complex Finite State Automata.
Thesis (Masters)
Master of Philosophy (MPhil)
School of Engineering
Science, Environment, Engineering and Technology
Full Text
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Duong, Khanh Viet. "On Enhancing Deterministic Sequential ATPG". Thesis, Virginia Tech, 2011. http://hdl.handle.net/10919/31283.

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This thesis presents four different techniques for improving the average-case performance of deterministic sequential circuit Automatic Test Patterns Generators (ATPG). Three techniques make use of information gathered during test generation to help identify more unjustifiable states with higher percentage of â donâ t careâ value. An approach for reducing the search space of the ATPG was introduced. The technique can significantly reduce the size of the search space but cannot ensure the completeness of the search. Results on ISCASâ 85 benchmark circuits show that all of the proposed techniques allow for better fault detection in shorter amounts of time. These techniques, when used together, produced test vectors with high fault coverages. Also investigated in this thesis is the Decision Inversion Problem which threatens the completeness of ATPG tools such as HITEC or ATOMS. We propose a technique which can eliminate this problem by forcing the ATPG to consider search space with certain flip-flops untouched. Results show that our technique eliminated the decision inversion problem, ensuring the soundness of the search algorithm under the 9-valued logic model.
Master of Science
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Yuan, Zeying. "Sequential Equivalence Checking of Circuits with Different State Encodings by Pruning Simulation-based Multi-Node Invariants". Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/56693.

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Verification is an important step for Integrated Circuit (IC) design. In fact, literature has reported that up to 70% of the design effort is spent on checking if the design is functionally correct. One of the core verification tasks is Equivalence Checking (EC), which attempts to check if two structurally different designs are functionally equivalent for all reachable states. Powerful equivalence checking can also provide opportunities for more aggressive logic optimizations, meeting different goals such as smaller area, better performance, etc. The success of Combinational Equivalence Checking (CEC) has laid a foundation to industry-level combinational logic synthesis and optimization. However, Sequential Equivalence Checking (SEC) still faces much challenge, especially for those complex circuits that have different state encodings and few internal signal equivalences. In this thesis, we propose a novel simulation-based multi-node inductive invariant generation and pruning technique to check the equivalence of sequential circuits that have different state encodings and very few equivalent signals between them. By first grouping flip-flops into smaller subsets to make it scalable for large designs, we then propose a constrained logic synthesis technique to prune potential multi-node invariants without inadvertently losing important constraints. Our pruning technique guarantees the same conclusion for different instances (proving SEC or not) compared to previous approaches in which merging of such potential invariants might lose important relations if the merged relation does not turn out to be a true invariant. Experimental results show that the smaller invariant set can be very effective for sequential equivalence checking of such hard SEC instances. Our approach is up to 20x-- faster compared to previous mining-based methods for larger circuits.
Master of Science
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Lee, Chris Y. "Full Custom VLSI Design of On-Line Stability Checkers". DigitalCommons@CalPoly, 2011. https://digitalcommons.calpoly.edu/theses/607.

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A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly. A method for concurrent fault testing called On-line Stability Checking was introduced by Franco and McCluskey [10] to detect reliability failures. Reliability failures initially manifest themselves as delay faults and transient glitching, which become progressively larger over time due to the wearout of conducting metal lines, eventually leading to functional faults. Stability checkers periodically detect reliability failures by monitoring CUT output signals for unstable and late input signals over a time period after the sampling clock edge. The checkers are tested by applying variable delayed input test patterns to emulate reliability failures. Consequently, configurable delay chains were incorporated into the system to provide variable delays on the input signal lines. The system also includes external test signal ports. Circuit and layout designs were implemented in the Electric VLSI Design tool [12] and simulated with LTSPICE [13]. Electric provides Design Rule Checking (DRC) and Layout-versus-Schematic (LVS) utilities for verification. Each module was designed in a bottom-up, hierarchical cell-based approach. Functional simulation, DRC and LVS checks were performed at every subsequent higher cell layer in the design hierarchy. The final chip layout was taped out for fabrication on November 29, 2010 and finished parts were received on July 7, 2011 after two manufacturing delays. Finished packaged parts were successfully verified for functionality based on SPICE simulations. The stability checkers were tested for flip-flop operation, glitch detection and late signal arrival detection. Configurable delay chains were tested to determine delay resolution and uniformity. Actual delay resolution and range measurements show a 3 to 4 times difference compared to simulated values. The Electric design template created from this project includes basic CMOS logic gates with uniform standard cell heights. The template contains a 40-pin pad ring cell along with the individual pad ring components. EE 431 students would be able to create custom chips that are compatible for fabrication via the MOSIS MEP service. In future work, the template design library can be expanded to include more logic gate variants of various inputs and drive strengths as well as more complex functional modules.
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Ryu, Hyeyeon. "Integrated Circuits Based on Individual Single-Walled Carbon Nanotube Field-Effect Transistors". Doctoral thesis, Universitätsbibliothek Chemnitz, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-98220.

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This thesis investigates the fabrication and integration of nanoscale field-effect transistors based on individual semiconducting carbon nanotubes. Such devices hold great potential for integrated circuits with large integration densities that can be manufactured on glass or flexible plastic substrates. A process to fabricate arrays of individually addressable carbon-nanotube transistors has been developed, and the electrical characteristics of a large number of transistors has been measured and analyzed. A low-temperature-processed gate dielectric with a thickness of about 6 nm has been developed that allows the transistors and circuits to operate with voltages of about 1.5 V. The transistors show excellent electrical properties, including a large transconductance (up to 10 µS), a large On/Off ratio (>10^4), a steep subthreshold swing (65 mV/decade), and negligible leakage currents (~10^-13 A). For the realization of unipolar logic circuits, monolithically integrated load resistors based on high-resistance metallic carbon nanotubes or vacuum-evaporated carbon films have been developed and analyzed by four-probe and transmission line measurements. A variety of combinational logic circuits, such as inverters, NAND gates and NOR gates, as well as a sequential logic circuit based on carbon-nanotube transistors and monolithically integrated resistors have been fabricated on glass substrates and their static and dynamic characteristics have been measured. Optimized inverters operate with frequencies as high as 2 MHz and switching delay time constants as short as 12 ns
Thema dieser Arbeit ist die Herstellung und Integration von Feldeffekt-Transistoren auf der Grundlage einzelner halbleitender Kohlenstoffnanoröhren. Solche Bauelemente sind zum Beispiel für die Realisierung integrierter Schaltungen mit hoher Integrationsdichte auf Glassubstraten oder auf flexiblen Kunststofffolien von Interesse. Zunächst wurde ein Herstellungsverfahren für die Anfertigung einer großen Anzahl solcher Transistoren auf Glas- oder Kunststoffsubstraten entwickelt, und deren elektrische Eigenschaften wurden gemessen und ausgewertet. Das Gate-Dielektrikum dieser Transistoren hat eine Schichtdicke von etwa 6 nm, so das die Versorgungsspannungen bei etwa 1.5 V liegen. Die Transistoren haben sehr gute elektrische Parameter, z.B. einen großen Durchgangsleitwert (bis zu 10 µS), ein großes Modulationsverhältnis (>10^4), einen steilen Unterschwellanstieg (65 mV/Dekade) und vernachlässigbar kleine Leckströme (~10^-13 A). Für die Realisierung unipolarer Logikschaltungen wurden monolithisch integrierte Lastwiderstände auf der Grundlage metallischer Kohlenstoffnanoröhren mit großem Widerstand oder mittels Vakuumabscheidung erzeugter Kohlenstoffschichten entwickelt und u. a. mittels Vierpunkt- und Transferlängen-Messungen analysiert. Eine Reihe kombinatorischer Schaltungen, z.B. Inverter, NAND-Gatter und NOR-Gatter, sowie eine sequentielle Logikschaltung wurden auf Glassubstraten hergestellt, und deren statische und dynamische Parameter wurden gemessen. Optimierte Inverter arbeiten bei Frequenzen von bis zu 2 MHz und haben Signalverzögerungen von lediglich 12 ns
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Mohamed, Mohamed Hassan Wahba Ayman. "Diagnostic des erreurs de conception dans les circuits digitaux : le cas des erreurs simples". Grenoble 1, 1997. http://www.theses.fr/1997GRE10086.

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Le diagnostic automatique des erreurs de conception est un probleme important dans le domaine de la cao. Bien que des outils automatises de synthese soient employes pour generer des structures de circuits correctes-par-construction, celles-ci sont souvent modifiees manuellement pour refleter des petites modifications faites sur la specification, ou pour ameliorer certaines caracteristiques critiques de la conception. Les outils de verification peuvent reveler l'existence d'erreurs, mais ils ne donnent aucune information sur leurs emplacements ou la facon de les corriger. Ces outils generent seulement quelques contres-exemples qui mettent en evidence l'erreur. Les concepteurs utilisent ces contre-exemples pour diagnostiquer manuellement leur conception. Le diagnostic manuel est un processus tres lent et tres couteux. Le temps de diagnostic peut etre egal, voire superieur, au temps de conception. Nous presentons dans cette these de nouveaux algorithmes pour la localisation et la correction automatique des erreurs simples de conception dans les circuits logiques sous l'hypothese d'une seule erreur. Les erreurs traitees ici sont : le remplacement d'un composant dans les circuits combinatoires et sequentiels, et une erreur de connexion dans les circuits combinatoires. Le modele d'une seule erreur exige une strategie de verification frequente, dans laquelle la conception est verifiee apres chaque modification, pour que la probabilite d'insertion de plus d'une erreur ne soit pas trop elevee. Notre approche consiste a simuler et analyser automatiquement le circuit sous l'application de vecteurs de test que nous produisons specialement pour accelerer le diagnostic. Nous avons realise deux logiciels prototypes bases sur ces algorithmes. Ccds est l'outil de diagnostic pour les circuits combinatoires, et scds est l'outil de diagnostic pour les circuits sequentiels. Ces outils sont actuellement integres dans l'environnement de preuves prevail#t#m.
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Książki na temat "Sequential logic circuits"

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Ashar, Pranav. Sequential logic synthesis. Boston: Kluwer Academic Publishers, 1992.

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Srinivas, Devadas, i Newton A. Richard 1951-, red. Sequential logic testing and verification. Boston: Kluwer Academic, 1992.

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Vasyukevich, Vadim. Asynchronous Operators of Sequential Logic: Venjunction & Sequention: Digital Circuit Analysis and Design. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011.

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Monteiro, José. Computer-aided design techniques for low power sequential logic circuits. Boston: Kluwer Academic, 1997.

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Monteiro, Jose. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits. Boston, MA: Springer US, 1997.

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Monteiro, José, i Srinivas Devadas. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6319-8.

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Monteiro, José. Computer-aided design techniques for low power sequential logiccircuits. Boston, Mass: Kluwer, 1997.

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Comer, David J. Digital logic and state machine design. Wyd. 2. Philadelphia, Pa: Saunders College Pub, 1990.

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Comer, David J. Digital logic and state machine design. Wyd. 3. New York: Oxford University Press, 1995.

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Digital logic and state machine design. Wyd. 3. Ft. Worth: Saunders College Pub., 1995.

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Części książek na temat "Sequential logic circuits"

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Lewin, D., i D. Protheroe. "Sequential circuits". W Design of Logic Systems, 200–251. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4899-6856-2_6.

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Posthoff, Christian, i Bernd Steinbach. "Sequential Circuits". W Logic Functions and Equations, 459–94. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-02420-8_10.

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Steinbach, Bernd, i Christian Posthoff. "Sequential Circuits". W Logic Functions and Equations, 741–94. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-88945-6_12.

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Tietze, Ulrich, Christoph Schenk i Eberhard Gamm. "Sequential Logic Systems". W Electronic Circuits, 659–88. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-78655-9_9.

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Hsu, John Y. "Sequential Logic Circuits". W Computer Logic, 143–84. New York, NY: Springer New York, 2002. http://dx.doi.org/10.1007/978-1-4613-0047-2_5.

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Waterworth, G. "Sequential Logic Circuits". W Work Out Electronics, 240–53. London: Macmillan Education UK, 1988. http://dx.doi.org/10.1007/978-1-349-10008-8_14.

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Hajji, Bekkay, Adel Mellit i Loubna Bouselham. "Sequential Logic Circuits". W A Practical Guide for Simulation and FPGA Implementation of Digital Design, 119–73. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-0615-2_4.

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Groote, Jan Friso, Rolf Morel, Julien Schmaltz i Adam Watkins. "Sequential circuits". W Logic Gates, Circuits, Processors, Compilers and Computers, 53–72. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-68553-9_3.

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Taha, Saleem Mohammed Ridha. "Reversible Sequential Logic Circuits". W Studies in Systems, Decision and Control, 119–34. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-23479-3_5.

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Ghosh, Abhijit, Srinivas Devadas i A. Richard Newton. "Verification of Sequential Circuits". W Sequential Logic Testing and Verification, 123–51. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3646-8_5.

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Streszczenia konferencji na temat "Sequential logic circuits"

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Kasarabada, Yasaswy, Sudheer Ram Thulasi Raman i Ranga Vemuri. "Deep State Encryption for Sequential Logic Circuits". W 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2019. http://dx.doi.org/10.1109/isvlsi.2019.00068.

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Li, Ren, Reem Alhadrami i Hossein Fariborzi. "BEOL NEM Relay Based Sequential Logic Circuits". W 2019 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2019. http://dx.doi.org/10.1109/iscas.2019.8702123.

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Dai, Jing, Jianping Hu, Weiqiang Zhang i Ling Wang. "Adiabatic CPL Circuits for Sequential Logic Systems". W 2006 49th IEEE International Midwest Symposium on Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/mwscas.2006.382162.

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Lukac, Martin, i Marek Perkowski. "Quantum Finite State Machines as Sequential Quantum Circuits". W 2009 39th International Symposium on Multiple-Valued Logic. IEEE, 2009. http://dx.doi.org/10.1109/ismvl.2009.46.

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Soeken, M., R. Wille, C. Otterstedt i R. Drechsler. "A Synthesis Flow for Sequential Reversible Circuits". W 2012 IEEE 42nd International Symposium on Multiple-Valued Logic (ISMVL). IEEE, 2012. http://dx.doi.org/10.1109/ismvl.2012.72.

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Qiaoyan Yu i Drew Stock. "Collaborative error control method for sequential logic circuits". W 2013 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2013. http://dx.doi.org/10.1109/iscas.2013.6571964.

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Erbakanov, Lenko, Krassimir Atanassov, Sotir Sotirov i Stanislav Simeonov. "Generalized net models of basic sequential logic circuits". W 2016 IEEE 8th International Conference on Intelligent Systems (IS). IEEE, 2016. http://dx.doi.org/10.1109/is.2016.7737483.

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Rohini, H., S. Rajashekar i Priyatam Kumar. "Design of basic sequential circuits using reversible logic". W 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT). IEEE, 2016. http://dx.doi.org/10.1109/iceeot.2016.7755062.

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Mohammadi, Karim, Hadi Jahanirad i Pejman Attarsharghi. "Fast Reliability Analysis Method for Sequential Logic Circuits". W 2011 21st International Conference on Systems Engineering (ICSEng). IEEE, 2011. http://dx.doi.org/10.1109/icseng.2011.70.

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Hsiao, Shen-Fu, Ming-Yu Tsai i Chia-Sheng Wen. "Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits". W APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/apccas.2006.342077.

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