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Artykuły w czasopismach na temat „REVERSIBLE MULTIPLIER”

Autor: Grafiati

Data publikacji: 11 września 2023

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1

HAGHPARAST, MAJID, MAJID MOHAMMADI, KEIVAN NAVI i MOHAMMAD ESHGHI. "OPTIMIZED REVERSIBLE MULTIPLIER CIRCUIT". Journal of Circuits, Systems and Computers 18, nr 02 (kwiecień 2009): 311–23. http://dx.doi.org/10.1142/s0218126609005083.

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Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.

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2

Rashno, Meysam, Majid Haghparast i Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier". International Journal of Quantum Information 18, nr 03 (kwiecień 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.

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In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.

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3

Rayudu, Kurada Verra Bhoga Vasantha, Dhananjay Ramachandra Jahagirdar i Patri Srihari Rao. "Design and testing of systolic array multiplier using fault injecting schemes". Computer Science and Information Technologies 3, nr 1 (1.03.2022): 1–9. http://dx.doi.org/10.11591/csit.v3i1.p1-9.

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Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low power appliances, faults and coverage of the reversible logic are calculated in this paper. To improvise more, we introduced a reversible logic gate and tested the reversible systolic array multiplier using the fault injection method of built-in self-test block observer (BILBO) in which all corner cases are covered which shows 97% coverage compared with existing designs. Finally, Xilinx ISE 14.7 was used for synthesis and simulation results and compared parameters with existing designs which prove more efficiency.

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4

Durgam, Veena, i Dr K. Ragini. "Design of 32x32 Reversible Unsigned Multiplier Using Dadda Tree Algorithm". ECS Transactions 107, nr 1 (24.04.2022): 16251–58. http://dx.doi.org/10.1149/10701.16251ecst.

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Multipliers are essential parts of every processor or computer. Microcontrollers and digital signal processors typically measure their performance on how many multiplications they can execute in a given amount of time. As a result, better multiplier designs are sure to increase system efficiency. A reversible Dadda multiplier is one such possible approach. The Dadda tree technique is used to construct two 32x32 reversible unsigned multipliers in this paper. The TG and FG gates are accustomed to create the partial product circuit in the first design. The PG and TG are utilized to create a partial product circuit in the second design. For adding partial products, the PG and reversible full adder gates are used. The design is implemented using Xilinx ISE 14.7 design suite.

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5

Raviteja, Ragoju, Mittapelli Kalyan Krishna, Gare Sandhya i N. Srinivasa Reddy. "Approximative Signed Wallace Tree Multiplier Using Reversible Logic". International Journal for Research in Applied Science and Engineering Technology 11, nr 4 (30.04.2023): 2474–78. http://dx.doi.org/10.22214/ijraset.2023.50668.

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Abstract: The bulk of high-performance and information systems, including microcomputers and digital signal processors, have multipliers as an essential piece of hardware. Convolutional unit are the computationally demanding and performancedetermining operating units in the vast majority of signal conditioning applications. Its length, latency, and power for convolution units, which largely employ adders and multiplyers, are strongly influenced by multipliers. Multimedia and convolution neural networks, which employ processing units, are two examples of real-world applications that place a high demand on high speed multipliers which are optimised both size and power. This project presents an innovative approximation sign Wallace tree multiplication with a approximative 4:2 compressor. Reversible circuitry improves the design for implementation.

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6

Zomorodi Moghadam, Mariam, i Keivan Navi. "Ultra-area-efficient reversible multiplier". Microelectronics Journal 43, nr 6 (czerwiec 2012): 377–85. http://dx.doi.org/10.1016/j.mejo.2012.02.004.

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7

Eshack, Ansiya, i S. Krishnakumar. "Reversible logic in pipelined low power vedic multiplier". Indonesian Journal of Electrical Engineering and Computer Science 16, nr 3 (1.12.2019): 1265. http://dx.doi.org/10.11591/ijeecs.v16.i3.pp1265-1272.

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<span>With an ever growing demand for low-power devices, it is a general trend to search for ways to reduce the power consumption of a system. Multipliers are an important requirement in applications linked to Digital Signal Processing, Communication Systems, Optical Computing, Nanotechnology, Low-Power Very Large Scale Integration and Quantum Computing. Conventional mathematics makes multiplication a very long and time consuming process. The use of Vedic mathematics has led to great reduction in the time required for such calculations. The excessive use of Urdhava Tiryakbhyam sutra in multiplication surely proves its effectiveness and simplicity in this domain. This sutra supports the process of pipelining, a method employed in reduction of the power used by a system. Reversible logic has been gaining demand due to its low-power capabilities and is currently being used in many computing applications. The paper proposes two multiplier systems: one design employs the Urdhava Tiryakbhyam sutra along with pipelining and the second uses reversible logic gates into the first design. These proposed systems provide very less delay for result computation and low hardware utilization when compared to non-pipelined Vedic multipliers.</span>

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8

Saravanan. "NOVEL REVERSIBLE VARIABLE PRECISION MULTIPLIER USING REVERSIBLE LOGIC GATES". Journal of Computer Science 10, nr 7 (1.07.2014): 1135–38. http://dx.doi.org/10.3844/jcssp.2014.1135.1138.

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9

Ariafar, Zahra, i Mohammad Mosleh. "Effective Designs of Reversible Vedic Multiplier". International Journal of Theoretical Physics 58, nr 8 (24.05.2019): 2556–74. http://dx.doi.org/10.1007/s10773-019-04145-0.

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10

SaiAbhinav, B., M. Jaipal Reddy, Y. Siva Kumar i S. Sivanantham S.Sivanantham. "ASIC Design of Reversible Adder and Multiplier". International Journal of Computer Applications 109, nr 10 (16.01.2015): 6–10. http://dx.doi.org/10.5120/19222-0638.

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11

Rashno, Meysam, Majid Haghparast i Mohammad Mosleh. "Designing of Parity Preserving Reversible Vedic Multiplier". International Journal of Theoretical Physics 60, nr 8 (13.07.2021): 3024–40. http://dx.doi.org/10.1007/s10773-021-04903-z.

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12

H.G, Rangaraju, Aakash Babu Suresh i Muralidhara K.N. "Design and Optimization of Reversible Multiplier Circuit". International Journal of Computer Applications 52, nr 10 (30.08.2012): 44–50. http://dx.doi.org/10.5120/8242-1523.

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13

PourAliAkbar, Ehsan, Keivan Navi, Majid Haghparast i Midia Reshadi. "Novel Optimum Parity-Preserving Reversible Multiplier Circuits". Circuits, Systems, and Signal Processing 39, nr 10 (8.04.2020): 5148–68. http://dx.doi.org/10.1007/s00034-020-01406-w.

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14

Baraniya, Shweta, i Sujeet Mishra. "Review Paper on Reversible Multiplier Circuit using Different Programmable Reversible Gate". International Journal of Electrical and Electronics Engineering 2, nr 10 (25.10.2015): 16–20. http://dx.doi.org/10.14445/23488379/ijeee-v2i10p104.

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15

Zhou, Rigui, Yang Shi, Hui’an Wang i Jian Cao. "Transistor realization of reversible “ZS” series gates and reversible array multiplier". Microelectronics Journal 42, nr 2 (luty 2011): 305–15. http://dx.doi.org/10.1016/j.mejo.2010.11.008.

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16

Rahman, Md M., Md M. Hossain, Lafifa Jamal i S. Nowrin. "Designing of a reversible fault tolerant booth multiplier". Bangladesh Journal of Scientific and Industrial Research 53, nr 3 (18.09.2018): 199–204. http://dx.doi.org/10.3329/bjsir.v53i3.38266.

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Conventional logic dissipates more power by losing bits of information whereas reversibility recovers bit loss from the unique input-output mapping. This paper presents the design of a reversible fault tolerant booth multiplier which can multiply both signed and unsigned numbers. The proposed circuit tolerant designed using only fault tolerant reversible gates. Thus the entire scheme inherently becomes fault tolerant. Several theorems on the numbers of gates, garbage outputs, quantum cost of the proposed design have been presented to show the efficiency of the design. The result analysis shows that the proposed design is optimized in terms of all cost parameters. The simulation of the proposed circuit verifies the correctness of the circuit.Bangladesh J. Sci. Ind. Res.53(3), 199-204, 2018

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17

Gholpe, Minal, i Prasad Sangare. "ASIC Design of Reversible Multiplier Using Adiabatic Technique". International Journal of Computer Applications Technology and Research 6, nr 2 (20.02.2017): 117–20. http://dx.doi.org/10.7753/ijcatr0602.1009.

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18

PourAliAkbar, Ehsan, i Mohammad Mosleh. "An efficient design for reversible Wallace unsigned multiplier". Theoretical Computer Science 773 (czerwiec 2019): 43–52. http://dx.doi.org/10.1016/j.tcs.2018.06.007.

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19

Islam, M. S., M. M. Rahman, Z. Begum i M. Z. Hafiz. "Low Cost Quantum Realization of Reversible Multiplier Circuit". Information Technology Journal 8, nr 2 (1.02.2009): 208–13. http://dx.doi.org/10.3923/itj.2009.208.213.

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20

H R, Bhagyalakshmi. "Optimized Multiplier Using Reversible Multicontrol Input Toffoli Gates". International Journal of VLSI Design & Communication Systems 3, nr 6 (31.12.2012): 27–40. http://dx.doi.org/10.5121/vlsic.2012.3603.

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21

Amrutha, P., i P. A. Sunny Dayal. "A Novel Design of Low Power Reversible Multiplier". IOSR Journal of Electronics and Communication Engineering 9, nr 3 (2014): 08–14. http://dx.doi.org/10.9790/2834-09350814.

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22

Sakode, Prof V. M., i Prof A. D. Morankar. "Reversible Multiplier with Peres Gate and Full Adder". IOSR Journal of Electronics and Communication Engineering 9, nr 3 (2014): 43–50. http://dx.doi.org/10.9790/2834-09364350.

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23

Sanjeevaiah, Girija, i Sangeetha Bhandari Gajanan. "Design of efficient reversible floating-point arithmetic unit on field programmable gate array platform and its performance analysis". International Journal of Electrical and Computer Engineering (IJECE) 13, nr 1 (1.02.2023): 697. http://dx.doi.org/10.11591/ijece.v13i1.pp697-708.

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<p><span>The reversible logic gates are used to improve the power dissipation in modern computer applications. The floating-point numbers with reversible features are added advantage to performing complex algorithms with high-performance computations. This manuscript implements an efficient reversible floating-point arithmetic (RFPA) unit, and its performance metrics are realized in detail. The RFP adder/subtractor (A/S), RFP multiplier, and RFP divider units are designed as a part of the RFP arithmetic unit. The RFPA unit is designed by considering basic reversible gates. The mantissa part of the RFP multiplier is created using a 24x24 Wallace tree multiplier. In contrast, the reciprocal unit of the RFP divider is designed using Newton Raphson’s method. The RFPA unit and its submodules are executed in parallel by utilizing one clock cycle individually. The RFPA unit and its submodules are synthesized separately on the Vivado IDE environment and obtained the implementation results on Artix-7 field programmable gate array (FPGA). The RFPA unit utilizes only 18.44% slice look-up tables (LUTs) by consuming the 0.891 W total power on Artix-7 FPGA. The RFPA unit sub-models are compared with existing approaches with better performance metrics and chip resource utilization improvements.</span></p>

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24

Rajmohan, V., i O. Uma Maheswari. "Design of Compact Baugh-Wooley Multiplier Using Reversible Logic". Circuits and Systems 07, nr 08 (2016): 1522–29. http://dx.doi.org/10.4236/cs.2016.78133.

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25

Raveendran, Sithara, Pranose J. Edavoor, Y. B. Nithin Kumar i M. H. Vasantha. "Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic". IEEE Access 9 (2021): 108119–30. http://dx.doi.org/10.1109/access.2021.3100892.

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26

Dayal, Anand, i Himanshu Shekhar. "A Result Analysis of ASIC Design of Reversible Multiplier Circuit". International Journal of Computer Applications 160, nr 8 (22.02.2017): 40–43. http://dx.doi.org/10.5120/ijca2017913071.

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27

Alexander, S. "Design and Implementation of Efficient Reversible Multiplier Using Tanner EDA". International Journal of MC Square Scientific Research 5, nr 1 (6.06.2013): 15–22. http://dx.doi.org/10.20894/ijmsr.117.005.001.003.

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28

Sagar, Sagar. "Design of Low Power Vedic Multiplier Based on Reversible Logic". International Journal of Engineering Research and Applications 07, nr 03 (marzec 2017): 73–78. http://dx.doi.org/10.9790/9622-0703027378.

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29

Nayeem. "Efficient Reversible Montgomery Multiplier and Its Application to Hardware Cryptography". Journal of Computer Science 5, nr 1 (1.01.2009): 49–56. http://dx.doi.org/10.3844/jcs.2009.49.56.

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30

AnanthaLakshmi, A. V., i G. F. Sudha. "Design of an Efficient Reversible Single Precision Floating Point Multiplier". Journal of Bioinformatics and Intelligent Control 4, nr 1 (1.03.2015): 21–30. http://dx.doi.org/10.1166/jbic.2015.1109.

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31

Nayeem. "Efficient Reversible Montgomery Multiplier and Its Application to Hardware Cryptography". Journal of Computer Science 5, nr 1 (1.01.2009): 49–56. http://dx.doi.org/10.3844/jcssp.2009.49.56.

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32

Pandey, Neeta, Nalin Dadhich i Mohd Zubair Talha. "An Optimized and Cost Efficient Realization of Reversible Braun Multiplier". i-manager's Journal on Circuits and Systems 3, nr 3 (15.08.2015): 17–24. http://dx.doi.org/10.26634/jcir.3.3.4781.

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33

Banerjee, Arindam, i Debesh Kumar Das. "The Design of Reversible Signed Multiplier Using Ancient Indian Mathematics". Journal of Low Power Electronics 11, nr 4 (1.12.2015): 467–78. http://dx.doi.org/10.1166/jolpe.2015.1413.

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34

Hridya, S., Dr S. Bhavani, Dr K. G. Dharani i M. Darani Kumar. "A Multiplier Design based on Ancient Indian Vedic Mathematics Using Reversible Logic: A Review". Journal of Advanced Research in Dynamical and Control Systems 11, nr 10-SPECIAL ISSUE (31.10.2019): 911–24. http://dx.doi.org/10.5373/jardcs/v11sp10/20192887.

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35

Anitha, R., R. Thenmozhi, M. Madhunila i Sarat Kumar Sahoo. "A Comparitive Study of Vedic BCD Multiplier using Reversible Logic Gates". Research Journal of Applied Sciences, Engineering and Technology 11, nr 12 (25.12.2015): 1298–304. http://dx.doi.org/10.19026/rjaset.11.2238.

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36

Mukku, Venkateswarlu, i Jaddu MallikharjunaReddy. "An Area Efficient and High Speed Reversible Multiplier Using NS Gate". International Journal of Engineering Research and Applications 7, nr 01 (styczeń 2017): 29–33. http://dx.doi.org/10.9790/9622-0701042933.

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37

PChavan, Arunkumar, Prakash Pawar i Varun R. "Design of Pulse Detectors and Unsigned Sequential Multiplier using Reversible Logic". International Journal of Computer Applications 92, nr 4 (18.04.2014): 11–17. http://dx.doi.org/10.5120/15996-4891.

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38

Nandal, Amita, T. Vigneswaran i Ashwani Rana. "Optimized Reversible Logic Based Add and Shift Multiplier Using Linear Transformation". Advanced Science, Engineering and Medicine 5, nr 5 (1.05.2013): 431–35. http://dx.doi.org/10.1166/asem.2013.1282.

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39

Pankaj, N. Rajeev, P. Venugopal i Prasanthi Mortha. "Design of quantum cost efficient reversible multiplier using Reed-Muller expressions". International Journal of Computing Science and Mathematics 7, nr 3 (2016): 221. http://dx.doi.org/10.1504/ijcsm.2016.077861.

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40

Kamaraj, A., i P. Marichamy. "Design of fault-tolerant reversible Vedic multiplier in quantum cellular automata". Journal of the National Science Foundation of Sri Lanka 47, nr 4 (17.12.2019): 371. http://dx.doi.org/10.4038/jnsfsr.v47i4.9677.

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41

Kumar, Ravi. "Implementation of the Binary Multiplier on CPLD Using Reversible Logic Gates". IOSR Journal of Electronics and Communication Engineering 12, nr 01 (marzec 2017): 40–42. http://dx.doi.org/10.9790/2834-1201034042.

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42

Gowthami, Nekkanti, i K. Srilakshmi. "Design and Implementation of Reversible Multiplier using optimum TG Full Adder". IOSR Journal of Electronics and Communication Engineering 12, nr 03 (lipiec 2017): 81–89. http://dx.doi.org/10.9790/2834-1203048189.

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43

Ahmad, Nabihah, Ahmad Hakimi Mokhtar, Nurmiza binti Othman, Chin Fhong Soon i Ab Al Hadi Ab Rahman. "VLSI Implementation of Fault Tolerance Multiplier based on Reversible Logic Gate". IOP Conference Series: Materials Science and Engineering 226 (sierpień 2017): 012140. http://dx.doi.org/10.1088/1757-899x/226/1/012140.

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44

Shukla, Vandana, O. P. Singh, G. R. Mishra i R. K. Tiwari. "Reversible Realization of 4-Bit Vedic Multiplier Circuit with Optimized Performance Parameters". Sensor Letters 17, nr 10 (1.10.2019): 826–31. http://dx.doi.org/10.1166/sl.2019.4155.

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Low power high speed calculating devices are foremost requirement of this era. Moreover, multiplication is considered as the most vital part of any calculating system. Multiplication process is generally considered as the speed limiting process as it requires more time as compared to other basic arithmetic calculations. So, here we focus on multiplication calculation using vedic method. Moreover, Reversible realization of any digital circuit improves the performance of the system by reducing the power loss from it. Here, the concept of vedic multiplication and Reversible approach are combined to propose a 4-bit multiplier circuit with optimized performance parameters. Proposed design is also analyzed and compared with existing designs. This approach may be employed to propose other low loss devices.

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45

D.V.R, Mohan, Vidyamadhuri K, RamaLakshmanna Y i K. H. S. Suresh kumar. "Design of Low Power Multiplier using Reversible logic: A Vedic Mathematical Approach". IJARCCE 6, nr 3 (30.03.2017): 96–102. http://dx.doi.org/10.17148/ijarcce.2017.6321.

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46

S M, Mayur. "Design of a Low Power Vedic Multiplier using BKG Reversible Logic Gate". International Journal for Research in Applied Science and Engineering Technology 6, nr 6 (30.06.2018): 1586–90. http://dx.doi.org/10.22214/ijraset.2018.6232.

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47

Yogeswari, K. "Design and Performance Comparison of 16-Bit UT Multiplier using Reversible Logic". International Journal for Research in Applied Science and Engineering Technology 7, nr 4 (30.04.2019): 903–11. http://dx.doi.org/10.22214/ijraset.2019.4161.

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48

K N, Hemalatha, i Sangeetha B G. "Efficient Design of Compact 8-bit Wallace Tree Multiplier Using Reversible Logic". International Journal of Engineering and Manufacturing 12, nr 4 (8.08.2022): 29–36. http://dx.doi.org/10.5815/ijem.2022.04.03.

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49

Akbar, Ehsan Pour Ali, Majid Haghparast i Keivan Navi. "Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology". Microelectronics Journal 42, nr 8 (sierpień 2011): 973–81. http://dx.doi.org/10.1016/j.mejo.2011.05.007.

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50

Nandal, Amita. "Booth Multiplier using Reversible Logic with Low Power and Reduced Logical Complexity". Indian Journal of Science and Technology 7, nr 4 (20.04.2014): 525–29. http://dx.doi.org/10.17485/ijst/2014/v7i4.15.

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