Gotowe bibliografie tematyczne / Reconfigurable Hardware Architecture

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Gotowa bibliografia na temat „Reconfigurable Hardware Architecture”

Autor: Grafiati
Data publikacji: 6 września 2023

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Artykuły w czasopismach na temat "Reconfigurable Hardware Architecture"

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Thomas, Alexander, Michael Rückauer i Jürgen Becker. "HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture". International Journal of Reconfigurable Computing 2012 (2012): 1–17. http://dx.doi.org/10.1155/2012/832531.

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Since the introduction of the first reconfigurable devices in 1985 the field of reconfigurable computing developed a broad variety of architectures from fine-grained to coarse-grained types. However, the main disadvantages of the reconfigurable approaches, the costs in area, and power consumption, are still present. This contribution presents a solution for application-driven adaptation of our reconfigurable architecture at register transfer level (RTL) to reduce the resource requirements and power consumption while keeping the flexibility and performance for a predefined set of applications. Furthermore, implemented runtime adaptive features like online routing and configuration sequencing will be presented and discussed. A presentation of the prototype chip of this architecture designed in 90 nm standard cell technology manufactured by TSMC will conclude this contribution.
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Siddiqui, Ali Shuja, Yutian Gui i Fareena Saqib. "Secure Boot for Reconfigurable Architectures". Cryptography 4, nr 4 (25.09.2020): 26. http://dx.doi.org/10.3390/cryptography4040026.

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Reconfigurable computing is becoming ubiquitous in the form of consumer-based Internet of Things (IoT) devices. Reconfigurable computing architectures have found their place in safety-critical infrastructures such as the automotive industry. As the target architecture evolves, it also needs to be updated remotely on the target platform. This process is susceptible to remote hijacking, where the attacker can maliciously update the reconfigurable hardware target with tainted hardware configuration. This paper proposes an architecture of establishing Root of Trust at the hardware level using cryptographic co-processors and Trusted Platform Modules (TPMs) and enable over the air updates. The proposed framework implements a secure boot protocol on Xilinx based FPGAs. The project demonstrates the configuration of the bitstream, boot process integration with TPM and secure over-the-air updates for the hardware reconfiguration.
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Fabiani, Erwan. "Experiencing a Problem-Based Learning Approach for Teaching Reconfigurable Architecture Design". International Journal of Reconfigurable Computing 2009 (2009): 1–11. http://dx.doi.org/10.1155/2009/923415.

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This paper presents the “reconfigurable computing” teaching part of a computer science master course (first year) on parallel architectures. The practical work sessions of this course rely on active pedagogy using problem-based learning, focused on designing a reconfigurable architecture for the implementation of an application class of image processing algorithms. We show how the successive steps of this project permit the student to experiment with several fundamental concepts of reconfigurable computing at different levels. Specific experiments include exploitation of architectural parallelism, dataflow and communicating component-based design, and configurability-specificity tradeoffs.
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Pionteck, Thilo, Roman Koch, Carsten Albrecht i Erik Maehle. "A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime". International Journal of Reconfigurable Computing 2009 (2009): 1–10. http://dx.doi.org/10.1155/2009/942930.

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Runtime reconfigurable system-on-chip designs for FPGAs pose manifold demands on the underlying system architecture and design tool capabilities. The system architecture has to support varying communication needs of a changing number of processing units mapped onto diverse locations. Design tools should support an arbitrary placement of processing modules and the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules. While few works address the design of flexible system architectures, the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules is hardly ever considered due to design tool limitations. In this paper, a technique for circumventing this restriction is presented. It allows for a rededication of the reconfigurable area to a different number of individually sized reconfigurable regions. This technique is embedded in the design flow of a runtime reconfigurable system architecture for Xilinx Virtex-4 FPGAs. The system architecture will also be presented to provide a realistic application example.
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Göhringer, Diana, Thomas Perschke, Michael Hübner i Jürgen Becker. "A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip". International Journal of Reconfigurable Computing 2009 (2009): 1–11. http://dx.doi.org/10.1155/2009/395018.

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Runtime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world. The runtime exchange of modules, implemented on a reconfigurable hardware, affects the instruction flow (e.g., in reconfigurable instruction set processors) or the data flow, which has a strong impact on the performance of an application. Furthermore, the choice of a certain processor architecture related to the class of target applications is a crucial point in application development. A simple example is the domain of high-performance computing applications found in meteorology or high-energy physics, where vector processors are the optimal choice. A classification scheme for computer systems was provided in 1966 by Flynn where single/multiple data and instruction streams were combined to four types of architectures. This classification is now used as a foundation for an extended classification scheme including runtime adaptivity as further degree of freedom for processor architecture design. The developed scheme is validated by a multiprocessor system implemented on reconfigurable hardware as well as by a classification of existing static and reconfigurable processor systems.
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Wijtvliet, Mark, Henk Corporaal i Akash Kumar. "CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures". ACM Transactions on Reconfigurable Technology and Systems 14, nr 4 (31.12.2021): 1–28. http://dx.doi.org/10.1145/3468874.

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Reconfigurable architectures are quickly gaining in popularity due to their flexibility and ability to provide high energy efficiency. However, reconfigurable systems allow for a huge design space. Iterative design space exploration (DSE) is often required to achieve good Pareto points with respect to some combination of performance, area, and/or energy. DSE tools depend on information about hardware characteristics in these aspects. These characteristics can be obtained from hardware synthesis and net-list simulation, but this is very time-consuming. Therefore, architecture models are common. This work introduces CGRA-EAM (Coarse-Grained Reconfigurable Architecture - Energy & Area Model), a model for energy and area estimation framework for coarse-grained reconfigurable architectures. The model is evaluated for the Blocks CGRA. The results demonstrate that the mean absolute percentage error is 15.5% and 2.1% for energy and area, respectively, while the model achieves a speedup of close to three orders of magnitude compared to synthesis.
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Voss, Nils, Bastiaan Kwaadgras, Oskar Mencer, Wayne Luk i Georgi Gaydadjiev. "On Predictable Reconfigurable System Design". ACM Transactions on Architecture and Code Optimization 18, nr 2 (marzec 2021): 1–28. http://dx.doi.org/10.1145/3436995.

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We propose a design methodology to facilitate rigorous development of complex applications targeting reconfigurable hardware. Our methodology relies on analytical estimation of system performance and area utilisation for a given specific application and a particular system instance consisting of a controlflow machine working in conjunction with one or more reconfigurable dataflow accelerators. The targeted application is carefully analyzed, and the parts identified for hardware acceleration are reimplemented as a set of representative software models. Next, with the results of the application analysis, a suitable system architecture is devised and its performance is evaluated to determine bottlenecks, allowing predictable design. The architecture is iteratively refined, until the final version satisfying the specification requirements in terms of performance and required hardware area is obtained. We validate the presented methodology using a widely accepted convolutional neural network (VGG-16) and an important HPC application (BQCD). In both cases, our methodology relieved and alleviated all system bottlenecks before the hardware implementation was started. As a result the architectures were implemented first time right, achieving state-of-the-art performance within 15% of our modelling estimations.
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Craven, Stephen, i Peter Athanas. "Dynamic Hardware Development". International Journal of Reconfigurable Computing 2008 (2008): 1–10. http://dx.doi.org/10.1155/2008/901328.

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Applications that leverage the dynamic partial reconfigurability of modern FPGAs are few, owing in large part to the lack of suitable tools and techniques to create them. While the trend in digital design is towards higher levels of design abstractions, forgoing hardware description languages in some cases for high-level languages, the development of a reconfigurable design requires developers to work at a low level and contend with many poorly documented architecture-specific aspects. This paper discusses the creation of a high-level development environment for reconfigurable designs that leverage an existing high-level synthesis tool to enable the design, simulation, and implementation of dynamically reconfigurable hardware solely from a specification written in C. Unlike previous attempts, this approach encompasses the entirety of design and implementation, enables self-re-configuration through an embedded controller, and inherently handles partial reconfiguration. Benchmarking numbers are provided, which validate the productivity enhancements this approach provides.
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NAKANO, KOJI. "A BIBLIOGRAPHY OF PUBLISHED PAPERS ON DYNAMICALLY RECONFIGURABLE ARCHITECTURES". Parallel Processing Letters 05, nr 01 (marzec 1995): 111–24. http://dx.doi.org/10.1142/s0129626495000102.

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A dynamically reconfigurable architecture is a parallel computer architecture that supports a physical switching of communication patterns during a computation. Basically, the dynamically reconfigurable architecture consists of locally controllable switches, which enables flexible-connection patterns of the network. The bibliography attempts to classify published papers on dynamically reconfigurable architectures according to the problems that are dealt with.
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Purohit, Gaurav, Kota Solomon Raju i Vinod Kumar Chaubey. "XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware". International Journal of Reconfigurable Computing 2016 (2016): 1–8. http://dx.doi.org/10.1155/2016/9128683.

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This paper presents a novel XOR-FREE algorithm to implement the convolutional encoder using reconfigurable hardware. The approach completely removes the XOR processing of a chosen nonsystematic, feedforward generator polynomial of larger constraint length. The hardware (HW) implementation of new architecture uses Lookup Table (LUT) for storing the parity bits. The design implements architectural reconfigurability by modifying the generator polynomial of the same constraint length and code rate to reduce the design complexity. The proposed architecture reduces the dynamic power up to 30% and improves the hardware cost and propagation delay up to 20% and 32%, respectively. The performance of the proposed architecture is validated in MATLAB Simulink and tested on Zynq-7 series FPGA.
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Rozprawy doktorskie na temat "Reconfigurable Hardware Architecture"

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Gelb, Benjamin S. "A timeshared, runtime reconfigurable hardware co-processing architecture". Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/53147.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.
Includes bibliographical references (leaves 73-74).
The constant desire for increased performance in microprocessor systems has led to the need for specialized hardware cores to accelerate specific computational tasks. In this thesis, we explore the potential of using FPGA partial reconfiguration to create a platform for customized hardware cores that may be loaded on demand, at runtime, and replaced when not in use. We implement two new software tools, bitparse and bitrender, to demonstrate the bitstream relocation technique. Further, we present a functional microprocessor system coupled with a runtime reprogramable peripheral synthesized on a Xilinx Virtex-5 FPGA and discuss its performance implications.
by Benjamin S. Gelb.
M.Eng.
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Peterkin, Raymond. "A reconfigurable hardware architecture for VPN MPLS based services". Thesis, University of Ottawa (Canada), 2006. http://hdl.handle.net/10393/27283.

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Internet applications are becoming increasingly resource intensive and perform poorly in the presence of significant congestion. Increased bandwidth cannot provide long-term congestion relief so Internet traffic must be prioritized and efficiently routed. Multiprotocol Label Switching (MPLS) [12] provides the means to process traffic quickly and reserve resources for applications with specific requirements. However, MPLS must provide the same resilience mechanisms as ATM [18] over SONET [46] to become an acceptable alternative for assigning and switching label switched paths (LSPs). This thesis proposes a reconfigurable architecture and a prototype of a hardware processor for MPLS to improve its overall performance. Establishing LSPs and label management are the central tasks of the processor. It is used to describe LSPs and perform packet switching. A significant subset of RSVP-TE is implemented in the processor to provide the necessary mechanisms of a signaling protocol. Functionality is also available for Traffic Engineering (TE) allowing a user to configure the allocation of resources available for MPLS. The processor is designed to interact with software so it can become part of an embedded system. Results and analysis for the processor are provided describing its resource usage and performance. Resource intensive tasks are identified through analysis and determinations are made about the worst case performance improvement compared to software implementations which depend on the number of LSPs considered and network size.
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Diniz, Claudio Machado. "Dedicated and reconfigurable hardware accelerators for high efficiency video coding standard". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/118394.

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A demanda por vídeos de resolução ultra-alta (além de 1920x1080 pontos) levou à necessidade de desenvolvimento de padrões de codificação de vídeo novos e mais eficientes para prover alta eficiência de compressão. O novo padrão High Efficiency Video Coding (HEVC), publicado em 2013, atinge o dobro da eficiência de compressão (ou 50% de redução no tamanho do vídeo codificado) comparado com o padrão mais eficiente até então, e mais utilizado no mercado, o padrão H.264/AVC (Advanced Video Coding). O HEVC atinge este resultado ao custo de uma elevação da complexidade computacional das ferramentas inseridas no codificador e decodificador. O aumento do esforço computacional do padrão HEVC e as limitações de potência das tecnologias de fabricação em silício atuais tornam essencial o desenvolvimento de aceleradores de hardware para partes importantes da aplicação do HEVC. Aceleradores de hardware fornecem maior desempenho e eficiência energética para aplicações específicas que os processadores de propósito geral. Uma análise da aplicação do HEVC realizada neste trabalho identificou as partes mais importantes do HEVC do ponto de vista do esforço computacional, a saber, o Filtro de Interpolação de Ponto Fracionário, o Filtro de Deblocagem e o cálculo da Soma das Diferenças Absolutas. Uma análise de tempo de execução do Filtro de Interpolação indica um grande potencial de economia de potência/energia pela adaptação do acelerador de hardware à carga de trabalho variável. Esta tese introduz novas contribuições no tema de aceleradores dedicados e reconfiguráveis para o padrão HEVC. Aceleradores de hardware dedicados para o Filtro de Interpolação de Pixel Fracionário, para o Filtro de Deblocagem, e para o cálculo da Soma das Diferenças Absolutas, são propostos, projetados e avaliados nesta tese. A arquitetura de hardware proposta para o filtro de interpolação atinge taxa de processamento similar ao estado da arte, enquanto reduz a área do hardware para este bloco em 50%. A arquitetura de hardware proposta para o filtro de deblocagem também atinge taxa de processamento similar ao estado da arte com uma redução de 5X a 6X na contagem de gates e uma redução de 3X na dissipação de potência. A nova análise comparativa proposta para os elementos de processamento do cálculo da Soma das Diferenças Absolutas introduz diversas alternativas de projeto de arquitetura com diferentes resultados de área, desempenho e potência. A nova arquitetura reconfigurável para o filtro de interpolação do padrão HEVC fornece 57% de redução de área em tempo de projeto e adaptação da potência/energia em tempo-real a cada imagem processada, o que ainda não é suportado pelas arquiteturas do estado da arte para o filtro de interpolação. Adicionalmente, a tese propõe um novo esquema de alocação de aceleradores em tempo-real para arquiteturas reconfiguráveis baseadas em tiles de processamento e de grão-misto, o que reduz em 44% (23% em média) o “overhead” de comunicação comparado com uma estratégia first-fit com reuso de datapaths, para números diferentes de tiles e organizações internas de tile. Este esquema de alocação leva em conta a arquitetura interna para alocar aceleradores de uma maneira mais eficiente, evitando e minimizando a comunicação entre tiles. Os aceleradores e técnicas dedicadas e reconfiguráveis propostos nesta tese proporcionam implementações de codificadores de vídeo de nova geração, além do HEVC, com melhor área, desempenho e eficiência em potência.
The demand for ultra-high resolution video (beyond 1920x1080 pixels) led to the need of developing new and more efficient video coding standards to provide high compression efficiency. The High Efficiency Video Coding (HEVC) standard, published in 2013, reaches double compression efficiency (or 50% reduction in size of coded video) compared to the most efficient video coding standard at that time, and most used in the market, the H.264/AVC (Advanced Video Coding) standard. HEVC reaches this result at the cost of high computational effort of the tools included in the encoder and decoder. The increased computational effort of HEVC standard and the power limitations of current silicon fabrication technologies makes it essential to develop hardware accelerators for compute-intensive computational kernels of HEVC application. Hardware accelerators provide higher performance and energy efficiency than general purpose processors for specific applications. An HEVC application analysis conducted in this work identified the most compute-intensive kernels of HEVC, namely the Fractional-pixel Interpolation Filter, the Deblocking Filter and the Sum of Absolute Differences calculation. A run-time analysis on Interpolation Filter indicates a great potential of power/energy saving by adapting the hardware accelerator to the varying workload. This thesis introduces new contributions in the field of dedicated and reconfigurable hardware accelerators for HEVC standard. Dedicated hardware accelerators for the Fractional Pixel Interpolation Filter, the Deblocking Filter and the Sum of Absolute Differences calculation are herein proposed, designed and evaluated. The interpolation filter hardware architecture achieves throughput similar to the state of the art, while reducing hardware area by 50%. Our deblocking filter hardware architecture also achieves similar throughput compared to state of the art with a 5X to 6X reduction in gate count and 3X reduction in power dissipation. The thesis also does a new comparative analysis of Sum of Absolute Differences processing elements, in which various architecture design alternatives with different area, performance and power results were introduced. A novel reconfigurable interpolation filter hardware architecture for HEVC standard was developed, and it provides 57% design-time area reduction and run-time power/energy adaptation in a picture-by-picture basis, compared to the state-of-the-art. Additionally a run-time accelerator binding scheme is proposed for tile-based mixed-grained reconfigurable architectures, which reduces the communication overhead, compared to first-fit strategy with datapath reusing scheme, by up to 44% (23% on average) for different number of tiles and internal tile organizations. This run-time accelerator binding scheme is aware of the underlying architecture to bind datapaths in an efficient way, to avoid and minimize inter-tile communications. The new dedicated and reconfigurable hardware accelerators and techniques proposed in this thesis enable next-generation video coding standard implementations beyond HEVC with improved area, performance, and power efficiency.
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Kung, Ling-Pei 1961. "Obtaining performance and programmability using reconfigurable hardware for media processing". Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/61855.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, School of Architecture and Planning, Program in Media Arts and Sciences, 2002.
Includes bibliographical references (p. 127-132).
An imperative requirement in the design of a reconfigurable computing system or in the development of a new application on such a system is performance gains. However, such developments suffer from long-and-difficult programming process, hard-to-predict performance gains, and limited scope of applications. To address these problems, we need to understand reconfigurable hardware's capabilities and limitations, its performance advantages and disadvantages, re-think reconfigurable system architectures, and develop new tools to explore its utility. We begin by examining performance contributors at the system level. We identify those from general-purpose and those from dedicated components. We propose an architecture by integrating reconfigurable hardware within the general-purpose framework. This is to avoid and minimize dedicated hardware and organization for programmability. We analyze reconfigurable logic architectures and their performance limitations. This analysis leads to a theory that reconfigurable logic can never be clocked faster than a fixed-logic design based on the same fabrication technology. Though highly unpredictable, we can obtain a quick upper bound estimate on the clock speed based on a few parameters. We also analyze microprocessor architectures and establish an analytical performance model. We use this model to estimate performance bounds using very little information on task properties. These bounds help us to detect potential memory-bound tasks. For a compute-bound task, we compare its performance upper bound with the upper bound on reconfigurable clock speed to further rule out unlikely speedup candidates.
(cont.) These performance estimates require very few parameters, and can be quickly obtained without writing software or hardware codes. They can be integrated with design tools as front end tools to explore speedup opportunities without costly trials. We believe this will broaden the applicability of reconfigurable computing.
by Ling-Pei Kung.
Ph.D.
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Balasubramanian, Karthikeyan. "Reconfigurable System-on-Chip Architecture for Neural Signal Processing". Diss., Temple University Libraries, 2011. http://cdm16002.contentdm.oclc.org/cdm/ref/collection/p245801coll10/id/144255.

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Electrical Engineering
Ph.D.
Analyzing the brain's behavior in terms of its neuronal activity is the fundamental purpose of Brain-Machine Interfaces (BMIs). Neuronal activity is often assumed to be encoded in the rate of neuronal action potential spikes. Successful performance of a BMI system is tied to the efficiency of its individual processing elements such as spike detection, sorting and decoding. To achieve reliable operation, BMIs are equipped with hundreds of electrodes at the neural interface. While a single electrode/tetrode communicates with up to four neurons at a given instant of time, a typical interface communicates with an ensemble of hundreds or even thousands of neurons. However, translation of these signals (data) into usable information for real-time BMIs is bottlenecked due to the lack of efficient real-time algorithms and real-time hardware that can handle massively parallel channels of neural data. The research presented here addresses this issue by developing real-time neural processing algorithms that can be implemented in reconfigurable hardware and thus, can be scaled to handle thousands of channels in parallel. The developed reconfigurable system serves as an evaluation platform for investigating the fundamental design tradeoffs in allocating finite hardware resources for a reliable BMI. In this work, the generic architectural layout needed to process neural signals in a massive scale is discussed. A System-on-Chip design with embedded system architecture is presented for FPGA hardware realization that features (a) scalability (b) reconfigurability, and (c) real-time operability. A prototype design incorporating a dual processor system and essential neural signal processing routines such as real-time spike detection and sorting is presented. Two kinds of spike detectors, a simple threshold-based and non-linear energy operator-based, were implemented. To achieve real-time spike sorting, a fuzzy logic-based spike sorter was developed and synthesized in the hardware. Furthermore, a real-time kernel to monitor the high-level interactions of the system was implemented. The entire system was realized in a platform FPGA (Xilinx Virtex-5 LX110T). The system was tested using extracellular neural recordings from three different animals, a owl monkey, a macaque and a rat. Operational performance of the system is demonstrated for a 300 channel neural interface. Scaling the system to 900 channels is trivial.
Temple University--Theses
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Lomonaco, Michael John. "CRYPTARRAY A SCALABLE AND RECONFIGURABLE ARCHITECTURE FOR CRYPTOGRAPHIC APPLICATIONS". Master's thesis, University of Central Florida, 2004. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4394.

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Cryptography is increasingly viewed as a critical technology to fulfill the requirements of security and authentication for information exchange between Internet applications. However, software implementations of cryptographic applications are unable to support the quality of service from a bandwidth perspective required by most Internet applications. As a result, various hardware implementations, from Application-Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), to programmable processors, were proposed to improve this inadequate quality of service. Although these implementations provide performances that are considered better than those produced by software implementations, they still fall short of addressing the bandwidth requirements of most cryptographic applications in the context of the Internet for two major reasons: (i) The majority of these architectures sacrifice flexibility for performance in order to reach the performance level needed for cryptographic applications. This lack of flexibility can be detrimental considering that cryptographic standards and algorithms are still evolving. (ii) These architectures do not consider the consequences of technology scaling in general, and particularly interconnect related problems. As a result, this thesis proposes an architecture that attempts to address the requirements of cryptographic applications by overcoming the obstacles described in (i) and (ii). To this end, we propose a new reconfigurable, two-dimensional, scalable architecture, called CRYPTARRAY, in which bus-based communication is replaced by distributed shared memory communication. At the physical level, the length of the wires will be kept to a minimum. CRYPTARRAY is organized as a chessboard in which the dark and light squares represent Processing Elements (PE) and memory blocks respectively. The granularity and resource composition of the PEs is specifically designed to support the computing operations encountered in cryptographic algorithms in general, and symmetric algorithms in particular. Communication can occur only between neighboring PEs through locally shared memory blocks. Because of the chessboard layout, the architecture can be reconfigured to allow computation to proceed as a pipelined wave in any direction. This organization offers a high computational density in terms of datapath resources and a large number of distributed storage resources that easily support a high degree of parallelism and pipelining. Experimental prototyping a small array on FPGA chips shows that this architecture can run at 80.9 MHz producing 26,968,716 outputs every second in static reconfiguration mode and 20,226,537 outputs every second in dynamic reconfiguration mode.
M.S.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical and Computer Engineering
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Avakian, Annie. "Reducing Cache Access Time in Multicore Architectures Using Hardware and Software Techniques". University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1335461322.

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Silva, Antonio Carlos Fernandes da. "ChipCflow: tool for convert C code in a static dataflow architecture in reconfigurable hardware". Universidade de São Paulo, 2015. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-30062015-141638/.

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A growing search for alternative architectures and softwares have been noted in the last years. This search happens due to the advance of hardware technology and such advances must be complemented by innovations on design methodologies, test and verification techniques in order to use technology effectively. Alternative architectures and softwares, in general, explores the parallelism of applications, differently to Von Neumann model. Among high performance alternative architectures, there is the Dataflow Architecture. In this kind of architecture, the process of program execution is determined by data availability, thus the parallelism is intrinsic in these systems. The dataflow architectures become again a highlighted search area due to hardware advances, in particular, the advances of Reconfigurable Computing and Field Programmable Gate Arrays (FPGAs). ChipCflow projet is a tool for execution of algorithms using dynamic dataflow graph in FPGA. In this thesis, the development of a code conversion tool to generate aplications in a static dataflow architecture, is described. Also the ChipCflow project where the code conversion tool is part, is presented. The specification of algorithm to be converted is made in C language and converted to a hadware description language, respecting the proposed by ChipCflow project. The results are the proof of concept of converting a high-level language code for dataflow architecture to be used into a FPGA.
Existe uma crescente busca por softwares e arquiteturas alternativas. Essa busca acontece pois houveram avanços na tecnologia do hardware, e estes avanços devem ser complementados por inovações nas metodologias de projetos, testes e verificação para que haja um uso eficaz da tecnologia. Os software e arquiteturas alternativas, geralmente são modelos que exploram o paralelismo das aplicações, ao contrário do modelo de Von Neumann. Dentre as arquiteturas alternativas de alto desempenho, tem-se a arquitetura a fluxo de dados. Nesse tipo de arquitetura, o processo de execução de programas é determinado pela disponibilidade dos dados, logo o paralelismo está embutido na própria natureza do sistema. O modelo a fluxo de dados possui a vantagem de expressar o paralelismo de maneira intrínseca, eliminando a necessidade do programador explicitar em seu código os trechos onde deve haver paralelismo. As arquiteturas a fluxo de dados voltaram a ser uma área de pesquisa devido aos avanços do hardware, em particular, os avanços da Computação Reconfigurável e dos Field Programmable Gate Arrays (FPGAs).Nesta tese é descrita uma ferramenta de conversão de código que visa a geração de aplicações utilizando uma arquitetura a fluxo de dados estática. Também é descrito o projeto ChipCflow, cuja ferramenta de conversão de código, descrita nesta tese, é parte integrante. A especificação do algoritmo a ser convertido é feita em linguagem C e convertida para uma linguagem de descrição de hardware, respeitando o modelo proposto pelo ChipCflow. Os resultados alcançados visam a prova de conceito da conversão de código de uma linguagem de alto nível para uma arquitetura a fluxo de dados a ser configurada em FPGA.
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Robinson, Kylan Thomas. "An integrated development environment for the design and simulation of medium-grain reconfigurable hardware". Pullman, Wash. : Washington State University, 2010. http://www.dissertations.wsu.edu/Thesis/Spring2010/k_robinson_041510.pdf.

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Streszczenie:
Thesis (M.S. in computer engineering)--Washington State University, May 2010.
Title from PDF title page (viewed on June 22, 2010). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 75-76).
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Das, Satyajit. "Architecture and Programming Model Support for Reconfigurable Accelerators in Multi-Core Embedded Systems". Thesis, Lorient, 2018. http://www.theses.fr/2018LORIS490/document.

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Streszczenie:
La complexité des systèmes embarqués et des applications impose des besoins croissants en puissance de calcul et de consommation énergétique. Couplé au rendement en baisse de la technologie, le monde académique et industriel est toujours en quête d'accélérateurs matériels efficaces en énergie. L'inconvénient d'un accélérateur matériel est qu'il est non programmable, le rendant ainsi dédié à une fonction particulière. La multiplication des accélérateurs dédiés dans les systèmes sur puce conduit à une faible efficacité en surface et pose des problèmes de passage à l'échelle et d'interconnexion. Les accélérateurs programmables fournissent le bon compromis efficacité et flexibilité. Les architectures reconfigurables à gros grains (CGRA) sont composées d'éléments de calcul au niveau mot et constituent un choix prometteur d'accélérateurs programmables. Cette thèse propose d'exploiter le potentiel des architectures reconfigurables à gros grains et de pousser le matériel aux limites énergétiques dans un flot de conception complet. Les contributions de cette thèse sont une architecture de type CGRA, appelé IPA pour Integrated Programmable Array, sa mise en œuvre et son intégration dans un système sur puce, avec le flot de compilation associé qui permet d'exploiter les caractéristiques uniques du nouveau composant, notamment sa capacité à supporter du flot de contrôle. L'efficacité de l'approche est éprouvée à travers le déploiement de plusieurs applications de traitement intensif. L'accélérateur proposé est enfin intégré à PULP, a Parallel Ultra-Low-Power Processing-Platform, pour explorer le bénéfice de ce genre de plate-forme hétérogène ultra basse consommation
Emerging trends in embedded systems and applications need high throughput and low power consumption. Due to the increasing demand for low power computing and diminishing returns from technology scaling, industry and academia are turning with renewed interest toward energy efficient hardware accelerators. The main drawback of hardware accelerators is that they are not programmable. Therefore, their utilization can be low is they perform one specific function and increasing the number of the accelerators in a system on chip (SoC) causes scalability issues. Programmable accelerators provide flexibility and solve the scalability issues. Coarse-Grained Reconfigurable Array (CGRA) architecture consisting of several processing elements with word level granularity is a promising choice for programmable accelerator. Inspired by the promising characteristics of programmable accelerators, potentials of CGRAs in near threshold computing platforms are studied and an end-to-end CGRA research framework is developed in this thesis. The major contributions of this framework are: CGRA design, implementation, integration in a computing system, and compilation for CGRA. First, the design and implementation of a CGRA named Integrated Programmable Array (IPA) is presented. Next, the problem of mapping applications with control and data flow onto CGRA is formulated. From this formulation, several efficient algorithms are developed using internal resources of a CGRA, with a vision for low power acceleration. The algorithms are integrated into an automated compilation flow. Finally, the IPA accelerator is augmented in PULP - a Parallel Ultra-Low-Power Processing-Platform to explore heterogeneous computing
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Książki na temat "Reconfigurable Hardware Architecture"

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N, Mahapatra Rabi, red. Design of low-power coarse-grained reconfigurable architectures. Boca Raton, FL: CRC Press, 2011.

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Nedjah, Nadia, i Chao Wang. Reconfigurable and Adaptive Computing: Theory and Applications. Taylor & Francis Group, 2018.

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Nedjah, Nadia, i Chao Wang. Reconfigurable and Adaptive Computing: Theory and Applications. Taylor & Francis Group, 2018.

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Reconfigurable and Adaptive Computing: Theory and Applications. Taylor & Francis Group, 2018.

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Reconfigurable and Adaptive Computing: Theory and Applications. Taylor & Francis Group, 2018.

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Nedjah, Nadia, i Chao Wang. Reconfigurable and Adaptive Computing: Theory and Applications. Taylor & Francis Group, 2018.

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Mahapatra, Rabi N., i Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2010.

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Mahapatra, Rabi N., i Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2017.

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Mahapatra, Rabi N., i Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2010.

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Mahapatra, Rabi N., i Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2010.

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Części książek na temat "Reconfigurable Hardware Architecture"

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Liu, Leibo, Bo Wang i Shaojun Wei. "Hardware Architecture of Reconfigurable Cryptographic Processors". W Reconfigurable Cryptographic Processor, 133–67. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8899-5_3.

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Thomas, Alexander, i Jürgen Becker. "Development and Synthesis of Adaptive Multi-grained Reconfigurable Hardware Architecture for Dynamic Function Patterns". W Dynamically Reconfigurable Systems, 3–24. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-3485-4_1.

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Goodman, James, i Anantha Chandrakasan. "An Energy Efficient Reconfigurable Public-Key Cryptography Processor Architecture". W Cryptographic Hardware and Embedded Systems — CHES 2000, 175–90. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-44499-8_13.

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Chen, Mengdong, Xiujiang Ren i Xianghui Xie. "An Efficient Rule Processing Architecture Based on Reconfigurable Hardware". W Communications in Computer and Information Science, 22–33. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-1850-8_3.

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Baidya, Paresh, Rourab Paul i Suman Sau. "High-Speed Loop Unrolled Grain Architecture in Reconfigurable Hardware". W Advances in Intelligent Systems and Computing, 165–73. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-1483-8_15.

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Nakada, Hiroshi, Kiyoshi Oguri, Norbert Imlig, Minoru Inamori, Ryusuke Koniski, Hideyuki Ito, Kouichi Nagami i Tsunemichi Shiozawa. "Plastic cell architecture: A dynamically reconfigurable hardware-based computer". W Lecture Notes in Computer Science, 679–87. Berlin, Heidelberg: Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/bfb0097953.

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Nedjah, Nadia, i Luiza de Macedo Mourelle. "Reconfigurable Hardware Architecture for Compact and Efficient Stochastic Neuron". W Artificial Neural Nets Problem Solving Methods, 17–24. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/3-540-44869-1_3.

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Knieper, Tobias, Paul Kaufmann, Kyrre Glette, Marco Platzner i Jim Torresen. "Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture". W Evolvable Systems: From Biology to Hardware, 250–61. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-15323-5_22.

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Ahn, Seong-Yong, Jun-Yong Kim i Jeong-A. Lee. "Heuristic Algorithm for Reducing Mapping Sets of Hardware-Software Partitioning in Reconfigurable System". W Advances in Computer Systems Architecture, 102–14. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30102-8_9.

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Weng, Sheng-Kai, Chien-Min Ou i Wen-Jyi Hwang. "VLSI Architecture for Fast Memetic Vector Quantizer Design on Reconfigurable Hardware". W Algorithms and Architectures for Parallel Processing, 513–24. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-03095-6_49.

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Streszczenia konferencji na temat "Reconfigurable Hardware Architecture"

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Ahmad, B., A. T. Erdogan i S. Khawam. "Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC". W First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06). IEEE, 2006. http://dx.doi.org/10.1109/ahs.2006.25.

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Rodriguez, Vladimir, Jose F. Martinez, Jesus A. Carrasco, Manuel S. Lazo, Rene Cumplido i Claudia Feregrino Uribe. "A hardware architecture for filtering irreducible testors". W 2014 International Conference on Reconfigurable Computing and FPGAs (ReConFig14). IEEE, 2014. http://dx.doi.org/10.1109/reconfig.2014.7032526.

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Wang, Ying, Jian Yan, Xuegong Zhou, Lingli Wang, Wayne Luk, Chenglian Peng i Jiarong Tong. "A partially reconfigurable architecture supporting hardware threads". W 2012 International Conference on Field-Programmable Technology (FPT 2012). IEEE, 2012. http://dx.doi.org/10.1109/fpt.2012.6412147.

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Jung, Yong-kyu. "A Hardware/Software Co-reconfigurable Multimedia Architecture". W 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia. IEEE, 2006. http://dx.doi.org/10.1109/estmed.2006.321277.

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Li, Zhijing, Yuwei Ye, Stephen Neuendorffer i Adrian Sampson. "Compiler-Driven Simulation of Reconfigurable Hardware Accelerators". W 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE, 2022. http://dx.doi.org/10.1109/hpca53966.2022.00052.

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Tasdizen, O., H. Kukner, A. Akin i I. Hamzaoglu. "A high performance reconfigurable Motion Estimation hardware architecture". W 2009 Design, Automation & Test in Europe Conference & Exhibition (DATE'09). IEEE, 2009. http://dx.doi.org/10.1109/date.2009.5090787.

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Dias, Mauricio A., i Fernando S. Osorio. "Reconfigurable Hardware Architecture for Vision-Based Driving Systems". W 2015 12th Latin American Robotics Symposium (LARS) and 2015 3rd Brazilian Symposium on Robotics (LARS-SBR). IEEE, 2015. http://dx.doi.org/10.1109/lars-sbr.2015.65.

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Pedraza, Cesar, Emilio Castillo, Javier Castillo, Cristobal Camarero, Jose L. Bosque, Jose I. Martinez i Rafael Menendez. "Cluster architecture based on low cost reconfigurable hardware". W 2008 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2008. http://dx.doi.org/10.1109/fpl.2008.4630017.

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Khalil, Kasem, Omar Eldash, Bappaditya Dey, Ashok Kumar i Magdy Bayoumi. "A Novel Reconfigurable Hardware Architecture of Neural Network". W 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2019. http://dx.doi.org/10.1109/mwscas.2019.8884809.

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Tu, Fengbin, Shouyi Yin, Peng Ouyang, Leibo Liu i Shaojun Wei. "RNA: A Reconfigurable Architecture for Hardware Neural Acceleration". W Design, Automation and Test in Europe. New Jersey: IEEE Conference Publications, 2015. http://dx.doi.org/10.7873/date.2015.0414.

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