Gotowa bibliografia na temat „Pre-silicon evaluation”
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Artykuły w czasopismach na temat "Pre-silicon evaluation"
Radue, C., i E. E. van Dyk. "Pre-deployment evaluation of amorphous silicon photovoltaic modules". Solar Energy Materials and Solar Cells 91, nr 2-3 (styczeń 2007): 129–36. http://dx.doi.org/10.1016/j.solmat.2006.07.007.
Pełny tekst źródłaLatukhina, N. V., D. A. Pisarenko, A. V. Volkov i V. A. Kitaeva. "PHOTOSENSITIVE MATRIX BASED ON POROUS MICROCRYSTALLINE SILICON". Vestnik of Samara University. Natural Science Series 17, nr 5 (14.06.2017): 115–21. http://dx.doi.org/10.18287/2541-7525-2011-17-5-115-121.
Pełny tekst źródłaKim, Gyu Hyun, Geun Min Choi i Young Wook Song. "Evaluation of Wafer Drying Methods for GIGA-LEVEL Device Fabrication". Solid State Phenomena 103-104 (kwiecień 2005): 67–70. http://dx.doi.org/10.4028/www.scientific.net/ssp.103-104.67.
Pełny tekst źródłaGuilley, Sylvain, Khaled Karray, Thomas Perianin, Ritu-Ranjan Shrivastwa, Youssef Souissi i Sofiane Takarabt. "Side-Channel Evaluation Methodology on Software". Cryptography 4, nr 4 (25.09.2020): 27. http://dx.doi.org/10.3390/cryptography4040027.
Pełny tekst źródłaWillems, Geert, i Herman Maes. "Evaluation of a Pre-Objective Scan System for the Laser Recrystallization of Silicon on Insulator Material". Japanese Journal of Applied Physics 31, Part 1, No. 8 (15.08.1992): 2631–39. http://dx.doi.org/10.1143/jjap.31.2631.
Pełny tekst źródłaHossain, Sk Saddam, Soumya Sarkar, Naresh Kr Oraon i Ashok Ranjan. "Pre-ceramic polymer-derived open/closed cell silicon carbide foam: microstructure, phase evaluation, and thermal properties". Journal of Materials Science 51, nr 21 (20.07.2016): 9865–78. http://dx.doi.org/10.1007/s10853-016-0220-1.
Pełny tekst źródłaZaman, Muhammad Yousuf, Denis Perrone, Sergio Ferrero, Luciano Scaltrito i Marco Naretto. "Evaluation of Correct Value of Richardson's Constant by Analyzing the Electrical Behavior of Three Different Diodes at Different Temperatures". Materials Science Forum 711 (styczeń 2012): 174–78. http://dx.doi.org/10.4028/www.scientific.net/msf.711.174.
Pełny tekst źródłaRadun, V., R. P. von Metzen, T. Stieglitz, V. Bucher i A. Stett. "Evaluation of adhesion promoters for Parylene C on gold metallization". Current Directions in Biomedical Engineering 1, nr 1 (1.09.2015): 493–97. http://dx.doi.org/10.1515/cdbme-2015-0118.
Pełny tekst źródłaShibata, Satoshi, Fumitoshi Kawase, Akihiko Kitada, Takashi Kouzaki i Akira Kitamura. "Evaluation of Pre-Amorphized Layer Thickness and Interface Quality of High-Dose Shallow Implanted Silicon by Spectroscopic Ellipsometry". IEEE Transactions on Semiconductor Manufacturing 23, nr 4 (listopad 2010): 545–52. http://dx.doi.org/10.1109/tsm.2010.2072450.
Pełny tekst źródłaGalaktionova, L. V., A. M. Korotkova, N. A. Terekhova, N. I. Voskobulova i S. V. Lebedev. "Evaluation of the use of silicon and iron nanoform for pre-sowing treatment of <i>Pisum sativum</i> seeds". Agrarian science, nr 12 (18.01.2023): 81–86. http://dx.doi.org/10.32634/0869-8155-2022-365-12-81-86.
Pełny tekst źródłaRozprawy doktorskie na temat "Pre-silicon evaluation"
Yao, Yuan. "Towards Comprehensive Side-channel Resistant Embedded Systems". Diss., Virginia Tech, 2021. http://hdl.handle.net/10919/104662.
Pełny tekst źródłaDoctor of Philosophy
Side-channel leakage, which reveals the secret information from the physical effects of computing secret variables, has become a serious vulnerability in secure hardware and software implementations. In side-channel attacks, adversaries passively exploit variations such as power consumption, timing, and electromagnetic emission during the computation with secret variables to retrieve sensitive information. The side-channel attack poses a practical threat to embedded devices, an embedded device's cryptosystem without adequate protection against side-channel leakage can be easily broken by the side-channel attack. In this dissertation, we investigate methodologies to build up comprehensive side-channel resistant embedded systems. However, this is challenging because of the complexity of the embedded system. First, an embedded system integrates a large number of components. Even if the designer can make sure that each component is protected within the system, the integration of the components will possibly introduce new vulnerabilities. Second, the existing side-channel leakage evaluation of embedded system design happens post-silicon and utilizes the measurement on the prototype of the taped-out chip. This is too late for mitigating the vulnerability in the design. Third, due to the complexity of the embedded system, even though the side-channel leakage is detected, it is very hard to precisely locate the root cause within the design. Existing side-channel attack countermeasures are very costly in terms of design overhead. Without a method that can precisely identify the side-channel leakage source within the design, huge overhead will be introduced by blindly add the side-channel countermeasure to the whole design. To make the challenge even harder, the Power Distribution Network (PDN) where the hardware design locates is also vulnerable to side-channel attacks. It has been continuously demonstrated by researchers that attackers can place malicious circuits on a shared PDN with victim design and open the opportunities for the attackers to inject faults or monitoring power changes of the victim circuit. In this dissertation, we address the challenges mentioned above in designing a side-channel-resistant embedded system. We categorize our contributions into three major aspects—first, we investigating the effects of integration of security components and developing corresponding countermeasures. We analyze the vulnerability in a widely used countermeasure - masking, and identify that the random number transfer procedure is a weak link in the integration which can be bypassed by the attacker. We further propose a lightweight protection scheme to protect function calls from instruction skip fault attacks. Second, we developed a novel analysis methodology for pre-silicon side-channel leakage evaluation and root cause analysis. The methodology we developed enables the designer to detect the side-channel leakage at the early pre-silicon design stage, locate the leakage source in the design precisely to the individual gate and apply highly targeted countermeasure with low overhead. Third, we developed a multipurpose on-chip side-channel and fault monitoring extension - Programmable Ring Oscillator (PRO), to further guarantee the security of PDN. PRO can provide on-chip side-channel resistance, power monitoring, and fault detection capabilities to the secure design. We show that PRO as application-independent integrated primitives can provide side-channel and fault countermeasure to the design at a low cost.
Takarabt, Sofiane. "Évaluation pré-silicium de circuits sécurisés face aux attaques par canal auxiliaire". Electronic Thesis or Diss., Institut polytechnique de Paris, 2021. http://www.theses.fr/2021IPPAT015.
Pełny tekst źródłaEmbedded systems are constantly threatened by various attacks, including side-channel attacks. To guarantee a certain level of security, cryptographic implementations must validate evaluation tests recommended by the certification standards, and thus meet the market needs. For this reason, it is necessary to implement reliable countermeasures to counter this type of attacks. However, once these countermeasures are implemented, verification and validation tests can be very costly in terms of time and money. Thus, optimizing the lifecycle of the circuit, between the design stage and the evaluation stage is paramount. We will explore a very broad class of existing attacks (passive and active), and propose methods of pre-silicon level assessments, allowing on the one hand, to detect the different types of leakages that a given attacker can exploit, and on the other hand, expose different techniques to counter these attacks, while respecting the performance and area aspect. In our analyses, we apply formal and empirical methods to track the impact of each vulnerability on the different abstraction levels of the circuit, and thus propose optimal countermeasures
Wu, Yu-hsin, i 吳育星. "Optimization of Signal Integrity by Using Amplitude Adjustment in a Pre-Silicon Full-Transmission Evaluation". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/63144969227910399384.
Pełny tekst źródła國立中央大學
電機工程研究所碩士在職專班
99
In the recent years, as the High definition video and bulk size format data transfer became popular, the Gb/s level high speed differential transmission signals like HDMI, SATA and USB3.0 are instead of the traditional style became more popular in 3C market. The newest generation transmission interface had been developed for this requirement In the Gb/s high speed, these loadings became the major factors for signal integrity. How to estimate the signal integrity of high speed differential pairs is more important for real product in Pre-silicon full-transmission evaluation. In this paper, we defined the PSFTE flow to simulate and analyze the signal integrity from die to far-end in Pre-silicon stage. Then we can use amplitude adjustment method to optimize the signal integrity for different full transmission line. It can avoid not only the extra cost from the version change, the most important is the timing delay will cause more business loss.
Części książek na temat "Pre-silicon evaluation"
Rahman, Ismail Abdul, i Frank L. Riley. "High quality silicon nitride powder derived from Malaysian rice husks". W Chemistry and Technology of Silicon and Tin, 377–83. Oxford University PressOxford, 1992. http://dx.doi.org/10.1093/oso/9780198555803.003.0029.
Pełny tekst źródłaStreszczenia konferencji na temat "Pre-silicon evaluation"
Perdomo, Elias, Alexander Kropotov, Francelly Katherine Cano Ladino, Syed Zafar, Teresa Cervero, Xavier Martorell Bofill i Behzad Salami. "Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs". W RAPIDO '24: Rapid Simulation and Performance Evaluation for Design. New York, NY, USA: ACM, 2024. http://dx.doi.org/10.1145/3642921.3642928.
Pełny tekst źródłaTakarabt, Sofiane, Kais Chibani, Adrien Facon, Sylvain Guilley, Yves Mathieu, Laurent Sauvage i Youssef Souissi. "Pre-silicon Embedded System Evaluation as New EDA Tool for Security Verification". W 2018 IEEE 3rd International Verification and Security Workshop (IVSW). IEEE, 2018. http://dx.doi.org/10.1109/ivsw.2018.8494881.
Pełny tekst źródłaEsposito, C., C. De Martino, S. Lehmann, Zhixing Zhao, M. Schroter i M. Spirito. "Pre-Silicon direct Calibration/De-embedding Evaluation and Device Parameters Uncertainty Estimation". W 2021 97th ARFTG Microwave Measurement Conference (ARFTG). IEEE, 2021. http://dx.doi.org/10.1109/arftg52261.2021.9640156.
Pełny tekst źródłaRusu, Alecsandra, Emilian David, Marina Țopa, Vasile Grosu, Andi Buzo i Georg Pelz. "Improvement and Performance Evaluation of an Adaptive Method for Integrated Circuits Pre-silicon Verification". W 2023 International Symposium on Signals, Circuits and Systems (ISSCS). IEEE, 2023. http://dx.doi.org/10.1109/isscs58449.2023.10190850.
Pełny tekst źródłaNikiforov, Dima, Shengjun Chris Dong, Chengyi Lux Zhang, Seah Kim, Borivoje Nikolic i Yakun Sophia Shao. "RoSÉ: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation". W ISCA '23: 50th Annual International Symposium on Computer Architecture. New York, NY, USA: ACM, 2023. http://dx.doi.org/10.1145/3579371.3589099.
Pełny tekst źródłaTiwari, Santosh K., i Brian K. Paul. "Fabrication of TiO2 and SiO2 Thin Films by Room Temperature Liquid Phase Deposition". W ASME 2007 International Manufacturing Science and Engineering Conference. ASMEDC, 2007. http://dx.doi.org/10.1115/msec2007-31093.
Pełny tekst źródłaNewton, Christopher D., Steven P. Jordan, Martin R. Bache i Louise Gale. "High Temperature Fatigue Assessment of a SiCf/SiC Ceramic Matrix Composite Using Advanced Monitoring Techniques". W ASME Turbo Expo 2019: Turbomachinery Technical Conference and Exposition. American Society of Mechanical Engineers, 2019. http://dx.doi.org/10.1115/gt2019-90355.
Pełny tekst źródłaTedesco, Sarah, Ming Shi, Jason Coryell, Qi Lu i Jianfeng Wang. "New Generation Press Hardening Steels with Tensile Strength of 1.7-2.0 GPa and Enhanced Bendability". W HT2021. ASM International, 2021. http://dx.doi.org/10.31399/asm.cp.ht2021p0180.
Pełny tekst źródłaUme, I. Charles, Jie Gong, Razid Ahmad i Abel Valdes. "Laser Ultrasonic Inspection of Solder Bumps in Flip Chip Packages Using Virtual Package Device as Reference". W ASME 2010 International Mechanical Engineering Congress and Exposition. ASMEDC, 2010. http://dx.doi.org/10.1115/imece2010-39970.
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