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Amberetu, Mathew Atekwana. "Lateral superjunction power MOSFETs". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/MQ63012.pdf.
Pełny tekst źródłaDharmawardana, Kahanawita Gamaethiralalage Padmapani. "High performance power MOSFETs". Thesis, University of Cambridge, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.621963.
Pełny tekst źródłaLeedham, Robert John. "High frequency switching with power MOSFETs". Thesis, University of Cambridge, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.627468.
Pełny tekst źródłaChen, Yuhui. "Resonant Gate Drive Techniques for Power MOSFETs". Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/10099.
Pełny tekst źródłaMaster of Science
Xiangxiang, Fang. "Characterization and Modeling of SiC Power MOSFETs". The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1354687371.
Pełny tekst źródłaLiu, Jingjing Michelle. "Strain induced effects on lateral power MOSFETs". [Gainesville, Fla.] : University of Florida, 2009. http://purl.fcla.edu/fcla/etd/UFE0041290.
Pełny tekst źródłaZupac, Dragan 1961. "ESD-induced noncatastrophic damage in power MOSFETs". Thesis, The University of Arizona, 1990. http://hdl.handle.net/10150/291470.
Pełny tekst źródłaDE, GASPERI SERGIO. "Integrated health condition monitoring for power MOSFETs". Doctoral thesis, Università degli Studi di Milano-Bicocca, 2022. http://hdl.handle.net/10281/392351.
Pełny tekst źródłaPower semiconductors have a crucial role in conversion and distribution of electric energy. Power MOSFETs, especially, can be found in a large variety of applications, like consumer electronics, automotive or grid applications. Such an ubiquitous technology is indeed subject to unceasing cost-optimization efforts. Minimization of materials usage is the most straightforward way to cost optimization, and it comes together with a decrease in the footprint size of devices. This comes at cost of an increase in power densities, and therfore an increase in heat dissipation per unit area. As a result, during operation, power MOSFETs need to withstand intense thermo-mechanical stress, which is the main reliability concern on many application fields. This thesis is focused on a vertical DMOS technology, for which power metallization degradation is the main stress-related failure cause. A possible way to improve reliability of power MOSFETs is to implement in-situ prognostic health management capabilities: in this thesis, two implementation methods are experimentally investigated. The first method consists of building a non-vital structure that shares the same degradation driving force as power metallization, although the degradation process is different. Thermo-mechanical stress results in the formation of short circuits into the non-vital structure, which are electrically detectable. The second method here proposed relies on local temperature measurements in different spots of the DMOS during power transients. Power metallization degradation leads to failure precisely because it modifies the thermal behavior of the device, therefore, temperature measurements may allow to directly observe the outcome of degradation. Experiments partially validate the investigated health monitoring principles, but the implementation tested so far are not reliable enough for industrial application. For both experiments, time limitations and the need for different actions in very diverse fields (circuit design, technology development, test engineering, materials science) posed a remarkable challenge. As a result, the experience acquired in the development of the two techniques shaped a concept for a third solution, that is only conceptually described in the last part of this thesis. As a conclusion, this thesis demonstrates that innovative solutions to the problem can be developed through an effort on different fields of expertise, and the achieved preliminary results pose a promising outlook for further investigations, which may successfully develop robust and reliable implementations.
Safarjameh, Kourosh 1961. "Fast-neutron-induced resistivity change in power MOSFETs". Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277011.
Pełny tekst źródłaFayyaz, Asad. "Performance and robustness characterisation of SiC power MOSFETs". Thesis, University of Nottingham, 2018. http://eprints.nottingham.ac.uk/48937/.
Pełny tekst źródłaKulisek, Jonathan Andrew. "The Effects of Nuclear Radiation on Schottky Power Diodes and Power MOSFETs". The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1267502877.
Pełny tekst źródłaWang, Wei. "Power Module with Series-connected MOSFETs in Flip-chip Configuration". Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/36036.
Pełny tekst źródłaMaster of Science
Evans, J. L. "The design and manufacture of trench gated power MOSFETs". Thesis, University of Cambridge, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.598877.
Pełny tekst źródłaLandowski, Matthew. "DESIGN AND MODELING OF RADIATION HARDENED LATERAL POWER MOSFETS". Master's thesis, University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2823.
Pełny tekst źródłaM.S.E.E.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering MSEE
Shea, Patrick Michael. "Lateral power MOSFETs hardened against single event radiation effects". Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4705.
Pełny tekst źródłaID: 030646200; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 161-166).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering
Yiin, Andy Jyhpyng 1962. "Gate-charge characterization of irradiated N-channel power MOSFETs". Thesis, The University of Arizona, 1991. http://hdl.handle.net/10150/277890.
Pełny tekst źródłaHoagland, Richard W. "Time domain device modeling of High Frequency Power MOSFETs". Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-01102009-063443/.
Pełny tekst źródłaNEDELJKOVIC, SONJA R. "PARAMETER EXTRACTION AND DEVICE PHYSICS PROJECTIONS ON LATERAL LOW VOLTAGE POWER MOSFET CONFIGURATIONS". University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1005163403.
Pełny tekst źródłaWelchko, Brian A. "A High Power DC Motor Controller for an Electric Race Car Using Power Mosfets". Ohio University / OhioLINK, 1996. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1239733975.
Pełny tekst źródłaWelchko, Brian A. "A high power DC motor controller for an electrical race car using power MOSFETS". Ohio : Ohio University, 1996. http://www.ohiolink.edu/etd/view.cgi?ohiou1239733975.
Pełny tekst źródłaRong, Hua. "Development of 4H-SiC power MOSFETs for high voltage applications". Thesis, University of Warwick, 2015. http://wrap.warwick.ac.uk/79426/.
Pełny tekst źródłaNassif-Khalil, Sameh G. "CMOS-compatible power MOSFETs for on-chip DC/DC converters". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0023/MQ50383.pdf.
Pełny tekst źródłaWahle, Peter Joseph 1961. "Radiation effects on power MOSFETs under simulated space radiation conditions". Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277024.
Pełny tekst źródłaHasan, Samil Mukhlisin Yauma 1967. "Neutron irradiation effects on the breakdown voltage of power MOSFETs". Thesis, The University of Arizona, 1993. http://hdl.handle.net/10150/278361.
Pełny tekst źródłaLinewih, Handoko, i h. linewih@griffith edu au. "Design and Application of SiC Power MOSFET". Griffith University. School of Microelectronic Engineering, 2003. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20030506.013152.
Pełny tekst źródłaLinewih, Handoko. "Design and Application of SiC Power MOSFET". Thesis, Griffith University, 2003. http://hdl.handle.net/10072/367638.
Pełny tekst źródłaThesis (PhD Doctorate)
Doctor of Philosophy (PhD)
School of Microelectronic Engineering
Full Text
Huang, Chender 1960. "Characterization of interface trap density in power MOSFETs using noise measurements". Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276872.
Pełny tekst źródłaMulpuri, Vamsi. "Failure Analysis and High Temperature Characterization of Silicon Carbide Power MOSFETs". University of Akron / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=akron151076214366849.
Pełny tekst źródłaDibra, Donald [Verfasser]. "Single Pulse Safe Operating Area of Trench Power MOSFETs in Automotive Power Integrated Circuits / Donald Dibra". München : Verlag Dr. Hut, 2011. http://d-nb.info/1018982922/34.
Pełny tekst źródłaXiong, Yali. "MODELING AND ANALYSIS OF POWER MOSFETS FOR HIGH FREQUENCY DC-DC CONVERTERS". Doctoral diss., University of Central Florida, 2008. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3589.
Pełny tekst źródłaPh.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD
Akram, Farhan. "Gate driver solutions for high power density SMPS using Silicon Carbide MOSFETs". Thesis, Mittuniversitetet, Institutionen för elektronikkonstruktion, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-41188.
Pełny tekst źródłaHopkins, Andrew Neil. "Ancillary techniques for enabling high efficiency power conversion with super junction MOSFETs". Thesis, University of Bristol, 2018. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.738328.
Pełny tekst źródłaRalston, Parrish Elaine. "Design and Verification of a High Voltage, Capacitance Voltage Measurement System for Power MOSFETs". Thesis, Virginia Tech, 2008. http://hdl.handle.net/10919/36169.
Pełny tekst źródłaMaster of Science
Chern, Winston. "Prospects of germanium-based MOSFETs and tunnel transistors for low power digital logic". Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/109010.
Pełny tekst źródłaCataloged from PDF version of thesis.
Includes bibliographical references (pages 157-167).
Moore's law has driven technological improvements for decades by halving the areal footprint of the transistor every two years and increasing the performance of making integrated circuits while reducing their cost. The ability to reduce the footprint of the device was enabled by advances in processing technology, novel materials and device design. As ever-smaller footprints are desired, power density limitations and performance degradation require more innovations on all fronts. Recently introduced improvements to integrated circuits are high-K and metal gate for MOSFETs (45-nm node onward), the FinFET (22-nm node onward) and air gaps between copper interconnects (14-nm node) illustrating that at every new technology node there needs to be a materials or process-related improvement to reduce power and maintain performance. Other approaches are also being explored or taken to further improve the MOSFET performance in future technology nodes, namely use of channel materials with higher carrier mobility such as SiGe and Ge for p-MOSFETs, III-V compound semiconductors for n-MOSFETs and steep subthreshold swing devices such as tunnel field effect transistors (TFETs). This work evaluates both approaches utilizing germanium (Ge) and strained-Ge as a material to understand the benefits and drawbacks to both approaches. Hypothetically, high carrier mobility and velocity channel materials can lower the overall power consumption because lower power supply voltage is required to obtain the same amount of current. Germanium and strained-Ge are candidates for the channel material of p-MOSFETs. MOSFETs made using Ge and strained-Ge as the channel material are evaluated based upon the ITRS roadmap requirements using experimental results in this work and data from literature. The approach for using TFETs was evaluated in this work also using germanium as a channel material. TFETs can have a steep subthreshold swing (SS), better than the minimum of 60 mV/decade at room temperature for a MOSFET, which also reduces the total power and supply voltage required for operation. The reduced SS is hypothetically achieved through the band-to-band tunneling which allows for the filtering of the Fermi-tail distribution of carriers. Experimentally, TFETs have not generally shown the steeper than Fermi-tail SS promised by the theory and this work uses both results from fabricated strained-Si/strained-Ge TFETs as well as modeling to explain why this has been the case. The challenges for both technologies are outlined in this thesis and suggestions are made on approaches to tackling their respective intrinsic problems from the point of view of Ge-based devices.
by Winston Chern.
Ph. D.
Sachdeva, Rishi. "A two-stage gate drive scheme for snubberless operation of power MOSFETs and IGBTs". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/mq65166.pdf.
Pełny tekst źródłaSmith, Mark John. "Low temperature phonon-drag thermoelectric power calculations in GaAs/GaAlAs heterojunctions and Si MOSFETs". Thesis, University of Warwick, 1989. http://wrap.warwick.ac.uk/4163/.
Pełny tekst źródłaMarzoughi, Alinaghi. "Investigating Impact of Emerging Medium-Voltage SiC MOSFETs on Medium-Voltage High-Power Applications". Diss., Virginia Tech, 2018. http://hdl.handle.net/10919/81822.
Pełny tekst źródłaPh. D.
Kosier, Steven Louie 1966. "The effects of ionizing radiation on the breakdown voltage of p-channel power MOSFETs". Thesis, The University of Arizona, 1990. http://hdl.handle.net/10150/277798.
Pełny tekst źródłaPastorek, Matej. "Fabrication and characterization of III-V MOSFETs for high performance and low power applications". Thesis, Lille 1, 2017. http://www.theses.fr/2017LIL10186/document.
Pełny tekst źródłaScaling the size of CMOS circuits to extremely small dimensions gets the semiconductor industry to a point where its cornerstone, Silicon-based MOSFET starts to suffer a poor power efficiency. In the quest for alternative solutions cannot be omitted a concept of III-V MOSFET. Its outstanding transport properties hold a promise of reduced CMOS supply voltage without compromising the performance. This can path a way not only to the smaller, greener electronics but also to more co-integrated RF and CMOS electronics. In this context, we present fabrication and characterization of Ultra-Thin body InAs MOSFETs and InAs FinFET. Synergy of a deeply scaled gate length, low access resistance and a high mobility of InAs channel enabled to obtain impressively high drain currents (IMAX=2000mA/mm for LG=25nm). Equally, the introduction of Ultra-Thin body and FinFET channel design provides an improved electrostatic control. A specific feature of the process presented in this work is a fabrication of contacts and channel by localized molecular beam epitaxy MBE epitaxy
Broadmeadow, Mark A. "Characterisation of the cascode gate drive of power MOSFETs in clamped inductive switching applications". Thesis, Queensland University of Technology, 2015. https://eprints.qut.edu.au/82868/4/Mark%20Broadmeadow%20Thesis.pdf.
Pełny tekst źródłaZetterling, Carl-Mikael. "Silicon dioxide and aluminium nitride as gate dielectric for high temperature and high power silicon carbide MOSFETs". Doctoral thesis, KTH, Electronic Systems Design, 1997. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-2514.
Pełny tekst źródłaSilicon carbide (SIC) is a wide bandgap semiconductor thathas been suggested as a replacement for silicon in applicationsusing high voltages, high frequencies, high temperatures orcombinations thereof. Several basic process steps need to bedeveloped for reliable manufacturing of long-term stableelectronic devices. One important process step is the formationof an insulator on the silicon carbide surface that may be usedas a) a gate dielectric, b) for device isolation or c) forpassivation of the surface. Silicon dioxide and aluminumnitride have been suggested for these purposes. This thesiscovers the investigation of some formation methods for boththese materials on 4H and 6H silicon carbide, and theelectrical characterisation of the resulting films.
Commercially available n-type and p-type 4H and 6H SICwafers have been used, and both the silicon face and the carbonface have been investigated. Silicon dioxide has been formed byseveral methods: a) dry thermal oxidation with or without theaddition of TCA (trichloroethane), b) wet oxidation inpyrogenic steam or with awater bubbler, c) oxide deposition byPECVD (plasma enhanced chemical vapor deposition) or LPCVD (lowpressure chemical vapor deposition) and d) oxidation of aevaporated or LPCVD deposited sacrificial layer of silicon. Theinfluence of various cleaning methods prior to oxidation hasbeen studied, as well as post-oxidation and post-metallisationannealing. The aluminum nitride films were grown by MOCVD(metal organic chemical vapor deposition) under various processconditions.
Oxidation kinetics have been studied for dry thermaloxidation at 1200 0C. The redistribution of aluminum (p-typedopant in SiC) during dry thermal oxidation has beeninvestigated using SIMS (secondary ion mass spectrometry). Themorphology of the aluminum nitride was determined using x-raydiffraction rocking curves, RHEED (reflection high energyelectron diffraction) and AFM (atomic force microscopy). Thequality of the silicon dioxide used as gate dielectric has beendetermined using breakdown field measurements. High frequencycapacitance-voltage measurements have been used on bothinsulators to a) verify thickness measurements made with othermethods, b) to determine fixed oxide charges by measuring theflatband voltage shifts and c) to quantitatively compare theamount of interface states.
For electrical characterisation either aluminum, titanium ordoped polysilicon circular gate contacts of various sizes wereformed on the insulator surface. Flat MOS capacitors weremainly used for the electrical characterisation. U-grooved MOScapacitors, manufactured by RIE (reactive ion etching), wereused to test the quality of oxides grown on vertical surfaces.Two types of MOSFETs (metal oxide semiconductor field effecttransistors) have been fabricated: vertical U-grooved andlateral devices.
Keywords:silicon carbide, thermal oxidation, silicondioxide, metal organic chemical vapor deposition (MOCVD),aluminum nitride, capacitance-voltage measurements, MOSFET.
Francisco, sousa alves Luciano. "Series-connected SiC-MOSFETs : A Novel Multi-Step Packaging Concept and New Gate Drive Power Supply Configurations". Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT050.
Pełny tekst źródłaThis work investigates new gate drive power supply configurations and a novel multi-steppackaging concept in order to improve the performance of series-connected SiC-MOSFETs. The new gate drive configurations are proposed in order to reduce noise currents that circulate in the control part of the electrical system. Furthermore, a new gate drive power supply is proposed to increase the dv/dt of the switching cell. These improvements, i.e., noise current reduction and dv/dt boosting, are achieved by modifying the impedance of the gate drive circuitry. The novel multi-step packaging concept is proposed in order to improve the voltage sharing performance. The proposed package geometry considers optimal dielectric isolation for each device leading to a multi-step geometry. It has a significant impact on the parasitic capacitances introduced by the packaging structure that are responsible for voltageunbalances. The new gate driver configurations and the proposed multi-step packaging concepts are introduced and analysed thanks to equivalent models and time domain simulations. Then, experimental set-ups are performed to confirm that the proposed concepts are better than traditional ones in terms of voltage balancing, switching speed and conducted EMI reduction
Johnson, Gregory Howard 1965. "Features of a heavy-ion-generated-current filament used in modeling single-event burnout of power MOSFETs". Thesis, The University of Arizona, 1990. http://hdl.handle.net/10150/277796.
Pełny tekst źródłaPang, Yon Sup. "Design and modeling of non-uniformly doped deep-submicron pocket MOSFETs for low-voltage low-power applications". Diss., The University of Arizona, 2000. http://hdl.handle.net/10150/279886.
Pełny tekst źródłaBalasubramanian, Venkatesh. "Characterization of sub-90 nm Gate Length RF MOSFETs using Large Signal Network Analyzer". The Ohio State University, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=osu1230671230.
Pełny tekst źródłaJabs, Dominic Verfasser], Christoph [Akademischer Betreuer] [Jungemann i Tibor [Akademischer Betreuer] Grasser. "Hot-carrier degradation at avalanche breakdown: microscopic simulation of power MOSFETs / Dominic Jabs ; Christoph Antonius Jungemann, Tibor Grasser". Aachen : Universitätsbibliothek der RWTH Aachen, 2017. http://d-nb.info/1162553898/34.
Pełny tekst źródłaJabs, Dominic [Verfasser], Christoph [Akademischer Betreuer] Jungemann i Tibor [Akademischer Betreuer] Grasser. "Hot-carrier degradation at avalanche breakdown: microscopic simulation of power MOSFETs / Dominic Jabs ; Christoph Antonius Jungemann, Tibor Grasser". Aachen : Universitätsbibliothek der RWTH Aachen, 2017. http://nbn-resolving.de/urn:nbn:de:101:1-2018071111001536929864.
Pełny tekst źródłaGopalakrishna, Keshava. "Frequency Characterization of Si, SiC,and GaN MOSFETs Using Buck ConverterIn CCM as an Application". Wright State University / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=wright1387661422.
Pełny tekst źródłaBernoux, Béatrice. "Caractérisation de MOSFETs de puissance cyclés en avalanche pour des applications automobiles micro-hybrides". Thesis, Toulouse, INSA, 2010. http://www.theses.fr/2010ISAT0007/document.
Pełny tekst źródłaResearch work presented in this thesis concern the conception and the study of low voltage power MOSFETs for micro hybrid vehicles (starter alternator). For some of these applications, developed transistors must be able to operate in classical ON and OFF state mode and in avalanche mode at high current and high temperature. To reproduce this operating mode, MOSFETs are submitted to a specific repetitive UIS test. In order to evaluate silicon’s temperature during this test, several temperature measurement methods have been developed and compared. In parallel, in order to understand the impact of repetitive avalanche on the transistor, standard electrical parameters (BVDSS, IDSS, RDSon…) are monitored during the test. The only parameter that seems to be shifting with the number of cycles is the RDSon. This phenomenon is due to the measurement method and to a variation of source metallization resistance during cycling. Indeed several observations have shown source metallization ageing and a shift in its resistivity. Different metallization and assembly parameters have been tested to limit this phenomenon. Also various test structures have been designed to study metallization evolution and to compare different metallization behaviors
Aviñó, Salvadó Oriol. "Contribution to the study of the SiC MOSFETs gate oxide". Thesis, Lyon, 2018. http://www.theses.fr/2018LYSEI110/document.
Pełny tekst źródłaSiC power MOSFETs are called to replace Si IGBT for some medium and high power applications (hundreds of kVA). However, even if crystallographic defects have been drastically reduced, SiC MOSFETs are always concerned by some robustness issues such as the internal diode robustness or the robustness of the gate oxide. The last one especially affects MOSFETs devices and is linked to the apparition of instabilities in the threshold voltage. This thesis focuses on these two issues. The study of the internal diode robustness highlighted that the I-V curve (of the intrinsic diode) remains stable after the application of a current stress in static mode, but also with the DUT placed in a converter with inductive switchings. These are the most stressful conditions. However, a surprising drift in the threshold voltage has been observed when some devices operates under these conditions; in static mode or in a converter. Complementary tests stressing the channel instead of the internal diode in the same temperature and dissipated power, have not resulted in a drift of the threshold voltage. Thus, the application of a current stress when the device is in accumulation regime could favour the apparition of instabilities in the threshold voltage. The study of the gate oxide focus in the instabilities of the threshold voltage, but also on the expected lifetime of the oxide at nominal conditions. Results obtained shown that the expected lifetime (TDDB) of the oxide is no longer a problem. Indeed, tests realized in static mode, but also in a converter under inductive switching conditions resulted in expected lifetimes well above 100 years. However, the monitoring of the gate current during the test and gate capacitance characterizations C(V) highlighted a shift in the capacitance due to carrier injection and trapping phenomena and probably to the presence of mobile-ions. Still regarding the instabilities of the threshold voltage, classic tests resulted in no significant variations of the threshold voltage at 150 _C. However, at 200 _C the drift observed for some manufacturers is higher than +30%. This is unacceptable for high-temperature applications and evidence that the quality of the gate oxide and the SiC=SiO2 interface must continue to be improved, together with the manufacturing methods to minimize the presence of mobile ions in the substrate