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1
Belfiore, Guido, Laszlo Szilagyi, Ronny Henker i Frank Ellinger. "Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect". SPIE, 2015. https://tud.qucosa.de/id/qucosa%3A34801.
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This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm². The driver can achieve an error-free (
2
Ochana, Andrew. "Power cycling of flip chip assemblies". Thesis, Loughborough University, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.418328.
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Mischenko, Alexandre. "On-chip cooling and power generation". Thesis, University of Cambridge, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.612857.
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Peter, Eldhose. "Power efficient on-chip optical interconnects". Thesis, IIT Delhi, 2016. http://localhost:8080/iit/handle/2074/7224.
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Wu, Wei-Chung. "On-chip charge pumps". Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13451.
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Hamwi, Khawla. "Low Power Design Methodology and Photonics Networks on Chip for Multiprocessor System on Chip". Thesis, Brest, 2013. http://www.theses.fr/2013BRES0029.
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Les systèmes multiprocesseurs sur puce (MPSoC)s sont fortement émergent comme principaux composants dans les systèmes embarqués à hautes performances. La principale complexité dans la conception et l’implémentation des MPSoC est la communication entre les cœurs. Les réseaux sur puce (NoC) sont considérés comme la solution pour cet effet. ITRS prédit que des centaines de cœurs seront utilisées dans la génération future de système sur puce (SoC), ce qui va donc augmenter les coûts de l’évolutivité, de bande passante et de l’implémentation des réseaux sur puce (NoC)s. Ces problèmes sont présents dans diverses tendances technologiques dans le domaine des semiconducteurs et de la photonique. Cette thèse préconise l'utilisation de la synthèse NoC comme l'approche la plus appropriée pour exploiter ces tendances technologiques et rattraper les exigences des applications. A partir de plusieurs méthodologies de conception basées sur la technologie FPGA et des techniques d'estimation basse énergie (HLS) pour plusieurs IPs, nous proposons une implémentation ASIC basée sur la technologie 3D Tezzaron. Multi-FPGA technologie est utilisée pour valider la conception MPSoC avec 64 processeurs Butterfly NoC. La synthèse NoC est basée sur le regroupement de maîtres et d’esclaves générant des architectures asymétriques avec un soutien approprié pour les demandes très haut débit par optique NoC (ONoC), tandis que les demandes de bande passante inférieure sont traitées par électronique NoC. Une programmation linéaire est proposée comme une solution pour la synthèse NoCMultiprocessor systems on chip (MPSoC)s are strongly emerging as main components in high performance embedded systems. Several challenges can be determined in MPSoC design like the challenge which comes from interconnect infrastructure. Network-on-Chip (NOC) with multiple constraints to be satisfied is a promising solution for these challenges. ITRS predicts that hundreds of cores will be used in future generation system on chip (SoC) and thus raises the issue of scalability, bandwidth and implementation costs for NoCs. These issues are raised within the various technological trends in semiconductors and photonics. This PhD thesis advocates the use of NoC synthesis as the most appropriate approach to exploit these technological trends catch up with the applications requirements. Starting with several design methodologies based on FPGA technology and low power estimation techniques (HLS) for several IPs, we propose an ASIC implementation based on 3D Tezzaron technology. Multi-FPGA technology is used to validate MPSoC design with up to 64 processors with Butterfly NoC. NoC synthesis is based on a clustering of masters and slaves generating asymmetric architectures with appropriate support for very high bandwidth requests through Optical NoC (ONoC) while lower bandwidth requests are processed by electronic NoC. A linear programming is proposed as a solution to the NoC synthesis
7
Hamwi, Khawla. "Low Power Design Methodology and Photonics Networks on Chip for Multiprocessor System on Chip". Electronic Thesis or Diss., Brest, 2013. http://www.theses.fr/2013BRES0029.
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Les systèmes multiprocesseurs sur puce (MPSoC)s sont fortement émergent comme principaux composants dans les systèmes embarqués à hautes performances. La principale complexité dans la conception et l’implémentation des MPSoC est la communication entre les cœurs. Les réseaux sur puce (NoC) sont considérés comme la solution pour cet effet. ITRS prédit que des centaines de cœurs seront utilisées dans la génération future de système sur puce (SoC), ce qui va donc augmenter les coûts de l’évolutivité, de bande passante et de l’implémentation des réseaux sur puce (NoC)s. Ces problèmes sont présents dans diverses tendances technologiques dans le domaine des semiconducteurs et de la photonique. Cette thèse préconise l'utilisation de la synthèse NoC comme l'approche la plus appropriée pour exploiter ces tendances technologiques et rattraper les exigences des applications. A partir de plusieurs méthodologies de conception basées sur la technologie FPGA et des techniques d'estimation basse énergie (HLS) pour plusieurs IPs, nous proposons une implémentation ASIC basée sur la technologie 3D Tezzaron. Multi-FPGA technologie est utilisée pour valider la conception MPSoC avec 64 processeurs Butterfly NoC. La synthèse NoC est basée sur le regroupement de maîtres et d’esclaves générant des architectures asymétriques avec un soutien approprié pour les demandes très haut débit par optique NoC (ONoC), tandis que les demandes de bande passante inférieure sont traitées par électronique NoC. Une programmation linéaire est proposée comme une solution pour la synthèse NoCMultiprocessor systems on chip (MPSoC)s are strongly emerging as main components in high performance embedded systems. Several challenges can be determined in MPSoC design like the challenge which comes from interconnect infrastructure. Network-on-Chip (NOC) with multiple constraints to be satisfied is a promising solution for these challenges. ITRS predicts that hundreds of cores will be used in future generation system on chip (SoC) and thus raises the issue of scalability, bandwidth and implementation costs for NoCs. These issues are raised within the various technological trends in semiconductors and photonics. This PhD thesis advocates the use of NoC synthesis as the most appropriate approach to exploit these technological trends catch up with the applications requirements. Starting with several design methodologies based on FPGA technology and low power estimation techniques (HLS) for several IPs, we propose an ASIC implementation based on 3D Tezzaron technology. Multi-FPGA technology is used to validate MPSoC design with up to 64 processors with Butterfly NoC. NoC synthesis is based on a clustering of masters and slaves generating asymmetric architectures with appropriate support for very high bandwidth requests through Optical NoC (ONoC) while lower bandwidth requests are processed by electronic NoC. A linear programming is proposed as a solution to the NoC synthesis
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Lai, Yin Hing. "High power flip-chip light emitting diode /". View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20LAI.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004.Includes bibliographical references (leaves 60-68). Also available in electronic version. Access restricted to campus users.
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Singhal, Rohit. "Data integrity for on-chip interconnects". Texas A&M University, 2003. http://hdl.handle.net/1969.1/5929.
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With shrinking feature size and growing integration density in the Deep Sub-
Micron (DSM) technologies, the global buses are fast becoming the "weakest-links"
in VLSI design. They have large delays and are error-prone. Especially, in system-onchip
(SoC) designs, where parallel interconnects run over large distances, they pose
difficult research and design problems. This work presents an approach for evaluating
the data carrying capacity of such wires. The method treats the delay and reliability
in interconnects from an information theoretic perspective. The results point to an
optimal frequency of operation for a given bus dimension for maximum data transfer
rate. Moreover, this optimal frequency is higher than that achieved by present day
designs which accommodate the worst case delays.
This work also proposes several novel ways to approach this optimal data transfer
rate in practical designs.From the analysis of signal propagation delay in long wires,
it is seen that the signal delay distribution has a long tail, meaning that most signals
arrive at the output much faster than the worst case delay. Using communication theory,
these "good" signals arriving early can be used to predict/correct the "few"
signals that arrive late. In addition to this correction based on prediction, the approaches
use coding techniques to eliminate high delay cases to generate a higher transmission rate.
The work also extends communication theoretic approaches to other areas of
VLSI design. Parity groups are generated based on low output delay correlation to
add redundancy in combinatorial circuits. This redundancy is used to increase the
frequency of operation and/or reduce the energy consumption while improving the
overall reliability of the circuit.
10
Oberle, Michael. "Low power systems-on-chip for biomedical applications /". [S.l.] : [s.n.], 2002. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=14509.
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Lu, Jian. "Embedded Magnetics for Power System on Chip (PSoC)". Doctoral diss., University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2993.
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A novel concept of on-chip bondwire inductors and transformers with ferrite epoxy glob coating is proposed, offering a cost effective approach to realize power systems on chip (PSoC) or System-in-Package (PSiP). The concept has been investigated both experimentally and with finite element modeling. Improvement in total inductance is demonstrated for multi-turn bondwire inductors over single bondwire inductors. The inductance and Q factor can be further boosted with coupled multi-turn inductor concept. Transformer parameters including self- and mutual inductance, and coupling factors are extracted from both modeled and measured S-parameters. More importantly, the bondwire magnetic components can be easily integrated into SoC manufacturing processes with minimal changes to the layout, and open enormous possibilities for realizing cost-effective, high current, high efficiency PSoC's or PSiP's. The design guidelines for single bondwire inductors as well as multi-turn inductors are discussed step by step in several chapters. Not only is the innovated concept for bondwire inductor with ferrite ink presented, but also the practical implementation and design rules are given. With all the well defined steps, people who want to use these bondwire inductors with ferrite ink in their PSoC research or products will find it as simple as using commercial inductors. Last but not least, the PSoC concept using a bondwire inductor is demonstrated by building the prototype of dc-dc buck converter IC as well as the whole package. IC and the whole function block are tested and presented in this work.Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD
12
Ma, Kai. "Power Constrained Performance Optimization in Chip Multi-processors". The Ohio State University, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=osu1373297788.
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Leroy, Anthony. "Optimizing the on-chip communication architecture of low power Systems-on-Chip in Deep Sub-Micron technology". Doctoral thesis, Universite Libre de Bruxelles, 2006. http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/210801.
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Ce mémoire traite des systèmes intégrés sur puce (System-on-Chip) à faible consommation d'énergie tels que ceux qui seront utilisés dans les équipements portables de future génération (ordinateurs de poche (PDA), téléphones mobiles). S'agissant d'équipements alimentés par des batteries, la consommation énergétique est un problème critique. Ces plateformes contiendront probablement une douzaine de coeurs de processeur et une quantité importante de mémoire embarquée. Une architecture de communication optimisée sera donc nécessaire afin de les interconnecter de manière efficace. De nombreuses architectures de communication ont été proposées dans la littérature: bus partagés, bus pontés, bus segmentés et plus récemment, les réseaux intégrés (NoC).
Toutefois, à l'exception des bus, la consommation d'énergie des réseaux d'interconnexion intégrés a été largement ignorée pendant longtemps. Ce n'est que très récemment que les premières études sont apparues dans ce domaine.
Cette thèse présente:
- Une analyse complète de l'espace de conception des architectures de communication intégrées. Sur base de cet espace de conception et d'un état de l'art détaillé, des techniques jusqu'alors inexplorées ont pu être identifiées et investiguées.
- La conception d'environnements de simulation de bas et haut niveaux permettant de réaliser des comparaisons entre différentes architectures de communication en termes de consommation énergétique et de surface.
- La conception et la validation d'une architecture de communication intégrée innovante basée sur le multiplexage spatial
Ce dernier point a pour ambition de démontrer qu'un réseau basé sur le multiplexage spatial (SDM) constitue une alternative intéressante aux réseaux classiques principalement basés sur le multiplexage temporel dans le contexte très spécifique des architectures de communication intégrées.
Nous démontrerons la validité de la solution proposée à l'aide de campagnes de simulation de haut niveau pour divers types de trafic ainsi que des simulations de plus bas niveau. L'étude concerne successivement la conception de routers SDM, des interfaces réseau et finalement d'un réseau complet. Les avantages et inconvénients d'une telle technique seront discutés en détails.
Doctorat en sciences appliquées
info:eu-repo/semantics/nonPublished
14
Abdelhameed, Mohamed Ahmed Saad. "On-chip adaptive power management for WPT-Enabled IoT". Doctoral thesis, Universitat Politècnica de Catalunya, 2018. http://hdl.handle.net/10803/587158.
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Internet of Things (IoT), as broadband network connecting every physical objects, is becoming more widely available in various industrial, medical, home and automotive applications. In such network, the physical devices, vehicles, medical assistance, and home appliances among others are supposed to be embedded by sensors, actuators, radio frequency (RF) antennas, memory, and microprocessors, such that these devices are able to exchange data and connect with other devices in the network. Among other IoT’s pillars, wireless sensor network (WSN) is one of the main parts comprising massive clusters of spatially distributed sensor nodes dedicated for sensing and monitoring environmental conditions. The lifetime of a WSN is greatly dependent on the lifetime of the small sensor nodes, which, in turn, is primarily dependent on energy availability within every sensor node. Predominantly, the main energy source for a sensor node is supplied by a small battery attached to it. In a large WSN with massive number of deployed sensor nodes, it becomes a challenge to replace the batteries of every single sensor node especially for sensor nodes deployed in harsh environments. Consequently, powering the sensor nodes becomes a key limiting issue, which poses important challenges for their practicality and cost.
Therefore, in this thesis we propose enabling WSN, as the main pillar of IoT, by means of resonant inductive coupling (RIC) wireless power transfer (WPT). In order to enable efficient energy delivery at higher range, high quality factor RIC-WPT system is required in order to boost the magnetic flux generated at the transmitting coil. However, an adaptive front-end is essential for self-tuning the resonant tank against any mismatch in the components values, distance variation, and interference from close metallic objects. Consequently, the purpose of the thesis is to develop and design an adaptive efficient switch-mode front-end for self-tuning in WPT receivers in multiple receiver system.
The thesis start by giving background about the IoT system and the technical bottleneck followed by the problem statement and thesis scope. Then, Chapter 2 provides detailed backgrounds about the RIC-WPT system. Specifically, Chapter 2 analyzes the characteristics of different compensation topologies in RIC-WPT followed by the implications of mistuning on efficiency and power transfer capability. Chapter 3 discusses the concept of switch-mode gyrators as a potential candidate for generic variable reactive element synthesis while different potential applications and design cases are provided. Chapter 4 proposes two different self-tuning control for WPT receivers that utilize switch-mode gyrators as variable reactive element synthesis. The performance aspects of control approaches are discussed and evaluated as well in Chapter 4. The development and exploration of more compact front-end for self-tuned WPT receiver is investigated in Chapter 5 by proposing a phase-controlled switched inductor converter. The operation and design details of different switch-mode phase-controlled topologies are given and evaluated in the same chapter. Finally, Chapter 6 provides the conclusions and highlight the contribution of the thesis, in addition to suggesting the related future research topics.Internet de las cosas (IoT), como red de banda ancha que interconecta cualquier cosa, se está estableciendo como una tecnología valiosa en varias aplicaciones industriales, médicas, domóticas y en el sector del automóvil. En dicha red, los dispositivos físicos, los vehículos, los sistemas de asistencia médica y los electrodomésticos, entre otros, incluyen sensores, actuadores, subsistemas de comunicación, memoria y microprocesadores, de modo que son capaces de intercambiar datos e interconectarse con otros elementos de la red. Entre otros pilares que posibilitan IoT, la red de sensores inalámbricos (WSN), que es una de las partes cruciales del sistema, está formada por un conjunto masivo de nodos de sensado distribuidos espacialmente, y dedicados a sensar y monitorizar las condiciones del contexto de las cosas interconectadas. El tiempo de vida útil de una red WSN depende estrechamente del tiempo de vida de los pequeños nodos sensores, los cuales, a su vez, dependen primordialmente de la disponibilidad de energía en cada nodo sensor. La fuente principal de energía para un nodo sensor suele ser una pequeña batería integrada en él. En una red WSN con muchos nodos y con una alta densidad, es un desafío el reemplazar las baterías de cada nodo sensor, especialmente en entornos hostiles, como puedan ser en escenarios de Industria 4.0. En consecuencia, la alimentación de los nodos sensores constituye uno de los cuellos de botella que limitan un despliegue masivo práctico y de bajo coste. A tenor de estas circunstancias, en esta tesis doctoral se propone habilitar las redes WSN, como pilar principal de sistemas IoT, mediante sistemas de transferencia inalámbrica de energía (WPT) basados en acoplamiento inductivo resonante (RIC). Con objeto de posibilitar el suministro eficiente de energía a mayores distancias, deben aumentarse los factores de calidad de los elementos inductivos resonantes del sistema RIC-WPT, especialmente con el propósito de aumentar el flujo magnético generado por el inductor transmisor de energía y su acoplamiento resonante en recepción. Sin embargo, dotar al cabezal electrónico que gestiona y condicionada el flujo de energía de capacidad adaptativa es esencial para conseguir la autosintonía automática del sistema acoplado y resonante RIC-WPT, que es muy propenso a la desintonía ante desajustes en los parámetros nominales de los componentes, variaciones de distancia entre transmisor y receptores, así como debido a la interferencia de objetos metálicos. Es por tanto el objetivo central de esta tesis doctoral el concebir, proponer, diseñar y validar un sistema de WPT para múltiples receptores que incluya funciones adaptativas de autosintonía mediante circuitos conmutados de alto rendimiento energético, y susceptible de ser integrado en un chip para el condicionamiento de energía en cada receptor de forma miniaturizada y desplegable de forma masiva. La tesis empieza proporcionando una revisión del estado del arte en sistemas de IoT destacando el reto tecnológico de la alimentación energética de los nodos sensores distribuidos y planteando así el foco de la tesis doctoral. El capítulo 2 sigue con una revisión crítica del statu quo de los sistemas de transferencia inalámbrica de energía RIC-WPT. Específicamente, el capítulo 2 analiza las características de diferentes estructuras circuitales de compensación en RIC-WPT seguido de una descripción crítica de las implicaciones de la desintonía en la eficiencia y la capacidad de transferencia energética del sistema. El capítulo 3 propone y explora el concepto de utilizar circuitos conmutados con función de girador como potenciales candidatos para la síntesis de propósito general de elementos reactivos variables sintonizables electrónicamente, incluyendo varias aplicaciones y casos de uso. El capítulo 4 propone dos alternativas para métodos y circuitos de control para la autosintonía de receptores de energía
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Mathew, Jimson. "Design techniques for low power on-chip error correction". Thesis, University of Bristol, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.492442.
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As integrated circuit density increases, digital circuits characterized by high operating frequencies and low voltage levels will be increasingly susceptible to faults. Furthermore, it has recently been shown that for many digital signature and identification schemes an attacker can inject faults into the hardware and the resulting incorrect outputs may completely expose their secrets. On-chip error masking techniques such as error correction could be one of the options to mitigate the above problems. To this end, this thesis presents a framework of techniques to design error circuits.
16
Xia, Wenbo. "Power and thermal modeling for the proto-VIPRAM chip". Thesis, Southern Methodist University, 2014. http://pqdtopen.proquest.com/#viewpdf?dispub=1569659.
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As the power densities increase in integrated circuits (IC) nowadays, especially in 3 dimensional IC (3D-IC), power-induced thermal effects become more and more severe. Therefore, thermal analysis is becoming increasingly important for IC design. The aim of this thesis is to develop power and thermal modeling techniques and the verification method to address the power and thermal challenges in IC designs. The work of this thesis is done by the support of the Vertical Integrated Pattern Recognition Associated Memory (VIPRAM) project from Fermilab. Using the proposed techniques, a power and a thermal model for proto-VIPRAM chip have been developed respectively. Treating one CAM cell as a single power source is found to result in best trade-off between accuracy and speed. A practical verification method for the two modeling approach, which is suitable with the capability of current circuit simulator and thermal sensor system, has been proposed as well. Considering the special power property of the proto-VIPRAM compared to conventional CPU or DRAM chip, the optimization for the input pattern, which can cause the maximum temperature variation across the chip, has also been researched and found. The simulation results provide a good reference to the design of VIPRAM in the next stage. The proposed modeling and analysis methods for power and thermal issues can be also used in other chips for High Energy Physics (HEP) application.
17
Simon, Thomas D. (Thomas David). "A low power video compression chip for portable applications". Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/9474.
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Park, Sunghyun Ph D. Massachusetts Institute of Technology. "Towards low-power yet high-performance networks-on-chip". Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/93776.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 144-154).
A network-on-chip (NoC), the de-facto communication backbone in manycore processors, consumes a significant portion of total chip power, competing against the computation cores for the limited power and thermal budget. On the other hand, overall system performance of manycore chips increasingly relies on on-chip latency and bandwidth as core counts scale. This thesis aims to design low-power yet high-performance NoCs through circuit and microarchitecture co-design contrary to the traditional approaches where NoCs sacrifice latency and/or bandwidth for low-power operation; then demonstrate such design concepts through test chip prototyping, enabling detailed measurements for rigorous analysis of the pros and cons of the proposed NoCs. The thesis starts with a 4x4 mesh NoC chip prototype that tries to simultaneously optimize energy, latency and throughput for all kinds of traffic (unicasts, multicasts and broadcasts). Its extensive experiment results make it possible to accurately analyze energy/performance benefits and timing/area overheads of the virtually bypassed, multicast-optimized router design; energy savings, area overheads and reduced reliability of the clocked low-swing datapath circuits; and a power gap between simulated estimations and measurement results. Next demonstrated is a link test chip of two clockless low-swing repeater designs, a self-resetting logic repeater (SRLR) optimized for transmission energy and a voltage-locked repeater (VLR) for transmission delay. This second chip prototype shows that the clockless, single-ended low-swing signaling of SRLRs armed with variation-robust circuit techniques has lower energy and smaller area than clocked, differential lowswing signaling. Featured with lower delay than full-swing repeaters, VLRs provide the fundamental building block to the single-cycle reconfigurable NoC that enables potential power saving at architecture level through single-cycle multi-hop asynchronous link traversal on dynamically configurable routes. The last one-third of this thesis explores a 3D-IC chip prototype of a throughsilicon via (TSV) interconnect that can support simultaneously bi-directional (SBD) signaling. While TSVs, as 3D-IC NoC links, offer an appealing solution to manycore architectures that require huge off-die bandwidth, existing TSV technologies impose considerable power and area overheads (using spare TSVs) to improve reliability. The proposed SBD TSV circuit shows better energy efficiency and smaller area than unidirectional TSVs, thus providing reliable 3D signaling within tight power/silicon budget. Such SBD signaling also enables configurable off-die bandwidth, and hence, can be the basis of a bandwidth-adaptive 3D NoC that efficiently supports highly dynamic traffic on manycore chips.
by Sunghyun Park.
Ph. D.
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Nilsson, Joakim. "Wireless, Single Chip, High Temperature Monitoring of Power Semiconductors". Licentiate thesis, Luleå tekniska universitet, EISLAB, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-18113.
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Because failures in power electronics can cause production stops and unnecessary damage to interconnected equipment, monitoring schemes that are able to predict such failures provide various economic and safety benefits. The primary motivation for this thesis is that such monitoring schemes can increase the reliability of energy production plants. Power semiconductors are crucial components in power electronics, and monitoring their temperatures yields information that can be used to predict incipient failures.This thesis presents a system concept for wireless, single-chip, high-temperature monitoring of power semiconductors. A wireless single-chip solution is both cost effective and easy to integrate with existing power semiconductor modules. However, the concept presents two major challenges: the implementation of wireless power and communication, and the low-power design of the temperature sensors. Thus, the feasibility of using on-chip coils to provide communication with and obtain power from an external reader coil is assessed, and a low-power, high-temperature bandgap temperature sensor is developed. The sensor is capable of operating in the high-temperature range, allowing it to be useful for detecting incipient faults, particularly solder faults, at up to 230 °C. This is achieved by compensating for leakage currents that arise in hot reverse-biased p-n junctions, which become significant at these high temperatures.A single-chip, on-chip coil solution provides the combined advantages of galvanic isolation from the power device and simplicity of integration in existing modules. However, as the use of a wireless design with a small on-chip coil will limit the amount of available power, it incurs the disadvantage of requiring a low-power design for the sensor. Initial experiments have been performed on a prototype on-chip coil to assess the feasibility of this concept and provide insight into the challenges of on-chip coil design.In this thesis, focus is placed on the challenge of how to handle large leakage currents in low-power integrated silicon circuits. At high temperatures, these leakage currents can approach or even surpass the level of the circuit's quiescent current. Earlier work on leakage current compensation techniques is examined, compared to and combined with a compensation technique designed to compensate for collector-base leakage in the main bipolar pair of a Brokaw bandgap reference. Experiments show that fully analogue sensors operating at up to 228 °C with an accuracy of 10 °C that consume only 8.2 µW are feasible. If a higher accuracy, such as 3 °C, is required, then a temperature range of up to 200 °C can be achieved with a power consumption of 2.3 µW.It is likely that the high temperature range and low power consumption of the sensors presented in this thesis, in combination with on-chip coils, will make them suitable for use in solder fault prediction in power semiconductor modules.Godkänd; 2016; 20160304 (joanil); Nedanstående person kommer att hålla licentiatseminarium för avläggande av teknologie licentiatexamen. Namn: Joakim Nilsson Ämne: Industriell Elektronik/Industrial Electronics Uppsats: Wireless, Single Chip, High Temperature Monitoring of Power Semiconductors Examinator: Docent Jonny Johansson, Institutionen för system- och rymdteknik, Avdelning: EISLAB, Luleå tekniska universitet. Diskutant: Docent Johan Sidén, Avdelningen för Elektronikkonstruktion, Mittuniversitetet, Sundsvall. Tid: Tisdag 3 maj, 2016 kl 8.30 Plats: A1547, Luleå tekniska universitet
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Vivekraja, Vignesh. "Low-Power, Stable and Secure On-Chip Identifiers Design". Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/34854.
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Trustworthy authentication of an object is of extreme importance for secure protocols. Traditional methods of storing the identity of an object using non-volatile memory is insecure. Novel chip-identifiers called Silicon Physical Unclonable Functions (PUFs) extract the random process characteristics of an Integrated Circuit to establish the identity. Though such types of IC identifiers are difficult to clone and provide a secure, yet an area and power efficient authentication mechanism, they suffer from instability due to variations in environmental conditions and noise. The decreased stability imposes a penalty on the area of the PUF circuit and the corresponding error correcting hardware, when trying to generate error-free bits using a PUF.
In this thesis, we propose techniques to improve the popular delay-based PUF architectures holistically, with a focus on its stability. In the first part, we investigate the effectiveness of circuit-level optimizations of the delay based PUF architectures. We show that PUFs which operate in the subthreshold region, where the transistor supply voltage is maintained below the threshold voltage of CMOS, are inherently more stable than PUFs operating at nominal voltage because of the increased difference in characteristics of transistors at this region. Also, we show that subthreshold PUF enjoys higher energy and area efficiency. In the second part of the thesis, we propose a feedback-based supply voltage control mechanism and a corresponding architecture to improve the stability of delay-based PUFs against variations in temperature.Master of Science
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Wu, Pei-Ming. "Micromachined On-Chip Fluxgate Magnetometers with Low Power Consumption". University of Cincinnati / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1277465560.
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Ting, Goodwin. "An integrated BiCMOS driver chip for medium power applications /". Online version of thesis, 1991. http://hdl.handle.net/1850/11291.
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Mineo, Andrea. "Low Power Techniques for Future Network-on-Chip Architectures". Doctoral thesis, Università di Catania, 2017. http://hdl.handle.net/10761/3964.
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In a multi-many/core system, the Network-on-Chip (NoC) based communication
backbone is responsible for a relevant fraction of the overall energy
budget. In fact, the I/O buffers, the crossbars of the routers and the
inter-router links are the main contributors of the NoC s energy dissipation.
Specifically, electrical links will soon represent a bottleneck both in terms
of energy dissipation and delay. For these reasons, several short and long
terms solutions have been proposed from the NoCs research community. In
particular, several techniques are based on reducing the voltage swing in
links resulting in significant energy saving.
We propose techniques and architectures for runtime tuning of the voltage
swing of inter-router links. The proposed technique, is compared with the
state of the art in link energy reduction through data encoding under both
synthetic and real traffic scenarios. We found that the proposed techniques
allow to significantly reduce the energy consumption of the NoC fabric without
degrading the performance metrics. Energy savings ranging from 20%
to 43% have been observed without any relevant impact on the performance
metrics. Wireless networks-on-chip (WiNoCs), have been recently proposed as candidate
solutions for addressing the scalability limitations of conventional multi-hop
NoC architectures. In a WiNoC, a subset of network nodes, namely, radio
hubs, are equipped with a wireless interface that allows them to wire
lessly communicate with other radio hubs. Thus, long-range communications,
which would involve multiple hops in a conventional wireline NoC, can
be realized by a single hop through the radio medium. Unfortunately, the
energy consumed by the RF transceiver into the radio hub (i.e., the main
building block in a WiNoC), and in particular by its transmitter, accounts
for a significant fraction of the overall communication energy. In order to alleviate
such contribution, two techniques have been proposed in this thesis.
A first solution consists in a runtime tunable transmitting power technique
for improving the energy efficiency of the transceiver. The basic idea is tuning
the transmitting power based on the physical location of the recipient
of the current communication. Specifically, based on the destination address
of the incoming packet, the radio hub tunes its transmitting power to
a minimum level, but high enough to reach the destination antenna without
exceeding a certain bit error ratio. The proposed technique applied on different
representative WiNoC architectures results in an average transmitter
energy reduction up to 50% without any impact on performance and with
a negligible overhead in terms of silicon area. A second solution focuses on
the impact of antennas orientation on energy figures and performs a design
space exploration for determining the optimal orientation of the antennas in
such a way to minimize the communication energy consumption. When the
antennas are optimally oriented, up to 80% transmitter energy saving has
been observed.
Unfortunately, energy consumed by WiNoC transceiver does not depend
by the transmitter but also by other modules including the receiver. In this
sense, in order to obtain a further energy reduction in this thesis we propose
a technique based on selectively turning off, for the appropriate number of
cycles, all the radio-hubs that are not involved in the current wireless communication.
The proposed energy managing technique is assessed on several
network configurations under different traffic scenarios both synthetic and
extracted from the execution of real applications. The obtained results show
that, the application of the proposed technique allows up to 25% total communication
energy saving without any impact on performance and with a
negligible impact on the silicon area of the radio-hub.
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Wang, Wei. "Power Module with Series-connected MOSFETs in Flip-chip Configuration". Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/36036.
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Power module design is needed for high system performance and reliability, especially in terms of high efficiency and high power density. Low parasitic impedance and thermal management is desired for the lower power loss and device stress.
For power module with high efficiency and improved breakdown voltage, this thesis proposes a novel series-connected power MOSFETs module. Three IRF7832 MOSFETs (30 V breakdown voltage) in series are simulated in a chopper circuit. The drain-source voltage sharing in switching off-mode shows that the devices can share voltage within their breakdown ranges. The switching characteristics are studied, and the switching energy losses without parasitic inductance and with 5 nH parasitic inductances are 203.38 µJ and 316.49 µJ, respectively. The critical parasitic inductance is the one connecting the source of the upper MOSFET and the drain of the middle MOSFET. The switching energy loss due to critical parasitic inductance is about 44.4% of the total switching energy loss. The layout is designed for the double-substrates direct-bond module and wire-bonded module using direct-bond-copper (DBC) substrate. Based on layout dimensions and packaging materials, the packaging moduleâ s parasitic parameters are obtained using Ansoft® Q3D extractor. Using parasitic inductance values from simulation, the switching energy losses of direct-bond module and wire-bonded module are 296.18 µJ and 238.99 µJ, respectively. Thermal management is then studied using Ansoft® ePhysics. The MOSFET junction-to-air thermal resistances of the double-substrate direct-bond module and the single-substrate wire-bonded module are 33oC/W and 82oC/W, respectively. Hence, by comparing the direct-bond module with a wire-bonded power module, direct-bond module shows lower parasitic impedances and better thermal management.
To test the breakdown voltage of series-connected power MOSFETs module, three TI DualCoolTM N-channel NexFET Power MOSFETs (25 V breakdown voltage) in series are assembled using flip-chip direct-bond technology. Three samples are assembled and the breakdown voltages are measured by using high-power curve tracer as 76 V, 82 V, and 72 V. The more accurate method for testing breakdown voltages by digital voltmeter obtains 77.51 V, 82.31 V, and 73.06 V. The series-connected power MOSFETs module shows compact volume, low parasitic impedances, thermal resistances and improved breakdown voltage. This power module has strong potential for use in applications that require minimized packaging size and parasitic inductance for high voltage, high switching frequency, and high efficiency.Master of Science
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Jeon, Woochul. "Design and fabrication of on chip microwave pulse power detectors". College Park, Md. : University of Maryland, 2005. http://hdl.handle.net/1903/3170.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2005.Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Ahmad, Waqar. "Core Switching Noise for On-Chip 3D Power Distribution Networks". Doctoral thesis, KTH, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-103566.
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Reducing the interconnect size with each technology node and increasing speed with each generation increases IR-drop and Ldi/dt noise. In addition to this, the drive for more integration increases the average current requirement for modern ULSI design. Simultaneous switching of core logic blocks and I/O drivers produces large current transients due to power distribution network parasitics at high clock frequency. The current transients are injected into the power distribution planes thereby inducing noise in the supply voltage. The part of the noise that is caused by switching of the internal logic load is core switching noise. The core logic switches at much higher speed than driver speed whereas the package inductance is less than the on-chip inductance in modern BGA packages. The core switching noise is currently gaining more attention for three-dimensional integrated circuits where on-chip inductance is much higher than the board and package inductance due to smaller board, and package. The switching noise of the driver is smaller than the core switching noise due to small driver size and reduced capacitance associated with short on-board wires for three-dimensional integrated circuits. The load increases with the addition of each die. The power distribution TSV pairs to supply each extra die also introduce additional parasitic. The core switching noise may propagate through substrate and consequently through interconnecting TSVs to different dies in heterogeneous integrated system. Core switching noise may lead to decreased device drive capability, increased gate delays, logic errors, and reduced noise margins. The actual behavior of the on-chip load is not well known in the beginning of the design cycle whereas altering the design during later stages is not cost effective. The size of a three-dimensional power distribution network may reach billions of nodes with the addition of dies in a vertical stack. The traditional tools may run out of time and memory during simulation of a three-dimensional power distribution network whereas, the CAD tools for the analysis of 3D power distribution network are in the process of evolution. Compact mathematical models for the estimation of core switching noise are necessary in order to overcome the power integrity challenges associated with the 3D power distribution network design. This thesis presents three different mathematical models to estimate core switching noise for 3D stacked power distribution networks. A time-domain-based mathematical model for the estimation of design parameters of a power distribution TSV pair is also proposed. Design guidelines for the estimation of optimum decoupling capacitance based on flat output impedance are also proposed for each stage of the vertical chain of power distribution TSV pairs. A mathematical model for tradeoff between TSV resistance and amount of decoupling capacitance on each DRAM die is proposed for a 3D-DRAM-Over-Logic system. The models are developed by following a three step approach: 1) design physical model, 2) convert it to equivalent electrical model, and 3) formulate the mathematical model based on the electrical model. The accuracy, speed and memory requirement of the proposed mathematical model is compared with equivalent Ansoft Nexxim models.QC 20121015
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Nassif-Khalil, Sameh G. "CMOS-compatible power MOSFETs for on-chip DC/DC converters". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0023/MQ50383.pdf.
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Hansson, Martin. "Low-Power Multi-GHz Circuit Techniques for On-chip Clocking". Licentiate thesis, Linköping : Linköping University, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7545.
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Khasawneh, Shadi Turki. "Low-power high-performance register file design for chip multiprocessors". Diss., Online access via UMI:, 2006.
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Sullivan, Owen A. "Embedded thermoelectric devices for on-chip cooling and power generation". Thesis, Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45867.
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Thermoelectric devices are capable of providing both localized active cooling and waste heat power generation. This work will explore the possibility of embedding thermoelectric devices within electronic packaging in order to achieve better system performance. Intel and Nextreme, Inc. have produced thin-film superlattice thermoelectric devices that have above average performance for thermoelectrics and are much thinner than most devices on the market currently. This allows them to be packaged inside of the electronic package where the thermoelectric devices can take advantage of the increased temperatures and decreased thermal lag as compared to the devices being planted on the outside of the package. This work uses the numerical CFD solver FLUENT and the analog electronic circuit simulator SPICE to simulate activity of thermoelectric devices within an electronics package.
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Leuschner, Stephan [Verfasser]. "CMOS Power Amplifiers for Single-Chip Radio Integration / Stephan Leuschner". München : Verlag Dr. Hut, 2018. http://d-nb.info/1162767766/34.
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Yu, Xuehong. "Silicon-embedded magnetic components for on-chip integrated power applications". Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/54243.
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The objective of the proposed research is to design, fabricate, characterize and test silicon-embedded magnetic components for on-chip integrated power applications.
Driven by the trend towards continued system multi-functionality and miniaturization, MEMS technology can be used to enable fabrication of three-dimensional (3-D) functional devices into the silicon bulk, taking advantage of the 'dead volume' in the substrate and achieving a greater level of miniaturization and integration. As an example, one of the challenges in realizing ultra-compact high-frequency power converters lies in the integration of magnetic components due to their relatively large volume.
Embedding 3-D magnetic components within the wafer volume and implementing high-power, through-wafer interconnect for connection to circuitry on the wafer surface is a promising solution for achieving ultra-compact power converters, in which digital control circuitry and power switches are located on the wafer surface, and suitable magnetic components are embedded within the silicon substrate. In order to do this, key tasks in the following areas have been accomplished: development of new fabrication technologies for silicon embedding and 3-D structure realization; creation of high-current, through-wafer interconnects for connection of the device to circuitry; ability to incorporate a variety of magnetic materials when performance enhancement of the device is needed; exploration of a new design space for the devices due to ultra-compactness and silicon interaction; understanding of the complicated loss mechanisms in the embedded devices; and demonstration of device performance and in-circuit operation.
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Shafik, Rishad Ahmed. "Investigation into low power and reliable system-on-chip design". Thesis, University of Southampton, 2010. https://eprints.soton.ac.uk/157719/.
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It is likely that the demand for multiprocessor system-on-chip (MPSoC) with low power consumption and high reliability in the presence of soft errors will continue to increase. However, low power and reliable MPSoC design is challenging due to conflicting trade-off between power minimisation and reliability objectives. This thesis is concerned with the development and validation of techniques to facilitate effective design of low power and reliable MPSoCs. Special emphasis is placed upon system-level design techniques for MPSoCs with voltage scaling enabled processors highlighting the trade-offs between performance, power consumption and reliability. An important aspect in the system-level design is to validate reliability in the presence of soft errors through simulation technique. The first part of the thesis addresses the development of a SystemC fault injection simulator based on a novel fault injection technique. Using MPEG-2 decoder and other examples, it is shown that the simulator benefits from minimum design intrusion and high fault representation. The simulator is used throughout the thesis to facilitate the study of reliability of MPSoC. On-chip communication architecture plays a vital role in determining the performance and reliability of MPSoCs. The second part of the thesis focuses on comparative study between two types of on-chip communication architectures: network-on-chip (NoC) and advanced microprocessor bus architecture (AMBA). The comparisons are carried out using real application traffic based on MPEG-2 video decoder demonstrating the trade-off between performance and reliability. The third part of the thesis concentrates on low power and reliable system-level design techniques. Two new techniques are presented, which are capable of generating optimised designs in terms of low power consumption and reliability. The first technique demonstrates a power minimisation technique through appropriate voltage scaling of the MPSoC cores, such that real-time constraints are met and reliability is maintained at acceptable-level. The second technique deals with joint optimisation of power minimisation and reliability improvement for time-constrained MPSoCs. Extensive experiments are conducted for these two new techniques using different applications, including MPEG-2 video decoder. It is shown that the proposed techniques give significant power reduction and reliability improvement compared to existing techniques.
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Kundan, Shivam. "Contention-Aware and Power-Constrained Scheduling for Chip Multicore Processors". OpenSIUC, 2019. https://opensiuc.lib.siu.edu/theses/2620.
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The parallel nature of process execution on chip multiprocessors (CMPs) has considerably boosted levels of application performance in the past decade. Generally, a certain number of computing resources are shared among the several cores of a CMP, such as shared last-level caches, shared-buses, and shared-memory. This ensures architectural simplicity while also boosting performance for multi-threaded applications. However, a consequence of sharing computing resources is that concurrently executing applications may suffer performance degradation if their collective resource requirements exceed the total amount of resources available. If resource allocation is not carefully considered, the potential performance gain from having multiple cores may be outweighed by the losses due to contention among processes for shared resources. Furthermore, CMPs with inbuilt dynamic voltage-frequency scaling (DVFS) may try to compensate for the performance loss by scaling to a higher frequency. For performance degradation due to shared-resource contention, this does not necessarily improve performance but guarantees a significant penalty on power consumption due to the quadratic relation of electrical power and voltage (P ∝ V^{2}*f).
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Gold, Brian. "Balancing Performance, Area, and Power in an On-Chip Network". Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/34137.
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Several trends can be observed in modern microprocessor design. Architectures have become increasingly complex while design time continues to dwindle. As feature sizes shrink, wire resistance and delay increase, limiting architects from scaling designs centered around a single thread of execution. Where previous decades have focused on exploiting instruction-level parallelism, emerging applications such as streaming media and on-line transaction processing have shown greater thread-level parallelism. Finally, the increasing gap between processor and off-chip memory speeds has constrained performance of memory-intensive applications.
The Single-Chip Message Passing (SCMP) parallel computer sits at the confluence of these trends. SCMP is a tiled architecture consisting of numerous thread-parallel processor and memory nodes connected through a structured interconnection network. Using an interconnection network removes global, ad-hoc wiring that limits scalability and introduces design complexity. However, routing data through general purpose interconnection networks can come at the cost of dedicated bandwidth, longer latency, increased area, and higher power consumption. Understanding the impact architectural decisions have on cost and performance will aid in the eventual adoption of general purpose interconnects.
This thesis covers the design and analysis of the on-chip network and its integration with the SCMP system. The result of these efforts is a framework for analyzing on-chip interconnection networks that considers network performance, circuit area, and power consumption.Master of Science
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Kennedy, Matthew D. "Power-Efficient Nanophotonic Architectures for Intra- and Inter-Chip Communication". Ohio University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1458232838.
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Chang, Tai-Hung, i 張台宏. "On Chip ESD Protection Design In A Power Chip". Thesis, 2000. http://ndltd.ncl.edu.tw/handle/28290813888272543142.
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碩士國立交通大學
電子工程系
88
The damages to CMOS VLSI circuits caused by static electronics is a very serious issue to CMOS VLSI design technologies. Especially, as the the technology is getting progress, the techniques that are used to improve the operation speed of CMOS circuits such as short channel length, thinner gate oxides, utilization of polyside and silicide, as well as the techniques to reduce the Hot-carrier effects such as LDD(Lightly Doped Drain) dramatically degrade the barring ability of ESD circuits. Due to the semiconductor process difference between high power CMOS circuits and low power CMOS circuits, we first implement a test chip with various high power CMOS process devices, then we measure all the characteristics that are related to ESD of the devices on the test chip. By analyzing these device characteristics, we can charactrize the effectiveness of ESD protection circuits and proposed new ESD protection circuits that are more efficient, especially for circuits with high power CMOS process. The ESD protection circuits we proposed can safely protect the CMOS circuits and make the ESD level confined to industrial application standard.
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Chang, Kuei-Chung, i 張貴忠. "Tailoring Network-on-Chip to Low-Power Application-Specific System-on-Chip". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/97265126503577713063.
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博士國立中正大學
資訊工程所
96
As the number of cores on a chip increases, power consumed by the communication structures takes a significant portion of the overall power budget. In order to mitigate the problem, we first propose a circuit-switched interconnection architecture, which uses extit{crossroad switches} to construct dedicated channels dynamically between any pairs of cores for non-huge application-specific SoCs. The structure of the crossroad switch is simple, which can be regarded as a NoC-lite router, and we can easily construct low-power on-chip networks with these switches by a system-level analysis tool. We also present the design methodology to tailor the proposed interconnection architecture to low-power structures by two optimization schemes with profiled communication characteristics. The first scheme is power-aware topology construction, which can build low-power application-specific interconnection topologies according to the traffic characteristics. To further reduce the power consumption, we propose the second optimization scheme to predetermine the operating mode of dual-mode switches in the NoC at run time to save the power of arbitrations and routings. We evaluate several interconnection techniques, and the results show that the proposed architecture is more low-power and high-performance than other solutions in the literature under some constraints and scale boundaries. We take multimedia applications as case studies, and experimental results show the power savings of power-aware topology construction approximate to 49% of the interconnection architecture. The power consumption can be further reduced approximately 25% by applying partially dedicated path mechanism.
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Xue, Xin-Tai, i 薛心太. "Wireless Power Conversion Chip and System". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/2v22x9.
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碩士國立臺北科技大學
電腦與通訊研究所
102
With the global alternative energy issues, electric cars began to walk on general road surface, the thesis used in the wireless charging technology for electric vehicle charging, the initial use of the object lock for the elderly scooter. In this thesis, establishment of the wireless charging system, the primary power transfer stage transfers power in wireless by Inductive Coupling Class E Power Amplifier. In order to optimize efficiency of wireless charging system and obtain enough charging distance, the inductive coupling class E power amplifier will be optimized efficiency first. Two coupling distance specific of the inductive coupling class E power amplifier are 7cm and 14 cm to be designed. The coupling coils are more than 23cm in diameter. Efficiency of the two coupling distance specific of the inductive coupling class E power amplifier were improved to more than 83%, and output power is more than 20W by realized class E power amplifier principle, impedance matching, coupling coil analysis and design. Second, bridge rectifier was joined in the secondary side. The efficiency was optimized after joining bridge rectifier. Finally, the system joins DC-DC buck converter, charger and lead acid battery to become a wireless charging system to achieve wireless charging function. Finally, in this thesis, it contains a high voltage DC-DC buck converter chip design, the design motivation is reducing the impact ratio of voltage drop relative to input voltage to improve system efficiency, the architecture of the DC-DC buck converter chip is voltage-mode control, the high voltage DC-DC buck converter are fabricated by TSMC 0.25 um CMOS technology.
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Wang, Tu-Chih, i 王度智. "Low Power Motion Estimation Chip Design". Thesis, 1999. http://ndltd.ncl.edu.tw/handle/44596893333905375012.
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碩士國立臺灣大學
電機工程學研究所
87
In this thesis, we propose a low-power architecture for Full-Search Block-Match Algorithm (FSMBA). Motion estimation algorithm is the most computation intensive part in the video coding system, and FSBMA is the optimal solution in motion estimation algorithm. In order to handle the huge amount of data-transfer and computation, various architectures have been proposed. But most of these architectures do not have the consideration of power consumption. This proposed 256-PE architecture provides low switch probability, less pipeline register while maintaining the same critical path, and low external-memory bandwidth requirement. Therefore, it has better power performance in the architecture level. When the video coding has technology advanced, there are more functions needed in the new video-coding standard, such as AP mode, PB-frame mode, and true B frame mode. They are also considered in the purposed architecture. It has 2 previous frame buffer and calculates 4 AP mode vectors and 1 normal mode vector concurrently. For the purpose of decreasing the external-memory bandwidth, an efficient previous data buffer is proposed. The size of this buffer is optimized for search range of -16 to +15, which is normally used in the video standard. The external-memory bandwidth can be reduced to 4 luminance pixel rate (3 luminance pixel rate for previous data, 1 luminance pixel rate for current data). This scheme uses small amount of memory to achieve this low external memory bandwidth. In order to integrate motion estimation of the whole codec system, it is important to design a good interface with other parts in the system. This design also implements an interface with DSP and has some programmability.
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Tang, Tze-Sheng, i 唐資生. "Power management for multi-chip module". Thesis, 1996. http://ndltd.ncl.edu.tw/handle/64792963049848359398.
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碩士國立臺灣大學
電機工程研究所
84
There have been several techniques developed for low-power design of circuits. One of these techniques is power management (PM). There are two types in PM implementation: static power management(SPM) and dynamic power management (DPM). SPM saves power when the system is idle, and DPM saves power during normal operation. The combination of SPM and DPM together can achieve maximum power-saving. We study the problem of power management, and discusses the design methodology of power management for multi-chip modules(MCMs). This thesis also proposes a general-purpose power management module(PMM) design for MCM. The PMM is designed to be added on an existing MCM which does not implement power management features. Therefore, power-saving can be achieved. PMM is designed by means of finite state machine (FSM) which keeps PMM as simple as possible. In this thesis, we classify the execution behavior of MCM into three types: single-cycle model, multi-cycle model and pipeline model. Each model has its own characteristic and power-saving efficiency. We will illustrate the implementation of single -cycle model and pipeline model, and simulate the power-saving results of these two model by means of software simulation in this work.
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Kumar, Abhishek. "Low-Power Network on chip Architecture". Thesis, 2017. http://ethesis.nitrkl.ac.in/8855/1/2017_MT_AKumar.pdf.
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Due to rapid development in the field of technology, we are able to integrate many devices on a single chip. So the communication between these devices becomes noticeably indispensable.The network on chip (NoC) is a technology which is used for such communicate on. The fundamental component of a NoC is a router. Be that as it may, in NoC design, there is power, area, and performance trade-off in topology, buffer sizes, routing algorithms and flow control mechanisms. For the NoC, the architecture of router must be an efficient one for balancing all things in the NoC and it should have lower latency and higher throughput. We implemented 5x5 NoC
architectures, and its buffer, switch control, router which are synthesis through vhdl language. A parametric analysis for different NoC was done using different for evaluating for the maximum frequency.To design the above design we use VERILOG HDL and VHDL language, the simulation and Synthesis done through “XILINX ISE 14.2”tool. The simulation results of shows the validation of functionality of the designs and the synthesis result shows the clear picture of resource. From the Parametric based evaluation of the different NoCs, the 5X5NoC archivedthe minimum of 435.374Mbps under the clock frequency off 100 MHz and the maximum of latency of41.5 clock cycles.
Through clock gating process on the NoC5x5, we saved significant die area equal to 6.13% as well as power saving of 47.82%, since it removed large numbers of muxes and replaced them with clock gating logic.
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Fang, Chia-Hao, i 方嘉豪. "Low-power bus coding technologies for on-chip and off-chip bus connections". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/66668903104097516051.
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博士中興大學
電機工程學系所
99
Since technology advances, the global interconnect power consumption and the delay of long wires are two of the most important key issues in nanometer technologies. In particular, both resistance and capacitive crosstalk effects between parallel wires result in serious problems such as crosstalk delay and power consumption. Furthermore, the crosstalk effects between parallel wires cause the power consumption and delay of on-chip buses worse than before. Thus, system designers must reduce the power consumption and delay of on-chip busses to improve the circuit performance in deep submicron (DSM) technologies. As display technology evolves, the standard of digital visual interface (DVI) 1.0 has replaced the conventional analog video graphics array (VGA) standard. However, the unit capacitance of LCD digital interface through a cable is up to 50pF/m for DVI and is also higher than that of PCB bus connections. The power dissipation is one of the most important key issues in LCD systems. Therefore, system designers also must reduce the power consumption to improve the LCD interface performance with the DVI standard. In this dissertation, we discuss two bus coding technologies: on-chip bus coding and off-chip DVI bus coding technologies. In order to reduce switching and coupling activities in on-chip instruction address busses, we propose a novel address bus coding technique, i.e. the XOR-BITS method. Address data on address busses are highly sequential, and the novel bus coding technique can reduce switching and coupling activities simultaneously. The realization of the bus codec requires a low-complex circuit and its delay is short after optimizations. In order to support the on-chip data bus coding, we propose two novel bus coding techniques, i.e. CDBI and ECDBI, to reduce the dynamic power dissipation and wire propagation delay. Data values on data busses are always random, and the novel bus coding techniques can reduce switching and coupling activities on busses simultaneously. The realizations of the CDBI and ECDBI methods only need low-complex architectures and the two methods also reduce redundant bus widths. However, coupling capacitances are several times larger than loading capacitances. Thus, we propose novel bus coding techniques to reduce crosstalk effects. The proposed bus coding methods reduce the dynamic power dissipation and wire propagation delay efficiently. They eliminate the worst crosstalk effect completely and reduce coupling capacitances largely. The novel bus coding techniques can also reduce switching and coupling activities simultaneously. Their realization architecture is low-complex, and the techniques also reduce redundant bus widths and eliminate the worst crosstalk effect. For the digital visual interface, we propose a new bus encoding technique, i.e. ADALP, to reduce the dynamic power dissipation on the interface efficiently. On the digital visual interface, digital images exhibit high correlation between adjacent pixels. The proposed encoding technique uses the absolute difference value and the codeword to reduce transition activities largely. Its realization architecture is low-complex and the DC balance is also considered. Finally, simulation results are shown to verify our bus coding techniques. We use C languages to model and calculate switching and coupling activities on busses. However, the proposed bus coding methods may require some overheads, including the area, delay and power of the bus codec circuits. Then we use Hspice circuit simulator, Design VisionTM logic synthesizer, and SOC EncounterTM physical design tool to estimate the area, delay, and power of the bus codec circuits.
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Huang, Yu-Chi, i 黃榆棊. "Low Power DSP Chip with Audio Application". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/szcgmq.
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碩士國立中正大學
電機工程研究所
92
Recently, SOC design has the properties of high arithmetic operation capa-bility, low cost and low power. Especially in portable product, the power dis-passion of chips influences greatly on operation time, battery life and weight. In low power techniques, dynamic power manager is very effective to re-duce power dispassion. It includes precomputation, guarded evaluation, gated-clock finite state machines, FSM decomposition and other techniques. Each technique uses different approach to identify input data which circuit can be disable to archive power saving. These techniques have similar properties that the circuit only used is enabled and the circuit does not used is disabled. The tech-niques can provide some low power effort. In this Thesis we propose a data flow manager method. This method is a mechanism based on data flow to create finite state machine owing to produce control signal of control unit, and archives lowdown power dissipation. The method is implemented at instruction-level in low power CCU DSP and a five stage pipeline low power MAC. This DSP is compatible with TI TMS320 C54x DSP chip. We compared power dissipation with the method and low power MAC, low power MAC only, the method only, and original DSP in 4 experiment targets. Finally, audio programs have been tested on the DSP. As the experiment result, we can get about 30% powers saving in FIR, IDCT, Echo programs.
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周雋鎧. "Application-Oriented Network-on-Chip Power Management". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/29556513748980523573.
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Fan, Shen-Cheng, i 范順程. "Design and Implementation of power Management Chip". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/82217195073118184163.
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碩士國立雲林科技大學
電機工程系碩士班
90
This thesis presents the design and implementation of a pulse-width-modulation (PWM) power management chip which has low voltage, small space, many choices of switching frequency, and high frequency switching. The oscillator of conventional PWM control chips is controlled by one external resistor and capacitor, however, the external resistor and capacitor occupy much space out of the chip. To reduce the space of the chip, the oscillator is put inside the chip. The operational principle and equivalent circuits of the proposed voltage-mode and current-mode controller are analyzed in detail. Computer simulation has been carried out to analyze the proposed voltage-mode and current-mode schemes. Two prototype chips of voltage mode controller have been constructed with UMC 0.5μm, N-well, 2P2M CMOS technology.
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Chen, Ming-Jia, i 陳明家. "Design of Low Power CMOS Prescaler Chip". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/20120048650580766118.
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碩士國立勤益科技大學
電子工程系
99
In modern communication systems, the frequency synthesizer is one of the most important circuits. The maximum frequency of a synthesizer is limited by the frequency divider and voltage-controlled oscillator (VCO). The characteristics of frequency divider dominate the performance of frequency synthesizer. We propose two new types of dual-modulus 2/3 dividers. In addition, a 1/2/3 divider modular with programmable capability is improved in this thesis. First, a low-power 2/3 divider Type-1 is designed to reduce in charge sharing. The measured results show that the experimental Type-1 chip has advantages of low voltage and low power consumption. Another design, 2/3 divider Type-2 reduces power consumption by using D-Flip-flop of dynamic floating input techniques. The post-simulation results show that power consumption is lower than Type-1 design especially for low-voltage operation. Finally, 1/2/3 divider modular with programmable capability is improved in reductions of transistor number and chip area. We had realized a 4/5 divider and 16/17 divider by composed of several 2/3 dividers in cascaded. The all simulations and chip implementations are based on TSMC 0.18-m CMOS technology.
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Vikas, G. "Power Optimal Network-On-Chip Interconnect Design". Thesis, 2010. https://etd.iisc.ac.in/handle/2005/1408.
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A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Hence, techniques to reduce interconnect power have become a necessity. In this thesis, we present a design methodology that gives values of bus width for interconnect links, frequency of operation for routers, in Network on Chip scenario that satisfy required throughput and dissipate minimal switching power. We develop closed form analytical expressions for the power dissipation, with bus width and frequency as variables and then use Lagrange multiplier method to arrive at the optimal values.
To validate our methodology, we implement the router design in 90 nm technology and measure power for various bus widths and frequency combinations. We find that the experimental results are in good agreement with the predicted theoretical results. Further, we present the scenario of an Application Specific System on Chip (ASSoC), where the throughput requirements are different on different links. We show that our analytical model holds in this case also. Then, we present modified version of the solution considered for Chip Multi Processor (CMP) case that can solve the ASSoC scenario also.
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Vikas, G. "Power Optimal Network-On-Chip Interconnect Design". Thesis, 2010. http://etd.iisc.ernet.in/handle/2005/1408.
Pełny tekst źródłaStreszczenie:
A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Hence, techniques to reduce interconnect power have become a necessity. In this thesis, we present a design methodology that gives values of bus width for interconnect links, frequency of operation for routers, in Network on Chip scenario that satisfy required throughput and dissipate minimal switching power. We develop closed form analytical expressions for the power dissipation, with bus width and frequency as variables and then use Lagrange multiplier method to arrive at the optimal values.
To validate our methodology, we implement the router design in 90 nm technology and measure power for various bus widths and frequency combinations. We find that the experimental results are in good agreement with the predicted theoretical results. Further, we present the scenario of an Application Specific System on Chip (ASSoC), where the throughput requirements are different on different links. We show that our analytical model holds in this case also. Then, we present modified version of the solution considered for Chip Multi Processor (CMP) case that can solve the ASSoC scenario also.
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Tain, Hao-Luen, i 田浩倫. "A new intelligent power chip for switched mode power supply". Thesis, 2000. http://ndltd.ncl.edu.tw/handle/17782740459883348127.
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