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1
Salman, Fatma. "EXPERIMENTAL STUDY OF PROFILES OF IMPLANTED SPECIES INTO SEMICONDUCTOR MATERIALS USING SECONDARY ION MASS SPECTROMETRY". Doctoral diss., University of Central Florida, 2007. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3056.
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ABSTRACT The study of impurity diffusion in semiconductor hosts is an important field that has both fundamental appeal and practical applications. Ion implantation is a good technique to introduce impurities deep into the semiconductor substrates at relatively low temperature and is not limited by the solubility of the dopants in the host. However ion implantation creates defects and damages to the substrate. Annealing process was used to heal these damages and to activate the dopants. In this study, we introduced several species such as alkali metals (Li, Na, K), alkali earth metals (Be, Ca,), transition metals (Ti, V, Cr, Mn) and other metals (Ga, Ge) into semiconductor substrates using ion implantation. The implantation energy varies form 70 keV to 200 keV and the dosages vary between ~ 1.0x1012 and ~5.0x1015 atoms/cm2. The samples are annealed at different temperatures from 300°C to 1000°C and for different time intervals. The redistribution behaviors of the implanted ions are studied experimentally using secondary ion mass spectrometry (SIMS). We observed some complex distribution behaviors due to the defects created during the process of ion implantation. The diffusivities of some impurities are calculated and compared to previous data. It was found that the diffusivities of implanted impurities is related to the dosages, annealing temperatures and the defects and damages caused by ion implantation. Additionally, as we go from one type of semiconductor to another, the diffusion behavior of the impurities shows a different trend.Ph.D.
Department of Physics
Sciences
Physics PhD
2
Steffens, Jonathan [Verfasser]. "Dependencies Between poly-Si Composition and Solar Cell Performance of poly-Si/SiOx Passivating Contacts / Jonathan Steffens". Konstanz : KOPS Universität Konstanz, 2020. http://d-nb.info/122106259X/34.
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Ullah, Syed Shihab. "Solution Processing Electronics Using Si6 H12 Inks: Poly-Si TFTs and Co-Si MOS Capacitors". Thesis, North Dakota State University, 2011. https://hdl.handle.net/10365/28902.
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The development of new materials and processes for electronic devices has been driven by the integrated circuit (IC) industry since the dawn of the computer era. After several decades of '"Moore's Law"-type innovation, future miniaturization may be slowed down by materials and processing limitations. By way of comparison, the nascent field of flexible electronics is not driven by the smallest possible circuit dimension, but instead by cost and form-factor where features typical of 1970s CMOS (i.e., channel length - IO ?m) will enable flexible electronic technologies such as RFID, e-paper, photovoltaics and health monitoring devices. In this thesis. cyclohexasilane is proposed and used as a key reagent in solution processing of poly-Si and Co-Si thin films with the former used as the active layer in thin film transistors (TFTs) and the latter as the gate metal in metal-oxide-semiconductor (MOS) capacitors. A work function of 4.356 eV was determined for the Co-Si thin films via capacitance-voltage (C-Y) characterization which differs slightly from that extracted from ultraviolet photoemission spectroscopy (UPS) data (i.e., 4.8 eV). Simulation showed the difference between the C-V and UPS-derived data may be attributed to the existence of 8.3 x 10 (exponent 10) cm-2 interface charge density in the oxide-semiconductor junction. Poly-Si TFTs prepared using Si6 H12-based inks maintained the following electrical attributes: field effect mobility of 0.1 cm2V-1s-1; threshold voltage of 66 V; and, an on/off ratio of 1630. A BSIM3 version 3 NFET model was modified through global parametric extraction procedure to match the transfer characteristics of the fabricated poly-Si TFT. It is anticipated that this model can be utilized for future design simulation for solution-processed poly-Si circuits.
4
Xiong, Zhibin. "Novel scaled-down poly-Si thin-film transistor devices and technologies /". View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20XIONG.
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Xu, Guo-Yuan, i 許國原. "Poly-oxide, niteridized poly-oxide, amorphous-oxide grown on poly-Si and amorphous-Si-characterization and modelings". Thesis, 1986. http://ndltd.ncl.edu.tw/handle/22052767226291035676.
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Huang, Chen-Shuo, i 黃震鑠. "A Study of Poly-Si EEPROM". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/69476004541115860739.
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碩士國立清華大學
電子工程研究所
93
With the suggestion of SoP to reduce cost and create additional value, the memory which is fabricated on glass substrate is essential for peripheral driver ICs application. We have found and studied a simple twins poly-Si TFTs EEPROM’s to suit the low temperature and simple process on glass substrate. First, we actually fabricated the simple twins poly-Si TFTs EEPROM’s and examined the feasibility of it. We successfully made it and that has good memory characteristic. The memory also exhibited that higher area ratio in coupling cell results in bigger on-current of devices and the better programming/erasing efficiency, the results of experiment were agreed with previous report. And than we present a concept of enhancing this memory cell performance by increasing the overlap of the source/drain and gate in coupling cell and realize it. In addition, the influence of different S/D dopant type in active cell was investigated, the N-type S/D dopant have batter memory efficiency than P-type S/D dopant.
7
Tsao, Kai-Yang, i 曹凱揚. "High Strength Si(111) Substrate with Poly-Si/α-Si Sealing Nanotexture for GaN". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/x7thcw.
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Chen, Y. C., i 陳盈佳. "Excimer Laser Crystallization of Si Film for Poly-Si TFT Device". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/10160203242103772068.
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博士國立交通大學
材料科學與工程系
90
In this study, the crystallization of a-Si with semi-Gaussian excimer laser was investigated. After the single-shot excimer laser process, the poly-Si region showed grains with a wide range of sizes corresponding to the Gaussian distributed laser energy. From the view of laser energy, three crystallization regimes were found on the ELA a-Si films: (1) partial-melting, (2) near-complete-melting and (3) complete-melting regimes. Large super-lateral-grain-growth (SLG) grains were observed in the near-complete-melting regime. The grain size of poly-Si film using multiple shot laser annealing was constrained by the Gaussein distributed laser energy. The large grains were suppressed due to the small grains formed in the first shot. In addition, the influence of substrate temperature on the properties of polysilicon films prepared by excimer laser annealing was studied. As the substrate temperature was elevated, the maximum crystallinity and grain size increased, while the laser energy needed to obtain the maximum crystallinity of polysilicon films decreased. The elevated substrate temperature also changed the surface roughness of polysilicon films. In the partially melting regime, the surface roughness increased with laser energy and substrate temperature. The surface roughness dropped pronouncedly before reaching the super-lateral-grain-growth regime. Further increasing energy to homogeneous nucleation regime did not change much of the surface roughness. Furthermore, the influence of laser energy on the properties of excimer-laser-annealed (ELA) amorphous silicon (a-Si) and as-deposited polycrystalline silicon (poly-Si) films has been studied too. For the ELA poly-Si films, in the low energy region, the crystallinity decreased with the energy. After reaching the minimum, it increased to the maximum, and then dropped down. No SLG grains were found in the near-complete-melting regime. The largest grains were observed in the partial-melting regime. The largest grain size (100 nm) of ELA poly-Si was less than that of ELA a-Si (130 nm). Finally, the effects of energy on the microstructure of amorphous silicon (a-Si) films annealed by two-step laser process were systematically investigated. For the low-crystallinity / small-grain films, which were formed after the first low-energy laser crystallization, the grain size decreased and then increased with the energy of second laser annealing. In contrast, for the high-crystallinity films, i.e. SLG-grain films, the grain size monotonously decreased with second laser energy increased. Two-step laser annealed poly-Si films revealed that fine grains were formed and extruded at the grain boundary after the second high-energy laser annealing. High performance poly-Si TFTs can be fabricated from the poly-Si films crystallized by low-energy annealing followed by second high-energy laser annealing. When the results were compared, the poly-Si TFT using the poly-Si film crystallized by single high-energy laser annealing showed poorer mobility and subthreshold swing.
9
羅傑. "Hybrid Logic/Resistive-switching Poly-Si Thin". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/64642943623743268165.
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碩士國立交通大學
電子研究所
100
A hybrid device combined a resistive switching (RS) memory and a logic transistor is proposed in this thesis. The hafnium oxide (HfO2) is not only the high-κ gate dielectric of the transistor but also the resistive switching layer of the RRAM, and the nickel metal gate also acts like a top electrode in a traditional MIM or MIS which is the most common structure in the previous RRAM paper . We first demonstrated a one-bit RS operation by applying a swept voltage on either the gate or drain to trigger the RS. A large amount of VT shift after the RS operation was found when we applied voltage on the gate. On the other hand, the VT shift is negligible when we swept the drain voltage with source grounded during the set/reset process. With the help of the constant voltage stress experiment, we realized that the reason caused the considerable VT shift after resistive switching operation was the charge trapping and wearout attributed to the high voltage applied during the set/reset process, which might induce F-N tunneling. iii Finally, we realized a two-bit-per cell operation mode in our structure with almost negligible VT shift after RS for the first time, which indicated that a new type of high-density memory using the resistive switching mechanism in a traditional transistor structure is possible.
10
Fang, Wei-nan, i 方偉南. "2-stage Hydrogenation of Poly-Si TFTs". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/89456485798733398689.
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碩士大同大學
光電工程研究所
98
In this research, a parallel-plate plasma reactor(PECVD) is used to hydrogenate polysilicon thin-film transistors(TFT’s). And we find that the H+ and H have different diffusing length at different substrate temperature. Hence, we propose a new theory named 『2-stage hydrogenation』and success to improve the poly-Si TFT’s by 『2-stage hydrogenation』.Vth has decreased 42%﹐SS has reduced 17.5%, mobility has increased 27%, and Ids on/off ratio has induced 38%.
11
Lee, De-Chang, i 李德章. "Self-Heating Model of Poly-Si TFTs". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/81406430205317982808.
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碩士國立清華大學
電子工程研究所
93
To realize the system-on-panel (SOP) technology, in which we combine the peripheral circuit and panel array circuit on the same glass substrate. In this thesis, we especially focus on the Self-Heating model of poly-Si TFTs. In our work , we base on RPI model , I try to simulation the Self-Heating effect in the device which DC operation . First, we proceeded from RPI model, then supplement the description of temperature dependence parameters, lean on the equivalent thermal circuits, the model could generate the temperature addition for described the device’s temperature increased upon DC operation. This turn-on model has been verified through experimental measurements on n-type device.
12
Wen-HsienWang i 王文賢. "Studies of Novel Color MIC Poly-Si Thin Film and Paste Screen Printing Poly-Si Solar Cells for BIPV Applications". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/80086769147848197161.
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Chen, Ting-Wen, i 陳廷瑋. "Process Development of mc-Si and poly-Si Thin Films for Solar Cells". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/68634394243830386308.
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碩士國立雲林科技大學
光學電子工程研究所
99
Usually, the conversion efficiency of amorphous silicon (??Si) thin film solar cell may degrade a lot due to the large amount of defects and the Steabler-Wronski effect upon illumination in the amorphous silicon thin film. Because the microcrystalline silicon (?徯-Si) film can reduce the S.W. effect that the ??Si/?徯-Si thin film tandem solar cells can have larger efficiency than ??Si solar cells. In this study, the Corning EXG glass was used as the substrate and the ??Si/?徯-Si thin films were deposited by PECVD with different ratios of SiH4 and H2 in the temperature range of 150℃ to 350℃. The p-i-n ??Si/?徯-Si thin film solar cells were made on the glass substrates by subsequently depositing the N-Si (with doping gas PH3) and I-Si layers by PECVD, followed by depositing the P-Si layer by AIC.Thermally evaporated Al layer was used as back electrode for the solar cell. The deposited films were characterized with FE-SEM, Raman spectroscopy, UV-VIS spectroscopy, Hall measurement, and I-V measurement. In this work, the deposited ??Si/?徯-Si thin films have the highest crystalline fraction of 69.9% obtained under the process condition of SiH4/(SiH4+H2) = 2%, gas pressure = 1.25torr, RF power = 50W, and substrate temperature = 250℃. N-layer process condition of PH3/( SiH4+H2+PH3) = 0.47%, process pressure = 1. 5torr, RF power = 150W, substrate temperature = 250℃ and the highest crystalline fraction of 43.3%
14
Liu, Chung, i 劉仲. "The Research of Poly-Si TFT Key Technologies". Thesis, 1997. http://ndltd.ncl.edu.tw/handle/85225440056740017844.
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碩士國立交通大學
電子工程學系
85
Fabricating low-temperature processed poly-Si thin film transistors on large area glass substrate is of great interest for flat-panel liquid crystal displays. In this work, some novel key technologies for improving poly-Si TFT performance have been studied. There are three subjects in this thesis. In the first part, the plasma immersion ion implantation (PIII) technology is utilized for source/drain doping to replace conventional ion implantation. Some advantages of PIII doping include high efficiency and excellent uniformity. PIII is suitable for TFTs on large area substrate because of the large area plasma source. The dopant activation conditions of PIII doping and comparison of PIII with conventional ion implantation have been studied in this part. In the second part, we improve poly-Si TFT performance by improving the quality of liquid phase deposited (LPD) gate insulator. Before the LPD oxide deposited in the poly-Si surface, a thin pre-oxide layer must exist in the poly-Si surface. We use RTP at very short time forming the LPD pre-oxide layer to replace the conventional LPD pre-oxide layer formed in RCA cleaning HCl+ H2O2 solution. The poly-Si TFTs with the novel method exhibit better characteristics than conventional devices. We also change the gate oxide post- anneal conditions by short time RTP to improve LPD gate oxide quality. Moreover, the reliability of these devices with different gate oxide conditions is also studied in detail. In the third part, a novel anodic oxide is formed as the gate insulator of poly-Si TFTs. The formation of anodic oxide is at room temperature. The poly-Si TFTs with anodic oxide as gate insulator exhibit well performance and would have great application potential for low-temperature processed liquid crystal displays.
15
Chen, Yu-Han, i 陳昱翰. "Asymmetric Raised Drain Poly-Si Thin Film Transistor". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/bmv7z3.
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Lee, Jui-Che, i 李睿哲. "n+poly emitters for Si solar cell application". Thesis, 2018. http://ndltd.ncl.edu.tw/handle/pn2yy5.
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碩士國立清華大學
材料科學工程學系
106
To attain high-efficiency silicon solar cells, suppressing the recombination of electrons and holes at the highly doped emitter and collector is the key to increase the open circuit voltage and energy conversion efficiency. Polysilicon contacts are one of the few promising materials. It is a structure with heavily doped polysilicon and thin oxide layer on the silicon substrate, commonly called Tunnel Oxide Passivated Contact (TOPCon). The reason why TOPCon can effectively lower the saturation current density is that the interface oxide layer between the polysilicon and silicon substrate blocks the minority carrier to reach the polysilicon layer. However, this layer of interfacial oxide also blocks the major carrier to transport, thus increasing the specific contact resistance(c). Therefore, high-performance polysilicon must be able to meet both low Jo and c。 In our study, we aim to achieve the low saturation current density as well as the specific contact resistance. For the analysis of lowering the saturation current density, we fabricate chemical oxide layer by NAOS and SPM method. Heavily doped polysilicon layer is deposited through LPCVD, and the dopant is activated through high temperature annealing. Based on PCD measurement, We attain the saturation current density with different annealing temperature and interfacial oxide layer. For the analysis of specific contact resistance, we design 5 masks to fabricate the structure for measuring the specific contact resistance. Finally under the condition of NAOS growing interfacial oxide with annealing temperature 875˚C, we attain the best result of Jo=3.2(fA/cm2)，c=3.3(mΩ-cm2).
17
Yang, Kun-Da, i 楊昆達. "Simulation of Double-gated Poly-Si Nanowire Transistors". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/29h782.
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碩士國立東華大學
電機工程學系
100
Device technology endeavor to achieve the target of faster and lower power consumption recently. For nanowires structure, it makes it having the characteristics of high sensibility and short detection time. The study simulated the characteristic of double-gated poly-Si nanowire transistors with the TCAD software. The device contains three modes: Single gate 1Mode、Single gate2 Mode and Double gate Mode. The simulation revealed double gate mode’s electrical characteristic is best. It has excellent channel control capacity which can significantly reduce subthreshold swing and increase on-off current ratio. Thus, we only take double gate mode in our discussion. We want to know if quantum effects will affect the characteristic of double-gated poly-Si nanowire transistors under double gate mode. So we added density gradient model to simulate device electrical characteristic, the simulation results showed that only use drift-diffusion model is very similar to drift-diffusion model plus density gradient model. Therefore we can just take drift-diffusion Model for our simulation under 6nm nanowire with. Our study also found that after removal of Gate2, the device has similar characteristics to the Double gate structure, therefore Gate2 does not need to be deposited to achieve similar characteristics to the Double gate Mode.
18
Chen, Jian-Liang, i 陳建良. "Study on low-temperature Poly-Si Nonvolatile memory". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/44497796029484437436.
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碩士國立清華大學
電子工程研究所
93
Development of the “System-on-glass” display with low temperature Poly-Si (LTPS) TFT has rapidly advanced recently. The display incorporated with nonvolatile memories becomes an attractive topic. In this study, nonvolatile memories using low temperature poly-Si process with oxide-nitride-oxide (ONO) stack structure on glass was studied and fabricated. The memory window should be lager than 1V to meet the logic memory circuit. The operation of nonvolatile memory is giving differential bias combination on gate, source and drain, in order to program and erase. The traps of grain boundary in poly-Si, however, maybe degrade the performance in some operational mode. There could be some reliability issue in low temperature poly-Si nonvolatile memory. We therefore investigate various operational modes in N-channel and P-channel so as to search which operational mode is reliable. Using Fowler-Nordheim tunneling to program and hot hole injection to erase, the threshold voltage memory has 1.5V at P/E time of 100ms. After 104 P/E cycles, the devices maintain a 1.5v threshold voltage memory.
19
Chen, Jue Jye, i 陳志傑. "Study of Poly-Si Spacer for VLSI Circuits". Thesis, 1993. http://ndltd.ncl.edu.tw/handle/65113894076454146540.
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碩士國立交通大學
電子研究所
81
At first ,different materials, including low pressure chemical vapor deposition (LPCVD) TEOS ,LP Si3N4 , plasma enhanced CVD (PECVD) oxide ,LPCVD borophosphosilicate glass (BPSG) and LPCVD Poly-Si ,have been systematically fabricated and the spacers for the VLSI circuits.The electrical properties shows that the Poly-Si is the best one of all the these spacers due to its highest dielectric constant ,K=11.9 , This result is consistent with the literatures.Although Si3N4 has the higher dielectric constant ,it encounters the stress problems so that it is not suitable for the practical application. BPSG and PE oxide are also excluded due to their impurity contents. Hence the remained two candidates ,TEOS and Poly-Si ,are further appraised in the second section of this study. The purpose of the second section is focused on the TEOS and Poly-Si spacers. By using TEOS and Poly-Si as the spacers with different over etching (O/E) times ,lightly doped drain (LDD) structures can be fabricated via the direct implantation of arsenic and boron ions through these spacers. Then ,this simplified LDD technology is evaluated to subsitute the conventional LDD process. Fortunely ,Poly-Si spacers with the O/E times of 50 sec and 60 sec can meet the requirement of hot carrier immunity comparable to that of the conventional N-MOS LDD devices. However ,too long O/E time of the Poly-Si spacers results in the deep penetration of the boron and cause the sub-micron P- MOS punch through after the high-temperature annealing at 950 C. Consequently ,the sub-micron PMOS with this Poly-Si spacer will exhibit the normal-on characterics.
20
Zhan, Tian-Hao, i 詹天皓. "Study on contact resistance of PtSi/poly-Si". Thesis, 1993. http://ndltd.ncl.edu.tw/handle/76918280060200274511.
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Xiao, Yi-Hsuan, i 蕭逸璿. "Advanced Technologies to Improve Poly-Si TFT's Characteristics". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/5pr93d.
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碩士國立交通大學
電子工程系所
92
This thesis consists of two parts. In the first part, the concept of Modified-Schottky-Barrier (MSB) FinFET was employed to fabricate MSB TFTs. In the second part, wet etching technique of HfO2 film was developed. It is a key process step to integrate HfO2 film into TFTs process. It is demonstrated that Ni-silicide can be applied to both n-channel and p-channel devices simultaneously. Process complexity can be reduced greatly. Although two-step silicidation is suggested for bulk CMOSFETs and MSB FinFETs, Ni-salicide structure can be formed by one step RTA at 500℃ in MSB TFTs because the Si source is limited in the S/D region and device dimension of TFTs is much larger than that of CMOSFETs or FinFETs. MSB TFTs with the suitable activation process shows the superior I-V characteristics compared to CN TFTs and SB TFTs. A rapid thermal activation at temperature between 600℃ to 650℃ results in the best device performance for both MSB pTFTs and MSB nTFTs. When MSB TFTs are activated at the temperature higher than 700℃, Ni-silicide agglomerates at gate electrode and device performance degrades. At suitable activation temperature, 30 seconds RTA is a suitable activation time for MSB TFTs. Besides these, higher implantation dose can provide more dopants to enhance device performance. Considering the device geometries, narrower channel width has few grain boundaries and trap states; therefore, threshold voltage slightly decreases. On the other hand, strong reverse short channel effect appears due to traps states of MMGB’s. Fortunately, it is not necessary to scale channel length of TFTs down to around 1um and hydrogen contained plasma treatment is expected to passivate defects at MMGB’s. It is strong believed that the MSB TFTs can achieve excellent device performance and can be applied to LTPS TFTs due to its low thermal budget feature. Temperature, including deposition temperature and post-deposition annealing temperature, is the most important factor to affect the wet etching behavior of HfO2 film. The film structure deposited at different temperatures is studied in this chapter and the influence of PDA temperature is also examined. The higher deposition temperature causes fewer dangling Hf-O bonds and higher post-deposition annealing temperature reconstructs the dangling and imperfect Hf-O bonds. Therefore, the wet rate is lower. Fortunately, implantation process can help to degrade Hf-O bonds, and let the HfO2 films become wet etch-able.
22
Liao, Ming-Kai, i 廖銘楷. "Bottom-gate Poly-Si Thin Film Transistor Nonvolatile Memory with Si nanocrystals Trapping Layer". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/70304427957106230801.
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Ping, Lin Shiou, i 林修平. "The Research of Low Temperature Oxidation by ECR on Crystalline Si and Poly-Si". Thesis, 1996. http://ndltd.ncl.edu.tw/handle/14876166830530379723.
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Wei, Liu Ta, i 劉大偉. "Fabrication and Characterization of Novel Poly-Si Nanowire Devices". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/81551826635764531679.
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碩士國立交通大學
電子工程系所
96
In this thesis, several multiple-gated (MG) poly-Si nanowire (NW) devices were fabricated and characterized. Our fabrication process is simple, low cot, and flexible for fabricating devices with identical NW structure but different gate configuration. It thus allows us to investigate the impacts of MG on the basic electrical characteristics as well as the variation of devices. The experimental results show that, as compared with devices with planar structure, much improved device characteristics in terms of better subthreshold swing, lower leakage, and higher on/off ratio are obtained. Among all NW structures, superior device performance is achieved as the gated portion of NW channel surface increases, owing to the higher surface-to-volume ratio. We also study the device variation issue by plotting the standard deviation of VTH as a function of . We found that the device with gate-all-around configuration exhibits the best control in terms of the variation. Besides, the deviation of planar devices is evidently higher than the NW ones because of wider depletion width and worse plasma treatment efficiency. Tri-gated SONOS devices were also fabricated and characterized with a process flow modified from the aforementioned one. It is confirmed that the NW devices have higher P/E speed than planar ones. For reliability issue, NW SONOS devices possess good retention and endurance characteristics. The memory window is larger than 0.5V after 10 years for a device after subjecting to 104 times of P/E cycles.
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ZHANG, SAN-RONG, i 張三榮. "Study of the dielectrics grown on Poly-Si films". Thesis, 1992. http://ndltd.ncl.edu.tw/handle/08062689074843028468.
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Chen, Chien-Liang, i 陳建良. "Study of Poly-Si Buffered Shallow Trench Isolation Technology". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/72414352195372640838.
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碩士國立臺灣科技大學
電子工程系
89
The conventional LOCOS-based isolation technology is questionable for ULSI generation due to its inherent bird’s beak, field boron encroachment, and non-planarity issues. Shallow Trench Isolation (STI) combined with chemical-mechanical polishing (CMP) is widely used for deep sub-micron devices due to its high package density and good isolation characteristics for the ULSI age. In Shallow Trench Isolation (STI) structures significant stress buildup in the silicon mesa is often observed during thermal cycling process after STI formation. The thermal cycling lead to tensile stress due to the difference of thermal expansion coefficients between the silicon substrate and the trench fill oxide. As the active area pitch decrease, an increase both in stress and leakage current density is observed. That is the stress induced a huge amount defects and those defects generate larger leakage current density. In this thesis, we proposed to provide a new method to eliminate the stress generating from STI structure formation. We deposit a thin Poly-Si film and use the dry etching technology to form the poly silicon spacer, which is used to be a buffer layer to eliminate the stress. We design several kinds of poly silicon buffer layer thicknesses, thermal cycling temperatures and active area pitches and try to find out the relations between the stress by measuring the leakage current.
27
Shih, K. H., i 石坤桓. "The Study of Low-Temperature Poly-Si TFT''s". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/86266059176487431586.
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碩士國立交通大學
電子工程系
89
We have proposed both electron beam annealing and Ni-salicidation techniques to improve the performance of low-temperature poly-Si TFT''s. For E-beam annealing, it is performed at room substrate temperature and only takes several minutes. Compared with conventional furnace annealing, both crystallization temperature and annealing duration are vastly decreased by E-beam annealing. Furthermore, larger poly-Si grains and superior device characteristics could be obtained. Therefore, E-beam annealing has high potential for future low thermal budget high-resolution display on glass or even plastic substrate application. For silicidation technique, the sheet resistance of Ni-silicided polysilicon is observed to be reduced by two orders of magnitude. By forming self-aligned NiSi at source/drain contacts and gate electrode, the threshold voltage, drain current and carrier mobility of TFT''s are greatly improved. Therefore, the Ni-salicidation process of just one-step 4000C, 30sec annealing is a simple and effective method to enhance low-temperature poly-Si TFT''s performance.
28
jun-min, lin, i 林俊銘. "The reliability study of Poly-Si thin -film transistors". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/43537324633696371883.
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碩士國立交通大學
電子工程系
89
Utilizing polycrystalline silicon thin-film transistors (Poly-Si TFTs) as on-glass pixel switching elements and peripheral driver circuits is the future trend for fabricating active-matrix liquid-crystal displays (AMLCDs). The improvement of the electrical characteristic and the reliability of the low-temperature process Poly-Si TFTs are important issues. In this thesis, we proposed a new structure and studied the relibiality of the low-temperature process Poly-Si TFTs using the dynamic stress. In the first part, the dynamic stress on the low-temperature processed polycrystalline silicon thin-film transistors (poly-Si TFTs) is studied under two different stress conditions. As the falling time becomes short, the channel carriers can be accelerated to become hot and repelled from the channel region. Therefore, the device is seriously degraded by these hot channel carriers during the falling transient periods. It is also found that the degradation is more serious in the short channel device than that in the long channel one. In addition, as the stress frequency increases, the degradation is enhanced. Moreover, the reduced degradation under the high stress temperature is also expected to be related to the reduced hot carrier effect under the high temperature stressing. In the second part, we proposed a new structure with two sub-gate region, and we obtained that the slope variation and the threshold voltage shift of new structure were better than that of the conventional TFTs, and we are sure that they will improve substantially for the optimum condition for the new structure.
29
JHONG, YI-FAN, i 鍾邑帆. "High Performance Poly-Si Nanowire Junctionless Thin Film Transistor". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/09801309479957032938.
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碩士逢甲大學
電子工程學系
105
Abstract In recent years, many papers on junctionless transistor (JLT) have been published. Among these papers, the gate all around (GAA) structure showed a superior performance. However, in some GAA devices with suspended nanowires, the etching effect of the nanowire and the shake is more serious during SC1 cleaning/rinse process. These reasons will result in damage to the nanowires, bending and even fracture, and thus worsen the electrical performance of GAA devices. Therefore, the device with GAA structure often encountered difficulties in the clean/rinse process. In this paper, in order to improve the difficulties encountered above, it is proposed to deposit N+ Poly-Si as the bottom gate under the nanowire channel and etch the L-shaped pattern as a support region for the nanowire channel in order to avoid the influence of the cleaning process. Moreover, the proposed structure is similar to a GAA control over the nanowire channel. Additionally, the active layer of as-deposited N+ Poly-Si is annealed to reduce the defects between the grains and grains, leading to an improved electrical property of device. The advantage of the proposed structure is that the process is relatively easy and it can avoid the difficulties encountered in the clean/rinse process. According to the measured results and data extraction, the proposed device shows VTH= -0.65 V, S.S= 177 mV/Dec, DIBL=0.4 V / V and ION / IOFF ratio as high as 2.31 × 107.
30
Chang, Kai-Hsiang, i 張凱翔. "The study of multigate Poly-Si Thin-Film Transistors". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/30168709489216678656.
Pełny tekst źródłaStreszczenie:
碩士逢甲大學
電子工程所
99
Polycrystalline silicon thin-film transistors (Poly-Si) are used widely in various field, such as active-matrix liquid crystal displays (AMLCDs), solar cell, active matrix organic light emitting diode (AMOLED) and flash memories because of their high mobility and driving current. In recent year, the device is promising candidate to be used in display system-on-panel (SOP) as memory and controller. Then the conventional poly – Si TFT is not enough in term of the speed and the current drive capability. To increase the speed and the current of the poly-Si TFT, a double gate structure was proposed to provide an effective way to enhance the current drive capability of poly- Si TFT. Due to the double gate provides an additional current path. However the double gate is an attractive approach, there has the high electric field near the drain junction. It causes the device a larger leakage current and aggravates the kink effect than the convention structure. Then the light doped drain (LDD) combines the double gate. It has a effective way to improve the high electric field of double gate. Then the LDD also can reduce the leakage and maintain the high on-current. But the structure needs two the process of the expensive CMP. In the past, the dual gate had reported. We know that the gate and the channel relationship. It has a good controlled to the channel and not confer the gate length. It this letter, we propose the dual gate length to effecting the device performance. We only need to change the gate mask. And my structure also effectively reduce the nonideal effect neat the drain junction. My structure requires an extra mask to increase the cost. Keyword: DCTFT, dual gate, nonideal effect.
31
Fan, Yang-Wen, i 范揚文. "Sensing Mechanism of Surface Modified Poly-Si Nanowire FET". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/73409260180515596602.
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碩士國立交通大學
工學院加速器光源科技與應用碩士學位學程
102
Polycrystalline silicon nano-wire field effect transistor (p-Si NW FET), possessing low cost and easy fabrication, was applied for ammonia gas sensor. The sensing ability is defined by INH3/IN2 at certain gate voltage, in which IN2is the baseline. The typical ratio is around 1~3 at 0.5 ppm level of ammonia gas. In order to further enhancing the ammonia sensing ability, 3, 7-Bis[7-(9, 9-di-n-hexylfluoren-2-2yl)]-9, 9-di-n-hexylfluoren-2-yl] dibenzothiophene-S, S-dioxide was applied for polycrystalline silicon surface modification. The surface modified p-Si NW FET showed 4 times enhancement compared to the unmodified p-Si NW FET. The polarity shift on the organic-inorganic interface was suspected the main reason. The charge transfer phenomena were verified by UPS and XPS with synchrotron light source (TLS). The data suggested that the hydrogen-bond formed between NH3molecule and S, S-dioxide functional group caused the polarity shift at organic layer.
32
Chao-Yu, Meng. "Fabrication and Analysis of Poly-Si Thin Film Transistor and Si Nanowire Field Effect Transistor". 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2407200619491100.
Pełny tekst źródła
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Lin, Chieh-Chih, i 林建志. "HSPICE Modeling and Simulation of Passive Pixel Sensors in a-Si & poly-Si Technology". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/57867636577831558386.
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碩士國立清華大學
電子工程研究所
93
Recently, new imaging devices that take advantage of the TFT array have been developed in the non-display field. The majority of touch-enabled AMLCDs , active matrix liquid crystal display, are based on resistive, capacitive or inductive touch technology. All these solutions require externally added components or screens, which add cost and reduce optical performance. If we can match the passive pixel sensor circuit and use them on the medical image, we can promote the detection rate of the disease by a wide margin. In this way, a photodiode can be integrated into each pixel of the TFT array, or a photoconductive layer can be formed on the TFT array. Thus, the electric charge generated in the photo-detective can be stored in the pixel, depending on the outside of light signals. Then, the charge intensity information can be read out as the imaging data by sequential line-addressing. Passive pixel sensors provide an alternative to the conventional Active Pixel Sensor (APS) for high-density CMOS imaging arrays. Similar to the history of the single-transistor DRAM cell, this one-transistor pixel cell boasts one main advantage over the APS. It can achieve a high fill-factor in a smaller area, leading to a high density array of pixels with high quantum efficiency. Learn in the reports of several experiments, a major weakness in passive pixels is a signal-dependent parasitic current that can contaminate charge signals in different parts of the array. In this thesis we use HSPICE as the tool, and simulate several important parameters in passive pixel sensor circuit in amorphous Si TFT. The simulation result in the thesis demonstrates that, with the photo sensor current as small as 10-12 to 10-15 (A), the signal is not influenced by parasitic current in the circuit and can be conveyed out without deterioration. According to the result of our study, if it can be practically applied to the products design, and if the result is good, we believe that the application of passive pixel sensor with amorphous Si TFT will move a big step forward and be adopted to use widely in different consumer products.
34
Meng, Chao-Yu, i 孟昭宇. "Fabrication and Analysis of Poly-Si Thin Film Transistor and Si Nanowire Field Effect Transistor". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/91299119763967689187.
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博士國立臺灣大學
電機工程學研究所
94
The fabrication and analysis of poly-Si thin film transistor (TFTs) and Si nanowires (SiNWs) field effect transistor were studied in this thesis. The poly-Si with regular and large grain was fabricated by employing metallic pads as the heat sinks and with underlying silicon oxynitride (SiON) as the heat absorption layer. The TFTs fabricated by this method achieves a field effect mobility of 246 cm2/V-sec and an on/off current ratio exceeding 5×105. Besides, the degradation behavior of body-contact (BC) polysilicon thin film transistors under DC and AC stress were investigated and compared with conventional ones. It was found that the reliability of body-contact poly-Si TFTs is better than the conventional TFTs under both DC and AC stress conditions. After 1000s AC stress, the degradation of BC poly-Si TFTs become an order of magnitude less than the conventional ones. Therefore, a model was proposed to explain the degradation improvement of body-contact poly-Si TFTs. The fabrication of SiNWs has been demonstrated using excimer laser annealed gold nanoparticles as the catalyst and vapor-liquid-solid (VLS) growth. Scanning electron microscopes images of the excimer laser annealed Au nanoparticles from 2.5, 5, and 10 nm Au film showed that the nanoparticles had mean diameters of 12, 13, and, 15nm, respectively. The results show that the diameter controlled uniform silicon nanowires can be obtained utilizing controlled thickness of Au film combined with suitable laser power density. The un-doped and boron-doped SiNWs grown via VLS mechanism were studied. The diameters of un-doped and boron-doped SiNWs varied from 18.5 to 75.3 nm and 26.6 to 66.1 nm, respectively. The critical growth temperature of boron-doped SiNWs is 10 ℃ lower than that of un-doped ones and the diameters of the boron-doped SiNWs is always larger than that of the un-doped ones under different growth temperatures. This is because that the introduction of diborane enhanced the dissociation of SiH4 which determines the growth process of SiNW. Un-doped, N-type, and P-type doped SiNWs were grown at 460oC and 25 torr. The intensity ratio of anti-Stokes/Stokes (IAS/IS) peaks is used as an index of the sample temperature. Different SiNWs exhibit different Raman frequency shifts because their compressive stresses due to heating differ. The slopes of the IAS/IS peak ratio versus the Raman frequency for boron-doped, un-doped, phosphorous-doped SiNWs and bulk Si are -0.078, -0.036, -0.035 and -0.02 per cm-1, respectively. The different slopes reveal the different heating-induced compressive stresses in the SiNWs with different dopants and bulk Si. The electric-field-directed growth of SiNWs was performed utilizing Au film with different thicknesses. It is found that the 1 and 0.5 nm Au film are more suitable for the electric-field-directed growth of SiNWs due to the formation of separated Au clusters during the thermal evaporation. Besides, the electric field in the range 0.5~2.5 V/μm are suitable for the direction controlled growth of SiNWs. For further improvement of the position and direction controlled growth of SiNWs, the 20 nm Au nanoparticles were used as the catalyst to control the diameter of SiNWs. In the self-aligned structure, parts of the SiNWs across the gap become huger and the possible DC plasma enhance coating model is proposed to explain the phenomenon. It is also found that the position controlled structure with one sided Au catalyst is better and more suitable for the position and direction controlled SiNWs growth. Finally, the position and direction controlled SiNWs FETs were successfully fabricated by electric field directed growth. It demonstrates the feasibility to fabricate the SiNWs array and electrical devices with low cost.
35
Huang, Tien-Chun, i 黃添鈞. "Poly-Si TFTs Fabricated by Electroless Plating Pd Induced Crystallization of Amorphous Si Thin Films". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/15791725423933629973.
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碩士國立交通大學
材料科學與工程系
90
In our previous work, a novel method, electroless plating Pd induced a-Si crystallization (EPIC), was used to replace the PVD Pd during MIC/MILC process. The crystallinity and film structure of MIC/MILC poly-Si by EPIC method had also been investigated. According to results, EPIC method could be suggested to fabricate poly-Si TFT device. In this study, EPIC-TFT´s was fabricated by using high temperature SPC-TFT´s parameters to find out the problem sources in EPIC-TFT´s. Palladium silicide contamination and non-induced a-Si regions were main reasons caused worse performance in EPIC-TFT´s. Then, a two-step conventional furnace annealing (CFA) combined with high temperature rapid thermal annealing (RTA) was proposed to improve performance of EPIC-TFT´s. The two-step conventional furnace annealing step could reduce palladium silicide contamination and high temperature rapid thermal annealing step could improve crystallinity. Electrical properties of EPIC-TFT´s also could be improved.
36
Liou, Yu-Ling, i 劉禹伶. "A Study on the Fabrication and Characterization of Poly-Ge NWTFTs and Junctionless Poly-Si NWFETs". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/16866933398935808112.
Pełny tekst źródłaStreszczenie:
碩士國立交通大學
電子研究所
99
In this thesis, two kinds of nanowire devices, namely, poly-Ge nanowire thin film transistors (NWTFTs) and junctionless (JL) poly-Si nanowire field effect transistors (NWFETs) were fabricated and investigated. Poly-Ge NWTFTs were realized with a novel approach by adopting the sidewall spacer etching technique for NW channel formation. Solid phase crystallization (SPC) was utilized to transform amorphous Ge (α-Ge) to poly-Ge. By adopting multiple-gated structure, ON/OFF current ratio is increased to 104 and subthreshold swing (S.S.) is improved to 0.64V/dec. Besides, poly-Ge NWTFTs with independent double-gated (DG) configuration are characterized and compared. Each gate can be biased independently to manipulate the device. JL poly-Si NWFETs were fabricated in a simplified manner duo to the fact that the source/drain (S/D) and channel was formed simultaneously without implantation. JL devices show better on-state performance and lower series resistance. On the other hand, the inversion mode (IM) NWFETs present ultra-low S.S. lower than 60mV/dec under specific operation conditions.
37
Liu, Shu Chun, i 劉書君. "Study on FEM analysis procedure for Poly-Si Film Crystallization". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/96643173964839934617.
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碩士國立臺灣科技大學
機械工程系
92
The use of Excimer laser to produce poly-Si thin film with large grain sizes is one of the most concentrated research topics in the TFT display field. The setting of many parameters will influence the qualities of the poly-Si thin film, but there is no general relationship between parameters and qualities of the poly-Si thin film. Proper parameters can be obtained through the use of the trial and error procedure in the laboratory. The thesis uses the commercial FEM software, ANSYS, to simulate the Excimer laser annealing, and aims to establish the correct analysis procedure so as to build the foundation on fast setting of annealing parameters. This study successfully developed the simulation method by using the transient analysis capabilities of ANSYS with heat transform phenomenon including phase change with latent heat. The thesis also investigates the relationship between the laser intensity and the crystallization velocity and the relationship between the thickness of the a-Si thin film and the crystallization velocity.
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Sheu, Tzu-Shiun, i 許子訓. "Characteristics of Poly-Si Nanowire TFTs with Gate-All-Around". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/47451115451883427765.
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碩士國立交通大學
奈米科技研究所
96
This thesis successfully demonstrated gate-all-around polycrystalline silicon (poly-Si) thin film transistor with side-wall spacer nanowire technique. The poly-Si nanowire after solid phase crystallization for 24 hours was released to suspension from buried oxide by using wet etching process in DHF solution. The released suspending nanowire was followed by a 20-nm TEOS deposition as gate oxide. Subsequently, a 200-nm-thick in situ n+ doped poly-Si layer was deposited and patterned to form a gate electrode. The channel about 70-nm-width was wrapped around by gate oxide and poly-Si gate. This gate-all-around structure exhibits superior channel controllability and immunity of short channel effects (SCEs). After the device fabricated, it was passivated by NH3 plasma treatment for 1 hour at 300℃. The device performance was improved after NH3 plasma treatment, including a high driving current, a steep subthreshold swing(114 mV/dec), a better mobility, near free of DIBL, a high on/off current ratio(>108), and suppression of kink effect induces by ion impacted ionization. In addition, the multiple channel nanowire TFTs have a lower threshold voltage, a steeper subthreshold swing(107 mV/dec), a higher on/off current ratio(>109), but gate induce drain leakage was serious than dual-channel device. In this 3-D structure, the increase of gate area over channel to suppress SCEs and leakage current were accomplished. The device shows excellent performance than conventional planar transistor, double gate fin-FET, and tri-gate fin-FET. Due to the poly-Si TFTs were limited by the defects of grain boundary, the carrier mobility and on/off ratio are difficult to enhance, GAA structure was adopted to overcome these limitations. The trap state density of grain boundaries can be further reduced after NH3 plasma passivation.
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Huang, Hsuan-Yun, i 黃瑄勻. "Fabrication and Characterization of Novel Poly-Si Nanowire SONOS Devices". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/09784184643964341317.
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碩士國立交通大學
電機學院微電子奈米科技產業專班
98
In this thesis, poly-Si nanowire (NW) SONOS devices with various multiple-gated (MG) configurations were fabricated by utilizing a simple and low-cost technique. With a slight modification in the fabrication procedure, three different types of MG configuration, namely, SG, ΩG, and gate-all-around (GAA), were realized in the fabricated devices. It thus allows us to unambiguously investigate the impacts of different MG configurations on the basic electrical characteristics. The experimental results show that much improved device characteristics with GAA devices are achieved as compared with the other types of devices, owing to the superior gate controllability over NW channel with the GAA structure, which results in a higher ON-current, suppressed short channel effects, and steeper sub-threshold swing (SS) for NWs. For SONOS characterization, we confirmed that the round-shape GAA NW channel exhibits the best performance in P/E characteristics among all splits. For reliability issues, the GAA devices also exhibit good data retention and endurance characteristics. The memory window can be larger than 0.5 V after 10 years for a device after subjecting to 104 times of P/E cycles at room temperature.
40
Tsai, Ping-Yu, i 蔡秉諭. "Study of electron transportation in Si3N4/Poly-Si/Si3N4 nanostructures". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/75658848161084120355.
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碩士義守大學
電子工程學系
91
This thesis is to use electron beam lithography (EBL) to fabricate Single Electron Transistor (SET) and study single electron tunneling phenomena of nanostructure under Coulomb Blockcade effect. Single Electron Transistor is the important device in nanostructure semiconductor. The feature, electron transport in the SET devices one by one, is different from MOSFET in which there are uncountable electrons transporting. Due to the characteristics of low power and high density integration of SET, it may be a promising candidate to be a new potential device. We use Leica WEPRINT 200 E-Beam Lithography Direct-Writing System as lithography writer to fabricate our sample. For improving the resolution, we study the lithography condition, including the dosage of electron beam (about 14~15µC/cm), the choice of photoresist (NEB22 or DSE, the thickness of photoresist) and Proximity effect. With careful design, we can define ultra small size pattern on Si substrate. In order to reduce thermal tunneling, we measure our sample in dilution refrigerator system. Dilution refrigerator can provide a low-temperature environment (below 30K). Due to the ultra small signal of a SET device, we need to take care of environment noise. Thus good shielding is necessary in order to avoid unwanted tunneling event to measure our sample to promote our system accuracy.
41
Lin, Zi-Yan, i 林資硯. "Simulation of N-type Double-gated Poly-Si Nanowire Transistors". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/62859594616324820840.
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42
Wang, Chiau Jui, i 王昭瑞. "The Fabrication and Characterization of Poly-Si Thin Film Transistors". Thesis, 1995. http://ndltd.ncl.edu.tw/handle/77988511983027386763.
Pełny tekst źródła
43
Liu, Ping-Jung, i 劉秉融. "Study of Tunneling-Field-Effect Poly-Si Thin-Film-Transistors". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/4awym3.
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碩士國立臺灣科技大學
電子工程系
99
In the progress of the electronics industry, the scale down of conventional metal oxide semiconductor thin film transistor (MOSFET) will emerge some reliability problems, such as short-channel effect, hot- carrier effect and drain-induce barrier lowering (GIDL). When scale down of tunneling-field-effect transistor, it can make lower short-channel effect, hot-carrier effect and drain-induce barrier lowering. It can solve the reliability problems that it is scaled down. Although tunneling-field effect transistor (TFET) can improve disadvantages of conventional MOSTFT, some issues of TFET are still need to be resolved. To obtain higher-performance TFET in this study, the design of new device structure and the analysis of device relative parameters are carried out via process and device simulation. Above this new device structure, a counter-doping pocket region enclosing the source region is formed. The performance of device is really improved by changing different dose and energy. From the simulation results, the newly designed TFET structures do have better performance than the conventional TFET. TFET improves the leakage current problem of conventional MOSTFT that is produced in high scaling fabrication. Since there are not too many additional process steps compare with MOSFET, the new designed of TFET is an advancing device instead of MOSTFT in the future.
44
Jeng, Jyh-Nan, i 鄭志男. "Application of Liquid-Phase Deposited Oxide to Poly-Si TFT". Thesis, 1996. http://ndltd.ncl.edu.tw/handle/84041340742358973759.
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碩士國立交通大學
電子研究所
84
In this work, the applications of liquid-phase deposited (LPD) oxide to poly-Si TFTs have been studied. There are four subjects. In the first part, the application of LPD oxide to low-temperature processed (LTP) poly-Si TFTs is developed. A high quality thiner LPD oxide (10 nm) was successfully developed and applied as gate oxide to LTP poly-Si TFTs. For the poly-Si TFTs before hydrogenation, thereshold voltage (Vt) of 3.9V, subthreshold swing (S) of 0.57V/decade and ON/OFF current ratio of 2X10^6 are obtained. Moreover, scaling down gate oxide thickness also reveals several advantages, such as thereduction of Vt and S, the improvement of electrical characteristics uniformity and the endurance of short- channel effect. Compared to LTP TFTs with CVD gate oxide, the devices with ultra-thin LPD︹ate oxide are quite stable. In the second part, the application of LPD oxide to high- temperature processed (HTP) poly-Si TFTs is developed. Poly-Si TFTs with LPD oxide as gateinsulator have first been fabricatied by using a high-temperature quartz basedtechnology. The thermal effects during high-temperature on TFT performance andreliablity were investigated. The high-temperature devices exhibit much improvement in performance due to the rearrangement of LPD oxide structure andthe reduction of sheet resistance. In the third part, the application of LPD oxide to poly-Si TFTs with low thermal budget is developed. A N2O-anneal process by RTA method have been used to the fabrication of poly-Si TFTs with LPD gate oxide. This process is effective to improve the electrical characteristics and reduce thermal budget.The improvement in electrical characteristics can be attributed to the passivation effect due to incorporated nitrogen on active layer, as well as high-temperature annealing effect on LPD oxide and polysilicon film. In the last part, the applicaion of LPD oxide as a mask is developed. A novel poly-Si TFT has been first developed by using selective LPD SiO2-xFx formation technology as a mask. The TFT is suitable to high-density SRAM circuit applications, and it exhibits excellent electrical characteristics: Vt of 0.52V, S of 0.52V/ decade, ON/OFF current ratios of 2.8X10^7 and field effect mobility of 33.75cm2/V.sec after NH3 plasma treatment.
45
Chen, Wei-Hao, i 陳韋皓. "Poly-Si Nanowire Junctionless Thin Film Transistor on Nitride Film". Thesis, 2016. http://ndltd.ncl.edu.tw/handle/85654305503152599493.
Pełny tekst źródłaStreszczenie:
碩士國立中興大學
光電工程研究所
104
To continuously reduce the transistor’s size with higher device’s performance is necessary, when poly-Si thin-film transistors (TFTs) are further applied to system-on-panel (SOP) and three-dimensional integrated circuits (3-D ICs). In recent years, many studies have paid attentions to junctionless TFT’s, not only planer TFT’s structure is fabricated but also multiple-gate junctionless nanowire transistors are proposed and showing good device’s performances. In this paper, we focus on the fabrication of nanowire junctionless thin film transistor on nitride film, and by this fabrication we can get the better process in nanowire structure. As well-known, the gate-all-around (GAA) and double gate structures can obtain the great characteristics in TFTs. But there are some problems in the fabricating procedures. For the GAA structure, the nanowire channels must be suspended in the air, and the suspended nanowire channels might be subjected to more physical damages, and more chemical injure in the cleaning process of wet bench. For the double gate structure, it can achieve good characteristics without suspended nanowire channels, but it needs extra fabricating steps to form a bottom gate before fabricating the nanowire channels, Therefore the fabrication of double gate TFTs is more complicated, and the fabrication cost is also higher than the conventionl ones. In this paper, the nanowire channels are fabricated on the nitride film to prevent from the physical and chemical damages during the fabricating procedures. The junctionless poly-Si TFTs with triple-gate and multiple nanowires structures exhibit good electrical characteristics without complex processes and higher cost.And the yield of the proposed TFTs can be improved to 92%, as compared to that of wet oxide film TFT only being 44%.
46
Chang, Yu Shuo, i 張佑碩. "Study of Vertically Stacked Poly-Si Nanosheet Field-Effect-Transistor". Thesis, 2016. http://ndltd.ncl.edu.tw/handle/38303284729222024224.
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碩士國立清華大學
工程與系統科學系
104
The market demand for portable electrical equipments increase dramatically year by year., emphasizing on multifunctional, small size, light weight, etc. Under keen mutual competition environment of economic market and electronic industries, it has triggered electronic industries to improve their products to develop toward low cost, high density and scale down to react to the rapid demand in the market. Nevertheless, the expectation of scaling transistors suffered more and more difficult to design, whether the short channel effect in devices or the challenge of fabrication process are very vital research topics. In this thesis, we successfully demonstrate the stacked nanosheert(NS) vertically inversion-mode field-effect-transistors(VM-FET) in 3D stacked integrated circuit (IC) applications to increase transistor density for continuing Moore’s law. It may offer valuable information with regard to their practical industry and academic applications. This research which focus on is showing the following: (1) device process, (2).basic device characteristics analysis, (3) device simulation. In the fabrication process, we adopt the oxidation trimming method to form thin active layer and exhibit quasi-crystal channel due to the reduction of grain boundaries and defects. It is beneficial for excellent electrical performance. In the basic device characteristics analysis. First part will show the comparison of stacked NS VM-FET and conventional NS IM-FET. The stacked structure exhibits the better characteristics owing to due to the parallel resistance, resulting in smaller total resistance and improved around 4.36 times current drivability and higher ON/OFF current ratio up to 108. The 3D stacked layer can increase on-state current and maintain low leakage current. Second part will discuss about the change of width dimension for I-V characteristics with stacked structure. However, in the device simulation, we use Sentaurus TCAD to analyze and confirm the measured basic electrical characteristics As a result, we proposed the stacked NS VM-FET has better electrical characteristics. Additionally, it may offer a possible next-generation CMOS device solution and be applied in advanced system-on-chip and 3D stacked IC applications.
47
Chang, Chien-Hung, i 張建宏. "Study on the Fabricated Process of Poly-Si Thin Film". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/tau6hc.
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碩士國立成功大學
工程科學系碩博士班
90
When excimer laser is used in making poly-Si thin films from a-Si ones, it will be very helpful if the temperature distributions of working pieces, including Si, SiO2 and glass layers, can be predicted in advance. In this thesis, a mathematical model was built to analyze the temperature fields of the working pieces under different control parameters, such as laser energy intensity, pulse width. The numerical scheme is the finite difference method and the specific heat-enthalpy method was used to handle the release of latent heat. From the computing results, the temperature distributions considering the effect of latent heat are quite different from those without latent heat so that the latent heat should not be ignored in the analysis. With very high energy intensity, excimer laser makes the Si film’s temperature increase and decrease very rapidly, which leads to high melting and solidifying rates. The SiO2 layer could effectively decrease heat transferred to the glass substrate and keep most heat from laser in the Si layer. The solidification time of poly-Si can increase by raising the laser energy intensity, the temperature of glass substrate and the pulse width. Adjusting the pulse coverage fraction properly can induce the temperature gradient in the x direction, perpendicular to the incident direction of laser, which will increase the grain size in the x direction. Increasing the laser energy intensity and the temperature of glass substrate could enlarge the melting depth of Si and decrease the average growth rate of poly-Si. From these results, it can be concluded that the proposed model could predict the temperature distributions of the working pieces and the analyses of different control parameters could provide preferable working conditions, which are good for the crystal growth of poly-Si
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Luo, E.-Lun, i 羅以倫. "Characteristics of Poly-Si Nanowire TFTs With Asymmetric Ω-Gate". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/57313995967352113819.
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碩士國立交通大學
材料科學與工程學系奈米科技碩博士班
99
In order to increase the gate control capacity on the channel, multi-gate structure has been extensively studied as the critical dimension of thin-film transistors (TFTs) is scaled down. Both gate-all-around (GAA) TFTs and TFT SONOS memory devices have been demonstrated previously with excellent channel controllability and outstanding memory properties. On the base of previous research, polysilicon nanowire transistors with Ω-Gate have been proposed in this study. The Ω-Gate structure exhibits good controllability on channel presumably due to the coverage of four corners of device channel. Moreover, an asymmetric gate structure by converting one side of Ω-Gate into Tri-Gate such that lower leakage current and off state current enhanced. A comparison on the characteristics of both Ω-Gate devices and asymmetric Ω-Gate device were performed. It is found that changing the ratio of asymmetric structure can effectively change the device characteristics. When in high proportion of asymmetric structure, the device characteristics close to the Tri-Gate, and for low proportion of asymmetric structure, devices exhibit characteristics like Ω-Gate devices which possess properties including a high driving current, a steep subthreshold swing, a high on/off current ratio, low gate induced drain leakage (GIDL),and short channel effect suppression(SCE). The proposed asymmetric gate devices, combining Tri-gate and Ω-Gate, successfully inhibit the leakage current and suppress off-state current, and enhance the overall electrical properties.
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Jin, Da-Wei, i 金大為. "Fabrication of poly-Si TFT by Shadow mask patterning process". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/55400876302456532415.
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碩士國立臺灣科技大學
光電工程研究所
96
we have also successfully only used shadow mask to fabricate poly-silicon TFT on glass substrate. The On/Off current ratio of Id is 103, mobility is 10 cm2/V-S, threshold voltage (Vt) is 5 V and the subthreshold Swing (S) is 1.75 V/decade.
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Zheng, Zhi-Nan, i 鄭志男. "APPLICATION OF LIQUID－PHASE DEPOSITED OXIDE TO POLY－SI TFT". Thesis, 1996. http://ndltd.ncl.edu.tw/handle/91375040451393657045.
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