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1
Boyd, Richard L. (Richard Lyman). "An optical phase locked loop for semiconductor lasers". Thesis, Massachusetts Institute of Technology, 1988. http://hdl.handle.net/1721.1/35943.
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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Aeronautics and Astronautics, 1988.Title as it appeared in MIT Graduate list, June, 1988: An optical phase locked loop.
Includes bibliographical references.
by Richard L. Boyd.
M.S.
2
Beaudoin, Francis. "Design and implementation of a gigabit-rate optical, receiver and a digital frequency-locked loop for phase-locked loop based applications". Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=79996.
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The large demand for high-bandwidth communication systems has brought down the cost of optical system components. To be competitive in a crowded market, implementation of the different systems of an optical transceiver on a single chip has become mandatory.CMOS technologies, especially state-of-the-art processes like the 0.18mum CMOS, permit integration of huge amounts of transistors per millimeter square. Furthermore, deep-submicron CMOS processes have similar RF performances to their traditional bipolar equivalent. It is therefore a small footstep to go to congregate high-speed analog circuits with digital cores on a single die.
This thesis addresses two of the building blocks found in an optical communication receiver, namely the analog front-end receiver and a digital frequency-acquisition based clock-and-data recovery circuit. The latter reduces the headcount of bulky passive components needed in the implementation of the loop filter by porting the analog loop to the digital domain. This circuit has been successfully fabricated and tested.
Finally, an optical front-end, comprising a transimpedance amplifier and a limiting amplifier is proposed and fabricated using a standard 0.18mum CMOS process. The speed of this circuit has been pushed up to 5Gb/s. Different techniques have been employed to increase the effective bandwidth of the input amplifier, namely the use of a constant-k filter.
3
Kassa, Wosen Eshetu. "Modélisation électrique de laser semi-conducteurs pour les communications à haut débit de données". Thesis, Paris Est, 2015. http://www.theses.fr/2015PEST1016/document.
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Cette distinction est également valable pour le genre des individus (homme/femme). L'étude menée a montré que l'approche utilisant l'information spectrale des contours des phalanges permet une identification par seulement trois phalanges, à un taux EER (Equal Error Rate) inférieur à 0.24 %. Par ailleurs, il a été constaté « de manière surprenante » que la technique fondée sur les rapports de vraisemblance entre les phalanges permet d'atteindre un taux d'identification de 100 % et un taux d'EER de 0.37 %, avec une seule phalange. Hormis l'aspect identification/authentification, notre étude s'est penchée sur l'optimisation de la dose de rayonnement permettant une identification saine des individus. Ainsi, il a été démontré qu'il était possible d'acquérir plus de 12500/an d'images radiographiques de la main, sans pour autant dépasser le seuil administratif de 0.25 mSvL'avancement de la communication numérique optique dans les réseaux longue distance et d'accès a déclenché les technologies émergentes dans le domaine micro-ondes / ondes millimétriques. Ces systèmes hybrides sont fortement influencés non seulement par les déficiences de liens optiques mais aussi des effets de circuits électriques. Les effets optiques et électriques peuvent être ainsi étudiés en même temps en utilisant des outils assistés par ordinateur en développant des modèles de circuit équivalent de l'ensemble des composants de liaison tels que les lasers à semi-conducteurs, modulateurs, photo-détecteurs et fibre optique. Dans cette thèse, les représentations de circuit des composants de liaison photoniques sont développées pour étudier des architectures différentes. Depuis la source de lumière optique est le principal facteur limitant de la liaison optique, une attention particulière est accordée aux caractéristiques, y compris les plus importants de simples lasers en mode semi-conducteurs. Le modèle de circuit équivalent de laser qui représente l'enveloppe du signal optique est modifié pour inclure les propriétés de bruit de phase du laser. Cette modification est particulièrement nécessaire d'étudier les systèmes où le bruit de phase optique est important. Ces systèmes comprennent des systèmes de télécommande hétérodynes optiques et des systèmes auto-hétérodynes optiques. Les résultats de mesure des caractéristiques de laser sont comparés aux résultats de simulation afin de valider le modèle de circuit équivalent dans des conditions différentes. Il est démontré que le modèle de circuit équivalent peut prédire avec précision les comportements des composants pour les simulations au niveau du système. Pour démontrer la capacité du modèle de circuit équivalent de la liaison photonique pour analyser les systèmes micro-ondes / ondes millimétriques, le nouveau modèle de circuit du laser avec les modèles comportementaux des autres composants sont utilisés pour caractériser différents radio sur fibre (RoF) liens tels que la modulation d'intensité - détection directe (IM-DD) et les systèmes RoF hétérodynes optique. Signal sans fil avec des spécifications conformes à la norme de IEEE 802.15.3c pour la bande de fréquence à ondes millimétriques est transmis sur les liens RoF. La performance du système est analysée sur la base de l'évaluation de l'EVM. L'analyse montre que l'analyse efficace des systèmes de photonique micro-ondes / ondes millimétriques est obtenue en utilisant des modèles de circuit qui nous permet de prendre en compte les comportements à la fois électriques et optiques en même tempsThe advancement of digital optical communication in the long-haul and access networks has triggered emerging technologies in the microwave/millimeter-wave domain. These hybrid systems are highly influenced not only by the optical link impairments but also electrical circuit effects. The optical and electrical effects can be well studied at the same time using computer aided tools by developing equivalent circuit models of the whole link components such as semiconductor lasers, modulators, photo detectors and optical fiber. In this thesis, circuit representations of the photonic link components are developed to study different architectures. Since the optical light source is the main limiting factor of the optical link, particular attention is given to including the most important characteristics of single mode semiconductor lasers. The laser equivalent circuit model which represents the envelope of the optical signal is modified to include the laser phase noise properties. This modification is particularly necessary to study systems where the optical phase noise is important. Such systems include optical remote heterodyne systems and optical self-heterodyne systems. Measurement results of the laser characteristics are compared with simulation results in order to validate the equivalent circuit model under different conditions. It is shown that the equivalent circuit model can precisely predict the component behaviors for system level simulations. To demonstrate the capability of the equivalent circuit model of the photonic link to analyze microwave/millimeter-wave systems, the new circuit model of the laser along with the behavioral models of other components are used to characterize different radio-over-fiber (RoF) links such as intensity modulation – direct detection (IM-DD) and optical heterodyne RoF systems. Wireless signal with specifications complying with IEEE 802.15.3c standard for the millimeter-wave frequency band is transmitted over the RoF links. The system performance is analyzed based on EVM evaluation. The analysis shows that effective analysis of microwave/millimeter-wave photonics systems is achieved by using circuit models which allows us to take into account both electrical and optical behaviors at the same time
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Pinheiro, Ricardo Bressan. "Projeto de filtros tipo \"só-pólo\" para malhas de sincronismo de fase de alta frequência". Universidade de São Paulo, 2010. http://www.teses.usp.br/teses/disponiveis/3/3139/tde-30112010-153611/.
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Apresenta-se a evolução dos sitemas de comunicação, com ênfase especial nos sistemas com tecnologia óptica. Discute-se a necessidade contínua do aumento de capacidade de tais sistemas de comunicação, e a consequente repercussão sobre os futuros sistemas ópticos. Em vista da necessidade do aumento de capacidade dos futuros sistemas de comunicação óptica, apresentam-se em seguida duas propostas recentes da literatura, sendo uma referente à realização de um gerador de pulsos ópticos estreitos, e a outra referente à implementação de um extrator de relógio realizado com técnicas ópticas. Apresenta-se um breve resumo da teoria das malhas de sincronismo de fase, ou PLLs, mostrando como as duas propostas discutidas realizam funções típicas desses sistemas. Ressalta-se a necessidade dos PLLs de sistemas ópticos possuirem ganhos de malha (parâmetro K) elevados. Após a caracterização dos requisitos necessários para PLLs de futuros sistemas ópticos, e após um resumo de alguns conceitos necessários da teoria de redes e filtros elétricos, apresentam-se dois tipos de projeto de filtros para aqueles PLLs. As duas formas de projeto tem como objetivo viabilizar o uso de filtros de tipo e ordem arbitrários. Um tipo de projeto visa a realização da função de transferência do PLL com a curva de resposta igual à de um filtro escolhido. O outro tipo de projeto parte da realização do filtro de loop do PLL com as características de um tipo de filtro escolhido, e define métodos para ajustar a função de transferência resultante para esse PLL. Apresentam-se algoritmos para o cálculo de parâmetros importantes nos dois procedimentos. Após a discussão dos dois pontos de vista de projeto, apresentam-se exemplos de realização de PLLs de acordo com as técnicas apresentadas. Para cada exemplo, mostram-se as curvas de resposta em frequência tanto do PLL como do correspondente filtro de loop, bem como o lugar das raízes e a resposta de captura do PLL obtido. O processo de captura foi estudado por simulações que procuram reproduzir o mais fielmente possível as condições reais de implementação, sem entretanto considerar efeitos de ruído. Finalmente, mencionam-se brevemente possíveis linhas de pesquisa futuras, sendo o foco principal o uso de filtros com pólos e zeros finitos.The evolution of communication systems is discussed, with emphasis on optical technology. Special consideration is given to the continuous need for increasing the capacity of such systems, and the impact over future optical communication. In view of the great demands imposed over the capacity of future optical systems, an overview is presented of two recent proposals found in the literature, one of such proposals being the implementation of a generator of short optical pulses, and the other being a clock extractor device realized through the use of optical techniques. A brief review is made of phase-locked loop (or PLL) theory, to show how the discussed proposals could be used to realize tipical functions found in these systems. The very high loop gains (the so-called parameter K) that must be used in PLLs of optical communication systems are emphasized. After discussion of the necessary characteristics for PLLs of future optical systems, and also after a review of some concepts of the theory of electrical networks and filters, two design procedures for filters to be used in such PLLs are presented. Both designs have the goal of allowing the use of loop filters with any type and order. The first type of design has the objective to realize a PLL transfer function that has a frequency response identical to the response of a chosen type of filter. The other design starts with a chosen type of filter for a PLL loop filter, arriving to an suitable PLL transfer function. Some algorithms for determination of important design parameters are also presented. After the discussion of the two types of design, some examples of PLLs obtained by such methods are presented. For each example, frequency response curves are presented for the PLL and the respective loop filter, as well as the root locus and the capture response for the PLL so obtained. The capture process was studied through the use of simulations with parameters intended to approximate real implementation conditions, although noise effects are not considered. Finally, some possible research lines are discussed, whose main focus is on filters with finite poles and zeros.
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Terlemez, Bortecene. "Oscillation Control in CMOS Phase-Locked Loops". Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4841.
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Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications.
Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analog (or semi-digital) oscillators having various advantages over their digitally controlled counterparts, prompted the proposal of the digitally-controlled phase-locked loop. This research, then, investigates a class of otherwise analog PLLs that use a digital control path for driving a current-controlled oscillator. For this purpose, a novel method for control digitization is described where trains of pulses code the phase/frequency comparison information rather than the duration of the pulses: Pulse-Stream Coded Phase-Locked Loop (psc-PLL).
This work addresses issues significant to the design of future PLLs through a comparative study of the proposed digital control path topology and improved cutting-edge charge-pump PLLs.
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Gdeisat, Munther Ahmad. "Fringe pattern demodulation using digital phase locked loops". Thesis, Liverpool John Moores University, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.521754.
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Souder, William Dai Foster. "A low power 10 GHz phase locked loop for radar applications implemented in 0.13 um SiGe technology". Auburn, Ala, 2009. http://hdl.handle.net/10415/1631.
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Bordonalli, Aldario Chrestani. "Optical injection phase-lock loops". Thesis, University College London (University of London), 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.244183.
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Ratcliff, Marcus Dai Foster. "Phase locked loop analysis and design". Auburn, Ala, 2008. http://hdl.handle.net/10415/1452.
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Eklund, Robert. "Linearization of Voltage-Controlled Oscillators in Phase-Locked Loops". Thesis, Linköping University, Department of Science and Technology, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5366.
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This is a thesis report done as part of the Master of Science in Electronics Design Engineering given at Linköping University, Campus Norrköping. The thesis work is done at Ericsson AB in the spring of 2005. The thesis describes a method of removing variations in the tuning sensitivity of voltage-controlled crystal oscillators due to different manufacturing processes. These variations results in unwanted variations in the modulation bandwidth of the phase-locked loop the oscillator is used in. Through examination of the theory of phase-locked loops it is found that the bandwidth of the loop is dependent on the tuning sensitivity of the oscillator.
A method of correcting the oscillator-sensitivity by amplifying or attenuating the control-voltage of the oscillator is developed. The size of the correction depends on the difference in oscillator-sensitivity compared to that of an ideal oscillator. This error is measured and the correct correction constant calculated.
To facilitate the measurements and correction extra circuits are developed and inserted in the loop. The circuits are both analog and digital. The analog circuits are mounted on an extra circuit board and the digital circuits are implemented in VHDL in an external FPGA.
Tests and theoretical calculations show that the method is valid and able to correct both positive and negative variations in oscillator-sensitivity of up to a factor ±2.5 times. The bandwidth of the loop can be adjusted between 2 to 15 Hz (up to ±8 dB, relative an unmodified loop).
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Veillette, Benoît R. "On-chip characterization of charge-pump phase-locked loops". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0017/NQ44617.pdf.
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Stockmaster, Michael. "Tracking of multiple sinusoids using coupled phase-locked loops". The Ohio State University, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=osu1412945248.
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Choi, Pyung. "An equivalent circuit structure macromodel for analog phase locked loops". Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/14875.
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Wilcock, Reuben. "Switched-current filters and phase-locked loops : methods and tools". Thesis, University of Southampton, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.416917.
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Pamarti, Sudhakar. "Enabling techniques for wide bandwidth fractional-N phase locked loops /". Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3091331.
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Thacker, Timothy Neil. "Phase-Locked Loops, Islanding Detection and Microgrid Operation of Single-Phase Converter Systems". Diss., Virginia Tech, 2009. http://hdl.handle.net/10919/29281.
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Within recent years, interest in the installation of solar-based, wind-based, and various other renewable Distributed Energy Resources (DERs) and Energy Storage (ES) systems has risen; in part due to rising energy costs, demand for cleaner power generation, increased power quality demands, and the need for additional protection against brownouts and blackouts. A viable solution for these requirements consists of installation of small-scale DER and ES systems at the single-phase (1Φ) distribution level to provide ancillary services such as peak load shaving, Static-VAr Compensation (STATCOM), ES, and Uninterruptable Power Supply (UPS) capabilities through the creation of microgrid systems. To interconnect DER and ES systems, power electronic converters are needed with not only control systems that operate in multiple modes of operation, but with islanding detection and resynchronization capabilities for isolation from and reclosure to the grid.
The proposed system includes control architecture capable of operating in multiple modes, and with the ability to smoothly transfer between modes. Phase-Locked Loops (PLLs), islanding detection schemes, and resynchronization protocols are developed to support the control functionality proposed.
Stationary frame PLL developments proposed in this work improve upon existing methods by eliminating steady-state noise/ripple without using Low-Pass Filters (LPFs), increasing frequency/phase tracking speeds for a wide range of disturbances, and retaining robustness for weakly interconnected systems.
An islanding detection scheme for the stationary frame control is achieved through the stability of the PLL system interaction with the converter control. The proposed detection method relies upon the conditional stability of the PLL controller which is sensitive to grid-disconnections. This method is advantageous over other methods of active islanding detection mainly due to the need for those methods to perturb the output to test for islanding conditions. The PLL stability method does not inject signal perturbations into the output of the converter, but instead is designed to be stable while grid-connected, but inherently unstable for grid-disconnections.
Resynchronization and reclosure to the grid is an important control aspect for microgrid systems that have the ability to operate in stand-alone, backup modes while disconnected from the grid. The resynchronization method proposed utilizes a dual PLL tracking system which minimizes voltage transients during the resynchronization process; while a logic-based reclosure algorithm ensures minimal magnitude, frequency, and phase mismatches between the grid and an isolated microgrid system to prevent inrush currents between the grid and stand-alone microgrid system.Ph. D.
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Lee, Kun Seok. "Wideband phase-locked loops with high spectral purity for wireless communications". Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/44882.
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The objective of this research is to demonstrate the feasibility of the implementation of wideband RF CMOS PLLs with high spectral purity using deep sub-micron technologies. To achieve wide frequency coverage, this dissertation proposed a 45-nm SOI-CMOS RF PLL with a wide frequency range to support multiple standards. The PLL has small parasitic capacitance with the help of a SOI technology, increasing the frequency tuning range of a capacitor bank. A designed and fabricated chip demonstrates the PLL supporting almost all cellular standards with a single PLL. This dissertation also proposed a third order sample-hold loop filter with two MOS switches for high spectral purity. Sample-hold operation improves in-band and out-of-band phase noise performance simultaneously in RF PLLs. By controlling the size of the MOS switches and control time, the nonideal effects of the MOS switches are minimized. The sample-hold loop filter is implemented within a 45-nm RF PLL and the performance is evaluated. Thus, this research provides a solution for wideband CMOS frequency synthesizers for multi-band, multi-mode, and multiple-standard applications in deep sub-micron technologies.
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Sharkia, Ahmad. "On the design of type-i integer-n phase-locked loops". Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/54504.
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The phase-locked loop (PLL) is an essential building block of modern communication and computing systems. In a wireless communication system, a PLL is almost always used as the local oscillator (LO) that synthesizes the required frequency for data transmission and reception. In wireline and optical communication systems, PLL-based clock and data recovery (CDR) circuits are often employed for the extraction of the clock signal from the incoming data signal, and aligning the recovered clock edge with the incoming data for optimal bit-error rate (BER) performance. Furthermore, in microprocessor and field-programmable gate array (FPGA) systems, PLLs are typically used for clock generation.
Although phase-locking is a very mature research topic, its continuous application in modern integrated circuits (ICs) and systems, requires continuous improvement in its performance, power consumption, and manufacturing costs. Analog Type-II PLLs are among the most widely used category of PLLs in CMOS (complementary-metal-oxide-semiconductor) ICs, mainly due to their robustness, superior performance and their well-established theory. However, analog Type-II PLLs require a large area in loop-filter (LF) and employ noisy and difficult-to-design charge-pumps (CPs). All-digital PLLs are also widely used, but they suffer from the strict jitter requirements on time-to-digital converters (TDCs).
We propose a Type-I PLL that uses a small LF area, does not require bias-generation circuits or CP, and consumes low power. A pulse-width-modulated (PWM) voltage output from the phase-frequency detector (PFD) is fed to a simple RC single-pole LF. Two major limitations of conventional Type-I topologies – limited lock-range and large reference spur – are overcome by increasing the PFD gain with a combination of a voltage booster and a digital level shifter, and a sample-and-hold (S/H) envelope detector, respectively. Furthermore, a saturated-PFD (SPFD) is proposed to reduce cycle slipping and to further improve the lock-range and lock-time. A proof-of-concept prototype 2.2-to-2.8 GHz PLL occupies a core area of 0.12 mm² in 0.13-μm CMOS and achieves 490 fsrms random jitter, -103.4 dBc/Hz in-band phase-noise, -65 dBc reference spur, 2.5 μs worst-case lock-time while consuming 6.8 mW from a 1.2 V supply.Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
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Watson, David Rae. "Application of phase locked loops to rapid acquisition in satellite communications". Thesis, University of Cambridge, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.387068.
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Li, Shenggao. "High Performance GHZ RF CMOS IC's for Integrated Phase-Locked Loops". The Ohio State University, 2000. http://rave.ohiolink.edu/etdc/view?acc_num=osu1392372325.
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Zhu, Peiqing. "Design and characterization of phase-locked loops for radiation-tolerant applications". Ann Arbor, Mich. : ProQuest, 2008. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3331229.
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Thesis (Ph.D. in Electrical Engineering)--S.M.U.Title from PDF title page (viewed Mar. 16, 2009). Source: Dissertation Abstracts International, Volume: 69-11, Section: B Adviser: Ping Gui. Includes bibliographical references.
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Kim, Seongwon. "Built-in self-test technique for high-speed phase-locked loops /". Thesis, Connect to this title online; UW restricted, 2001. http://hdl.handle.net/1773/5957.
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Thain, Walter E. "A methodology for modeling noise and spurious responses in phase-locked loops". Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/13462.
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Upadhyaya, Parag. "A 5 GHZ low power, low jitter and fast settling phase locked loop architecture for wireline and wireless transceiver". Online access for everyone, 2008. http://www.dissertations.wsu.edu/Dissertations/Summer2008/P_Upadhyaya_072308.pdf.
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Thayaparan, Subramaniam. "Delay-locked loop techniques in direct sequence spread-spectrum receivers". Thesis, Hong Kong : University of Hong Kong, 1999. http://sunzi.lib.hku.hk/hkuto/record.jsp?B21904108.
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Bachmann, Adrian H. "Phase-locked Fourier domain optical coherence tomography /". Lausanne : EPFL, 2007. http://library.epfl.ch/theses/?nr=3847.
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Thèse Ecole polytechnique fédérale de Lausanne EPFL, no 3847 (2007), Faculté des sciences et techniques de l'ingénieur STI, Programme doctoral Photonique, Institut d'imagerie et optique appliquée IOA (Laboratoire d'optique biomédicale LOB). Dir.: Theo Lasser, Rainer Leitgeb.
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Davis, R. G. "Two-port millimetre wave oscillators and their stabilisation with phase-locked loops". Thesis, Lancaster University, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.383542.
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Hsiao, Sen-Wen. "Built-in test for performance characterization and calibration of phase-locked loops". Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51790.
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The objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops is first investigated to achieve a robust performance over process, temperature, voltage corners with minimum overhead. Different design techniques including adding loop programmability, increasing area efficiency, reducing noise immunity, and increasing frequency coverage are discussed. Secondly, built-in testing of phase-lock loops using sensors are proposed for loop dynamic parameters and reference spur. An integrator is designed to extract the subtle response from the system so that target parameters can be predicted. Different testing methodologies are applied different specification testing as well. Finally, an on chip phase-locked loop design is implemented for reference spur calibration. The phase-locked loop is designed with a programmable reference spur range. A static phase offset detector is included to identify the optimal setting of reference spur in the feedback system. The integrated jitter performance is improved by the calibration mechanism. The results of this thesis serve as an on-chip built-in self-test and self-calibration solution for embedded phase-locked loops in a high integration system.
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Barat, Aakriti. "Analysis and Design of Phase Locked Loops with insight into Wavelet Analysis". The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1483676715726685.
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Leung, Chi Tak. "Design of 1-V CMOS RF phase-locked loops and frequency synthesizers /". View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20LEUNG.
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Hallal, Ayman. "Génération d'ondes millimétriques et submillimétriques sur des systèmes fibrés à porteuses optiques stabilisées". Thesis, Rennes 1, 2017. http://www.theses.fr/2017REN1S005/document.
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Je rapporte dans ce manuscrit une étude théorique et expérimentale d’une source compacte, fiable et bas coût d’ondes électromagnétiques continues et cohérentes de 30 Hz de largeur de raie, accordables de 1 GHz à 500 GHz par pas de 1 GHz. Ces ondes sont générées par un photo-mélange de deux diodes lasers DFB (Distributed Feedback) très accordables autour de 1550 nm, stabilisées avec des polarisations orthogonales sur une même cavité Fabry-Perot optique fibrée. J’ai conçue des électroniques de correction très rapides pour chaque laser permettant d’avoir une bande passante d’asservissement de 7 MHz limitée par la longueur de la boucle. Je démontre des suppressions de bruit de phase jusqu’à -60 dBc/ Hz à 1 kHz et de -90 dBc/Hz à 100 kHz d’écart d’une porteuse électrique à 92 GHz. Je mesure aussi une dérive de fréquence de ~170 kHz d’un battement à 10 GHz à long terme sur 7,5 heures de verrouillage continu. Je montre une conception optimisée d’une boucle d’asservissement intégrée de quelques dizaines de cm de longueur qui réduit le bruit de phase de 18 dB à 1 MHz d’écart à la porteuse optique et des couplages phase-amplitude réduits dans la cavité d’un facteur 50 par rapport à ceux estimés expérimentalement. L’ajout d’un troisième laser DFB stabilisé en phase sur un oscillateur local permettrait d’avoir une source continûment accordable sur 1 THz. La source d’ondes continues permettrait également de générer à partir de fibres hautement non linéaires et dispersives des impulsions pico- ou femtosecondes à un taux de répétition fixe en remplacement les lasers DFB par des lasers plus stables. Je calcule par simulation une gigue temporelle de 7,2 fs sur un temps d’intégration de 1 ms à 40 GHz de taux de répétitionI report in this manuscript a theoretical and experimental study of a compact, reliable and low cost source of 30 Hz linewidth, continuous and coherent electromagnetic waves tunable from 1 GHz to 500 GHz in steps of 1 GHz. These waves are generated by photomixing two distributed feedback (DFB) laser diodes at 1550 nm which are frequency stabilized with orthogonal polarizations on the same optical fibered Fabry-Perot cavity. I have designed very fast electronic control filters for each laser allowing a 7 MHz servo bandwidth limited by the loop length. I demonstrate phase noise suppressions down to -60 dBc/Hz at 1 kHz and -90 dBc/Hz at 100 kHz offset frequencies from a 92 GHz electrical carrier. I also measure a ~170 kHz frequency drift of the beat note at 10 GHz on the long term over a continuous 7.5 hour locking period. I show an optimized design of an integrated servo loop of few tens of cm length which reduces the phase noise by 18 dB at 1 MHz optical carrier offset frequency and the phase-amplitude couplings in the cavity by a factor of 50 compared to the experimental one. The addition of a third DFB laser phase stabilized on a local oscillator allows the possibility to have continuously tunable source over 1 THz. The continuous wave source also makes it possible to generate fixed repetition rate pico- or femtosecond pulses from highly non-linear and dispersive fibers, replacing the DFB lasers by further stable lasers. I have calculated by simulation 7.2 fs temporal jitter at 40 GHz repetition rate over a 1 ms integration time
32
Vong, Chun-yin. "Performance study of uniform sampling digital phase-locked loops for [Pi]/4-differentially encoded quaternary phase-shift keying /". Hong Kong : University of Hong Kong, 1998. http://sunzi.lib.hku.hk/hkuto/record.jsp?B20007164.
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Cheng, Shanfeng. "Design of CMOS integrated phase-locked loops for multi-gigabits serial data links". Texas A&M University, 2006. http://hdl.handle.net/1969.1/4954.
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High-speed serial data links are quickly gaining in popularity and replacing the
conventional parallel data links in recent years when the data rate of communication
exceeds one gigabits per second. Compared with parallel data links, serial data links are
able to achieve higher data rate and longer transfer distance. This dissertation is focused on
the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks
used in multi-gigabits serial data link transceivers.
Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are
modeled and analyzed. The steady-state behavior of BPLLs is derived with combined
discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs
are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC-
192, the mainstream standard for optical serial data links, is presented. The CDR is based
on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked
loop based on a quad-level phase detector and a linear frequency-locked loop based on a
linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in
0.18 üm CMOS technology and consumes 250 mW under 1.8 V supply. The jitter
generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance
exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential
divide-by-eight injection-locked frequency divider with low power dissipation is presented.
The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It
has a maximum operating frequency of 18 GHz. The ratio of locking range over center
frequency is up to 50%. The prototype chip is implemented in 0.18 üm CMOS technology
and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques
of fully differential charge pumps are discussed. Techniques are proposed to minimize the
nonidealities associated with a fully differential charge pump, including differential
mismatch, output current variation, low-speed glitches and high-speed glitches. The
performance improvement brought by the techniques is verified with simulations of
schematics designed in 0.35 üm CMOS technology.
34
Kam, Brandon Ray. "(VDL)² : a jitter measurement built-in self-test circuit for phase locked loops". Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/42119.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 77-79).
This paper discusses the development of a new type of BIST circuit, the (VDL)2, with the purpose of measuring jitter in IBM's phase locked loops. The (VDL)2, which stands for Variable Vernier Digital Delay Locked Line, implements both cycle-to-cycle and phase jitter measurements, by using a digital delay locked loop and a 60 stage Vernier delay line. This achieves a nominal jitter resolution of 10 ps with a capture range of +/- 150 ps and does so in real time. The proposed application for this circuit is during manufacturing test of the PLL. The circuit is implemented in IBM's 90 nm process and was completed in the PLL and Clocking Development ASIC group at IBM Microelectronics in Essex Junction, Vermont as part of the VI-A program.
by Brandon Ray Kam.
M.Eng.
35
Lei, Feiran. "Injection Locked Synchronous Oscillators (SOs) and Reference Injected Phase-Locke Loops (PLL-RIs)". The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492789278258943.
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36
Chau-Chiun, Huang, i 黃超群. "Performance Analysis of Homodyne Phase-Locked Loops in Coherent Optical Fiber Communication Systems". Thesis, 1994. http://ndltd.ncl.edu.tw/handle/16572851101593667623.
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碩士國立清華大學
電機工程研究所
82
In this thesis, we firstly report the importance of the optimum phase deviation between mark-state and space-state bits in a PSK homodyne system with a balanced phase-locked- loop (PLL) receiver. The signal power penalty incurred by improper use of phase deviations is evaluated. It is found that such power penalty can amount to larger than 1.5 dB in a 10 Gbits/sec system. In the second part of this thesis, we explore the waveform distortion induced by the effect of transient response delay (TRD) that is inherent in a PLL receiving system. Phase- locked loops of both balanced and Costas types are considered in this study. It is found that as a large number of identical bits are consecutively transmitted, substantial signal distortion can be induced by the effect of TRD for a balanced PLL system while the effect of TRD can be neglected for a Costas PLL system.
37
Chin-Chung, Chou, i 周晉崇. "Performance Analysis of Balanced Phase-Locked Loops in Long- Haul Optical Fiber Communication Systems : Design Considerations". Thesis, 1993. http://ndltd.ncl.edu.tw/handle/13860008342830761879.
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碩士國立清華大學
電機工程研究所
81
We analyze the performance of a balanced PSK homodyne receiver accounting for the impacts of laser phase noise,data-to- phaselock crosstalk, shot noise and the noise induced by cascaded optical amplifiers. Of most interest in this thesis is the effect of accumulated optical amplifier noise on the performance of a phase-locked-loop. Due to such effect, the loop natural frequency should be properly chosen in order to reach an optimum system performance. It is found that the optimum loop natural frequency may decrease substantially due to the effect of accumulated optical amplifier noise. Furthermore, the phase deviation between the transmitted symbols for the mark and the space states is found to play a significant role in determining the receiver performance. The optimum phase deviation, which leads to a minimum bit-error rate for a constant received signal power, shifts to a larger value as the number of optical amplifiers increases.
38
Sharma, Jahnavi. "CMOS Signal Synthesizers for Emerging RF-to-Optical Applications". Thesis, 2018. https://doi.org/10.7916/D85Q66Z4.
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The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers.
This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented.
The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off.
The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space.
We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam.
39
Chuang, Kung-chang, i 莊恭彰. "A design of Phase-Locked Loop for the application in optical transmitter". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/9z6t2n.
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碩士國立臺灣科技大學
電子工程系
94
This thesis describes a design of PLL clock generator for optical transmitter in a standard CMOS process. It can produce multiple-times clocks for a multiplexer which combines the parallel sequences of data at lower rates to generate a single high-speed serial signal. Our design methodology, simulation, and measurement can be summarized as follows. First, in order to analyze the PLL clock generator, we have established the loop parameters. The parameters effect on the PLL transient characteristic has been studied. Besides, noise sources were introduced into the PLL and its relationship with the loop parameters was explored. Second, a 1GHz PLL clock generator has been designed. The simulated jitter performance at 1GHz is equal to 4.081ps rms. The circuit only occupies an area of 0.784mm × 0.653mm. Furthermore, our PLL clock generator has three features. (i) A removal glitch circuit was presented to eliminate the coincident output pulse of the PFD. (ii) The ring oscillator consists of two delay cells and it enables a high-frequency operation. (iii) By modifying a traditional TSPC D-FF (True-Single-Phase-Clock D type flip-flop) with NAND gate, a fast and glitch-free TSPC D-FF with NAND gate was designed in the prescaler. Third, although a single-chip system of PLL clock generator has not been completed, we have implemented some of the component subsystems such as the charge pump with charge removal, the transmission-gate VCO, and the self-regulating VCO. The measured self-regulating VCO exhibits a tuning range between 204MHz and 652MHz. Furthermore, it has better frequency immunity to supply voltage variation for the supply range of VDD ±10%. In the range of the control voltage from 3V to 1.6V, its frequency deviation is within ±4.3%. Finally, a complementary type LC oscillator was implemented in order to improve a higher operating frequency. The measured LC oscillator has a tuning range of 2.04GHz to 2.51GHz. The phase noise at a 1MHz offset is approximated equal to -100dBc/Hz.
40
Chen, Yi-Ju. "An integrated CMOS optical receiver with clock and data recovery Circuit". Diss., 2005. http://hdl.handle.net/2263/24807.
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Traditional implementations of optical receivers are designed to operate with external photodetectors or require integration in a hybrid technology. By integrating a CMOS photodetector monolithically with an optical receiver, it can lead to the advantage of speed performance and cost. This dissertation describes the implementation of a photodetector in CMOS technology and the design of an optical receiver front-end and a clock and data recovery system. The CMOS detector converts the light input into an electrical signal, which is then amplified by the receiver front-end. The recovery system subsequently processes the amplified signal to extract the clock signal and retime the data. An inductive peaking methodology has been used extensively in the front-end. It allows the accomplishment of a necessary gain to compensate for an underperformed responsivity from the photodetector. The recovery circuits based on a nonlinear circuit technique were designed to detect the timing information contained in the data input. The clock and data recovery system consists of two units viz. a frequency-locked loop and a phase-locked loop. The frequency-locked loop adjusts the oscillator’s frequency to the vicinity of data rate before phase locking takes place. The phase-locked loop detects the relative locations between the data transition and the clock edge. It then synchronises the input data to the clock signal generated by the oscillator. A system level simulation was performed and it was found to function correctly and to comply with the gigabit fibre channel specification.Dissertation (MEng (Micro-Electronics))--University of Pretoria, 2007.
Electrical, Electronic and Computer Engineering
unrestricted
41
Iyer, S. P. Anand. "Phase Synthesis Using Coupled Phase-Locked Loops". 2008. https://scholarworks.umass.edu/theses/182.
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Phase Synthesis is a fundamental operation in Smart Antennas and other Phased Array systems based on beamforming. There are increasing commercial applications for Integrated Phased Arrays due to their low cost, size and power and also because the RF and digital signal processing can be performed on the same chip. These low cost beamforming applications have augmented interest in Coupled Phase Locked Loop (CPLL) systems for Phase Synthesis.
Previous work on the implementation of Phase Synthesis systems using Coupled PLLs for low cost beamforming had the constraint of a limited phase range of ±90°. The idea behind the thesis is that this phase synthesis range can be increased to ±180° through the use of PLLs employing Phase Frequency Detectors(PFDs), which is a significant improvement over conventional coupled-PLL systems.
This work presents the detailed design and measurement results for a phase synthesizer using Coupled PLLs for achieving phase shift in the range of ±180°. Several Coupled PLL architectures are investigated and their advantages and limitations are evaluated in terms of frequency controllability, phase difference synthesis control and phase noise of the systems. A two-PLL system implementation using off the shelf components is presented, which generates a steady-state phase difference in the range ±180° using an adjustable DC control current. This is the proof of concept for doing an IC design for a Coupled Phase Locked Loop system. Commercial applications in the Wireless Medical Telemetry Service (WMTS) band motivate the design of a CPLL system in the 608-614 MHz band. The design methodology is presented which shows the flowchart of the IC design process from the system design specifications to the transistor level design. MATLAB simulations are presented to model the system performance quickly. VerilogA modeling of the CPLL system is performed followed by the IC design of the system and each block is simulated under different process and temperature corners. The transistor level design is then evaluated for its performance in terms of phase difference synthesis and phase noise and compared with the initial MATLAB analysis and improved iteratively. The CPLL system is implemented in IBM 130nm CMOS process and consumes 40mW of power from a 1.2V supply with a phase noise performance of -88 dBc/Hz for 177° phase generation.
42
Yogesh, Prasad K. R. "Generation of Modulated Microwave Signals using Optical Techniques for Onboard Spacecraft Applications". Thesis, 2013. http://etd.iisc.ernet.in/handle/2005/2849.
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This thesis deals with optical synthesis of unmodulated and modulated microwave signals. Generation of microwave signals based on optical heterodyning is discussed in detail.
The effect of phase noise of laser on heterodyned output has been studied for different phase noise profiles. Towards this, we propose a generic algorithm to numerically model the linewidth broadening of a laser due to phase noise. Generation of microwave signals is demonstrated practically by conducting an optical heterodyning experiment. Signals ranging in frequency from 12.5 MHz to 27 GHz have been generated.
Limitations of optical heterodyning based approach in terms of phase noise performance and frequency stability are discussed and practically demonstrated. A hardware-efficient Optical Phase Locked Loop (OPLL) is proposed to overcome these issues. Phase noise tracking performance of the proposed OPLL has been experimentally demonstrated. Phase noise values as low as -105 dBc/Hz at 10 KHz offset have been achieved.
Optical modulators, owing to their extremely low electro-optic response time, can support high frequency modulating signals. This makes them highly attractive in comparison to their microwave counterparts. In this thesis, we propose techniques to generate microwave signals modulated at very high bit rates by down-converting the corresponding modulated optical signals to microwave domain. Down-conversion required for this process is achieved by optical heterodyning. The proposed concept has been theoretically analyzed, simulated and experimentally validated. Amplitude Modulated and ASK modulated microwave signals have been generated as Proof-of-Concept.
Limitations posed by OPLL in generation of angle modulated microwave signals by optical heterodyning have been brought out. Schemes overcoming these limitations have been proposed towards generation of BPSK and QPSK modulated microwave signals.
Integrated Optics (IO) technology has been studied as a means of implementation of the proposed concepts. IO components like Sinusoidal bends, Y-branch splitters and Electro-Optic-Modulators (EOMs) have been designed towards optical synthesis of modulated microwave signals. Propagation of modulated optical signal through these IO components has also been studied.
An all-optic scheme based on Optical Beam Forming is proposed for transmission of QPSK modulated signal. Limitation of phase-shifting based approach, in terms of beam-squint, has been brought out. True-Time-Delay based approach has been proposed for applications demanding wide instantaneous bandwidth to avoid beam-squint.
Algorithms / numerical methods required for analyses and simulations associated with the above-mentioned tasks have been evolved.
This study is envisaged to provide useful insight into the realization of high-speed, compact, light-weight data transmitting systems based on Integrated Optics for future onboard spacecraft applications. This work, we believe, is a step towards realization of an Integrated Optic System-on-Chip solution for specific microwave data transmission applications.
43
Chen, Yen-Wen. "Low Power Techniques for Phase-Locked Loops". 2004. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2807200400113100.
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44
Chen, Yen-Wen, i 陳彥文. "Low Power Techniques for Phase-Locked Loops". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/72y8ds.
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碩士國立臺灣大學
電子工程學研究所
92
The goal of this work is to use a standard 0.35-μm CMOS process to implement the phase-locked loops with low power consumption, and the new methods of these three topics, reducing the power consumption of the VCO and divider, reducing the switching power of the output buffer and a dividerless PLL, are presented. The presented PLL include PFD, charge pump circuit, VCO, and divider, successfully reduces the power consumption on VCO and divider by regulated supply technique and novel schematic. To reduce the dynamic switching power consumption, we propose a new charge recycling buffer. The output transistors of the buffer will enter tri-state period first every time and do charge recycling in this period then the output starts transition. A dividerless PLL can be implemented by Aperture Phase Detection (APD) technique because this method only compares reference and VCO phase ones every reference period. A proposed new APD cell can also reduce the jitter caused by the charge pump mismatch current.
45
Lin, Jian-Da, i 林建達. "Delay-Locked Loops with phase error calibration". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/11571946077067957002.
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碩士長庚大學
電機工程學系
100
Because of the development of technology, smaller scale of MOSFET, channel effect, low supply voltage, and process-voltage-temperature variations, circuit design has become more and more difficult. The synchronous problem between circuits is undoubtedly important in system integration. Delay-locked loop is designed and implemented to solve the problem of clock synchronization and tracking. Delay-locked loop is widely used because of easy design, stability, and low power consumption. This thesis presents a new method to improve DLL’s phase error. Due to the current mismatch of Charge Pump, the input and output have phase error. We use the D flip-flop’s setup time to reduce current mismatch of Charge Pump in DLL. This chip is implemented in a 0.18μm CMOS process with 1.8V power supply voltage. The total area of the chip is 1*1mm2. The operating frequency range is from 700MHz to 900MHz. The power consumption is 46mW. The phase error is 3.3ps and peak-to-peak jitter is 14ps at 900MHz.
46
Chien-Cheng, Huang, i 黃建成. "Identifying Resonant Structure with Phase Locked Loops". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/05691156216365104340.
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碩士國立交通大學
機械工程系所
96
This study presents a simple method to evaluate the natural frequency and the damping ratio of a second order system considering resonant excitation. Structural imperfection and the viscous damping can dramatically reduce the performance of micro-electromechanical systems (MEMS) in gyro or accelerometer applications. Using the phase locked loops (PLL) as the electrical driving circuit of the MEMS devices, the tracking frequency can be used to calculate the natural frequency and the damping ratio. The proposed method is implemented using a simple circuit.
47
陳添欑. "The Transient Response of Phase-Locked Loops". Thesis, 1986. http://ndltd.ncl.edu.tw/handle/64071139970715905349.
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碩士國立臺灣大學
電機工程研究所
74
This thesis discusses the frequency step response and the phase step response of first-order and second-order phase-locked loops under no noise condition. With these studies, we may understand (1)If the PLL is initially locked, under what conditions will the PLL remain locked? (2)How to choose the PLL parameters to minimize the transient time? First, we introduce the basic principles and basic functional blocks of PLL. Second, we make a linear mode analysis of the various configurations of PLL, then to solve their formulas of the frequency step response and the phase step response, and to find their lock ranges respectively. Finally, we present a realized circuit of PLL and compare the results of this circuit with the formulas above.
48
Huang, Chih Wei, i 黃智威. "Delay-Locked Loops with phase error calibration". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/02572634294723259429.
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TANG, KAI-YUAN, i 湯凱元. "Investignations of novel optoelectronic phase-locked loops". Thesis, 1992. http://ndltd.ncl.edu.tw/handle/21907334695831579767.
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Chen, Peng-Sheng, i 陳鵬升. "Phase-Locked Loops and Temperature Compensated Oscillator". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/93743040042100356425.
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碩士國立臺灣大學
電子工程學研究所
100
Phase-Locked Loops (PLLs) are one of the key building blocks in mixed-signal integrated circuits, and are essential in various fields including communications, controls, instrumentations and sensors. For this reason, we design and analyze various features of the PLL in this thesis. This thesis consists of four parts. The first part realizes a fast-locking and low spur PLL. Using high-gain phase detector, we enhance the locking time and improve the spur problem. The measured locking time is reduced from 103.89us to 3.89us with the proposed FD. The measured reference spur is improved by 39dB with the proposed spur suppression technique. The second part implements a 0.4V 400MHz PLL. We propose several novel circuits for PLL to operate in the sub-threshold region. The core area is only 0.0143 mm2 with an on-chip second-order loop filter. The power consumption is 9.2uW. The third part aims to design a low temperature coefficient digitally-controlled ring oscillator. Positive and negative temperature coefficient delay cell is employed and analyzed. Besides, we propose a transconductance compensated technique to achieve higher compensation resolution. The proposed DCRO temperature coefficient is achieved 10.26 ppm/℃ over 120℃ temperature range. The fourth part proposes a 0.5V 900MHz PLL with adaptive supply technique. The adaptive supply not only resists the process, voltage, and temperature variations, but also achieves lower power consumption. The simulated power consumption is 42.15uW and the core area is 0.0228 mm2.