Gotowe bibliografie tematyczne / Multiple-Input Floating Gate MOS

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Gotowa bibliografia na temat „Multiple-Input Floating Gate MOS”

Autor: Grafiati

Data publikacji: 6 września 2023

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Artykuły w czasopismach na temat "Multiple-Input Floating Gate MOS"

Rodríguez-Villegas, Esther O., Alberto Yúfera i Adoración Rueda. "A Low-Voltage Floating-Gate MOS Biquad". VLSI Design 12, nr 3 (1.01.2001): 407–14. http://dx.doi.org/10.1155/2001/16935.

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A second-order gm-C filter based on the Floating-Gate MOS (FGMOS) technique is presented. It uses a new fully differential transconductor and works at 2 V of voltage supply with a full differential input linear range and a THD below 1%. Programming and tuning are performed by means of a single voltage signal. The transconductor incorporates a novel Common-Mode Feedback Circuit (CMFB) based also on FGMOS transistors.

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Gupta, Maneesha, Richa Srivastava i Urvashi Singh. "Low Voltage Floating Gate MOS Transistor Based Differential Voltage Squarer". ISRN Electronics 2014 (9.02.2014): 1–6. http://dx.doi.org/10.1155/2014/357184.

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This paper presents novel floating gate MOSFET (FGMOS) based differential voltage squarer using FGMOS characteristics in saturation region. The proposed squarer is constructed by a simple FGMOS based squarer and linear differential voltage attenuator. The squarer part of the proposed circuit uses one of the inputs of two-input FGMOS transistor for threshold voltage cancellation so as to implement a perfect squarer function, and the differential voltage attenuator part acts as input stage so as to generate the differential signals. The proposed circuit provides a current output proportional to the square of the difference of two input voltages. The second order effect caused by parasitic capacitance and mobility degradation is discussed. The circuit has advantages such as low supply voltage, low power consumption, and low transistor count. Performance of the circuit is verified at ±0.75 V in TSMC 0.18 μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator.

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Mehrvarz, H. R., i Chee Yee Kwok. "A novel multi-input floating-gate MOS four-quadrant analog multiplier". IEEE Journal of Solid-State Circuits 31, nr 8 (1996): 1123–31. http://dx.doi.org/10.1109/4.508259.

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Khateb, Fabian, Tomasz Kulej, Harikrishna Veldandi i Winai Jaikla. "Multiple-input bulk-driven quasi-floating-gate MOS transistor for low-voltage low-power integrated circuits". AEU - International Journal of Electronics and Communications 100 (luty 2019): 32–38. http://dx.doi.org/10.1016/j.aeue.2018.12.023.

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Srivastava, Richa, Maneesha Gupta i Urvashi Singh. "Fully Programmable Gaussian Function Generator Using Floating Gate MOS Transistor". ISRN Electronics 2012 (20.11.2012): 1–5. http://dx.doi.org/10.5402/2012/148492.

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Floating gate MOS (FGMOS) based fully programmable Gaussian function generator is presented. The circuit combines the tunable property of FGMOS transistor, exponential characteristics of MOS transistor in weak inversion, and its square law characteristic in strong inversion region to implement the function. Two-quadrant current mode squarer is the core subcircuit of Gaussian function generator that helps to implement full Gaussian function for positive as well as negative input current. FGMOS implementation of the circuit reduces the current mismatching error and increases the tunability of the circuit. The performance of circuit is verified at 1.8 V in TSMC 0.18 μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator.

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Khateb, Fabian, Tomasz Kulej, Montree Kumngern i Vilém Kledrowetz. "Low-Voltage Diode-Less Rectifier Based on Fully Differential Difference Transconductance Amplifier". Journal of Circuits, Systems and Computers 26, nr 11 (17.03.2017): 1750172. http://dx.doi.org/10.1142/s0218126617501729.

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This paper presents a voltage-mode low-voltage low-power diode-less rectifier with only one active element, the fully differential difference transconductance amplifier (FDDTA). The multiple-input floating-gate MOS (FG-MOS) transistor is used to build the differential pairs of the FDDTA resulting in the reduced count of transistors, circuit simplicity and the capability to work under low-voltage supply with extended input voltage range. The rectifier was designed with 0.9[Formula: see text]V voltage supply and 8[Formula: see text][Formula: see text]W power consumption, hence it is suitable for wearable electronics and biomedical applications. The simulation results obtained from the Cadence platform using 0.18[Formula: see text][Formula: see text]m TSMC CMOS technology show good performances for the designed circuit.

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Sharroush, Sherif, i Sherif Nafea. "A Novel Domino Logic Based on Floating-Gate MOS Transistors". Jordan Journal of Electrical Engineering 9, nr 3 (2023): 410. http://dx.doi.org/10.5455/jjee.204-1672498383.

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Domino logic finds a wide variety of applications in both static and dynamic random-access memories and in high-speed microprocessors. However, the main limitation of the domino logic-circuit family is the trade-off between the noise immunity and speed. In order to resolve such a trade-off, this paper proposes a domino logic that is based on floating-gate MOS (FGMOS) transistors. Compact-form expressions are derived for the noise margins for the low and high inputs as well as the propagation delays. The proposed scheme is verified by simulation adopting the 45 nm CMOS predictive technology model (PTM) with a power-supply voltage of 1 V. The obtained results unveil that the proposed domino logic outperforms the conventional domino logic in terms of the power-delay product and the energy-delay product when realizing wide fan-in OR gates. The realized, with the proposed scheme, 16-input OR gate has an average power consumption of 3.7 µW and a propagation delay of 51 ps.

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Plascencia Jauregui, Francisco Javier, Agustín Santiago Medina Vazquez, Edwin Christian Becerra Alvarez, José Manuel Arce Zavala i Sandra Fabiola Flores Ruiz. "On the methodology of calculating volume charge density in a MIFGMOS substrate using Poisson’s equation". Microelectronics International 38, nr 4 (14.10.2021): 206–15. http://dx.doi.org/10.1108/mi-01-2021-0004.

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Purpose This study aims to present a mathematical method based on Poisson’s equation to calculate the voltage and volume charge density formed in the substrate under the floating gate area of a multiple-input floating-gate metal-oxide semiconductor metal-oxide semiconductor (MOS) transistor. Design/methodology/approach Based on this method, the authors calculate electric fields and electric potentials from the charges generated when voltages are applied to the control gates (CG). This technique allows us to consider cases when the floating gate has any trapped charge generated during the manufacturing process. Moreover, the authors introduce a mathematical function to describe the potential behavior through the substrate. From the resultant electric field, the authors compute the volume charge density at different depths. Findings The authors generate some three-dimensional graphics to show the volume charge density behavior, which allows us to predict regions in which the volume charge density tends to increase. This will be determined by the voltages on terminals, which reveal the relationship between CG and volume charge density and will allow us to analyze some superior-order phenomena. Originality/value The procedure presented here and based on coordinates has not been reported before, and it is an aid to generate a model of the device and to build simulation tools in an analog design environment.

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Luck, A., S. Jung, R. Brederlow, R. Thewes, K. Goser i W. Weber. "On the design robustness of threshold logic gates using multi-input floating gate MOS transistors". IEEE Transactions on Electron Devices 47, nr 6 (czerwiec 2000): 1231–40. http://dx.doi.org/10.1109/16.842967.

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Rajesh, Durgam, Subramanian Tamil, Nikhil Raj i Bharti Chourasia. "Low-voltage bulk-driven flipped voltage follower-based transconductance amplifier". Bulletin of Electrical Engineering and Informatics 11, nr 2 (1.04.2022): 765–71. http://dx.doi.org/10.11591/eei.v11i2.3306.

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A low voltage high performance design of operational transconductance amplifier is proposed in this paper. The proposed architecture is based on bulk driven quasi-floating gate metal oxide semiconductor field effect transistor (MOSFET) which supports low voltage operation and improves the gain of the amplifier. Besides to this the tail current source requirement of operational transconductance amplifier (OTA) is removed by using the flipped voltage follower structure at the input pair along with bulk driven quasi-floating gate MOSFET. The proposed operational transconductance amplifier shows a five-fold increase in direct current (DC) gain and 3-fold increase in unity gain bandwidth when compared with its conventional bulk driven architecture. The metal oxide semiconductor (MOS) model used for amplifier design is of 0.18 um complementary metal oxide semiconductor (CMOS) technology at supply of 0.5 V.

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Rozprawy doktorskie na temat "Multiple-Input Floating Gate MOS"

Tripathi, Ankit. "Low Power Analog Neural Network Framework with MIFGMOS". Thesis, 2020. https://etd.iisc.ac.in/handle/2005/4829.

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Ever since the beginning of the notion behind the term 'cloud computing,' i.e., to share the pro- cessing and storage capabilities of a centralized system, there has been a signi cant increase in the availability of raw data. The challenges faced (e.g., high latency, storage limitations, channel band- width limitations, downtime) while processing such data in a cloud framework gave birth to edge computing where the idea is to push the computation to the edge of the network. Edge computing is a distributed computing paradigm, which off loads cloud because of performing data processing near to the source. For real-time applications (e.g., autonomous vehicles, air tra c control systems) where the latency is of prime concern, the deployment of Deep Neural Networks (DNNs) on the cloud would not be a feasible option. This is because of substantial inference time, enormous memory requirements, and numerous CPUs & GPUs, which translates to large power consumption. This difficulty in latency can be overcome by deploying DNN models on edge devices. Edge devices typically cannot handle a large DNN because of power and memory constraints. This lack of power and size restricts the need for small yet efficient implementation of DNN on edge devices. Promising results have been shown by employing the Extreme Learning Machine (ELM) in terms of faster training and high accuracy for Multilayer Perceptron (MLP) in applications such as object detection, recognition, and tracking. MLP being an instance of DNN could be a viable option to be deployed on edge devices. This motivates the need for analog implementation of MLP because of its characterizing fea- tures of low power and small size overcome the issues discussed above. In this work, a novel way of realizing the ELM framework on a single hidden layer feed-forward neural network (SLFN) is presented based on a Multiple-Input Floating Gate MOS (MIFGMOS) operational transconduc- tance amplifier (OTA). A multiple-input version of FGMOS called MIFGMOS is a device which because of its lossless charge sharing based voltage summation operation, dissipates meager power. The ability of a programmable threshold voltage and weighted summation of input gate voltage makes MIFGMOS an ideal device for emulation of biological neurons while working in the sub- threshold region for low power operation. Also, being able to serve as an analog memory in the form of statically stored charges renders the use of an input layer synaptic weights arrangement inessential. From the perspective of an analog neural network framework, the use of MIFGMOS improves areal density substantially. The transconductance curve of the employed OTA resembles a highly non-linear activation function (Sigmoid in this case). The slope and maximum level of the transconductance curve which are the tunable parameters of our setup serve as variability among activations. The proposed system has been implemented using 65nm Complementary Metal Oxide Semi- conductor (CMOS) process technology. The working principle of the implemented system has been veri ed by employing it for regression and classi cation tasks such as MNIST digit recognition.

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Części książek na temat "Multiple-Input Floating Gate MOS"

Yang, Kewei, i Andreas G. Andreou. "A Multiple Input Differential Amplifier Based on Charge Sharing on a Floating-Gate MOSFET". W Analog Signal Processing, 21–32. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4757-4503-0_2.

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Streszczenia konferencji na temat "Multiple-Input Floating Gate MOS"

Plascencia Jauregui, Francisco, Santiago Medina Vazquez, Edwin Becerra Alvarez, Jose Arce Zavala i Sandra Flores Ruiz. "A Method to Model the Volume Charge Density in a Multiple-Input Floating-Gate MOS Transistor". W 2020 17th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE). IEEE, 2020. http://dx.doi.org/10.1109/cce50788.2020.9299156.

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Tripathi, Ankit, Mehdi Arabizadeh, Sourabh Khandelwal i Chetan Singh Thakur. "Analog Neuromorphic System Based on Multi Input Floating Gate MOS Neuron Model". W 2019 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2019. http://dx.doi.org/10.1109/iscas.2019.8702492.

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Keles, Fatih, i Tulay Yildirim. "Pattern recognition using N-input neuron circuits based on floating gate MOS transistors". W IEEE EUROCON 2009 (EUROCON). IEEE, 2009. http://dx.doi.org/10.1109/eurcon.2009.5167634.

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Mankar, Monica V., i Shweta P. Hajare. "Multiple-Input Multiple-Valued Pseudo-floating Gate DAC". W 2010 International Conference on Advances in Recent Technologies in Communication and Computing (ARTCom). IEEE, 2010. http://dx.doi.org/10.1109/artcom.2010.100.

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Davila-Saldivar, C., A. S. Medina-Vazquez, A. Jimenez-Perez i M. A. Gurrola-Navarro. "Extracting the floating gate voltage on the multiple-input FGMOS transistor". W 2014 11th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE). IEEE, 2014. http://dx.doi.org/10.1109/iceee.2014.6978250.

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Kumngern, Montree, i Fabian Khateb. "A low-voltage and low-power multiple-input floating-gate FDCCII". W 2015 12th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON). IEEE, 2015. http://dx.doi.org/10.1109/ecticon.2015.7206943.

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Hang, Guoqiang, Xuanchang Zhou i Xiaohui Hu. "Design of Dynamic Digital Circuits with n-Channel Multiple-Input Floating-Gate Transistors". W 2014 IEEE 12th International Conference on Dependable, Autonomic and Secure Computing (DASC). IEEE, 2014. http://dx.doi.org/10.1109/dasc.2014.86.

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Arce-Zavala, J. M., A. S. Medina-Vazquez i M. A. Gurrola-Navarro. "Design and validation of a mixed-signal correlator using a multiple-input floating gate transistor". W 2015 12th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE). IEEE, 2015. http://dx.doi.org/10.1109/iceee.2015.7357913.

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Quah, A. C. T., D. Nagalingam, G. B. Ang, C. Q. Chen, H. H. Ma, E. Susanto, S. Moon, S. P. Neo, J. C. Lam i Z. H. Mai. "Enhanced Static Fault Localization Methodology on Resistive Open Defects Using Photon Emission Microscopy and Layout Defect Prediction". W ISTFA 2016. ASM International, 2016. http://dx.doi.org/10.31399/asm.cp.istfa2016p0520.

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Abstract In this paper, the effects of an open defect resulting in floating gate on combinational logic gate structures are studied. From this study, a novel method is derived to predict and narrow down the potential open defect location from a long failure path that is driving multiple branches of input nodes, into a much smaller segment without EBAC analysis. This method is applied with great success to localize open defects on actual low yield cases from advanced technology nodes with significant reduction in FA cycle time.

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