Gotowe bibliografie tematyczne / Multigate transistor

Gotowa bibliografia na temat „Multigate transistor”

Autor: Grafiati

Data publikacji: 25 maja 2024

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Artykuły w czasopismach na temat "Multigate transistor"

Lee, Chi-Woo, Aryan Afzalian, Nima Dehdashti Akhavan, Ran Yan, Isabelle Ferain i Jean-Pierre Colinge. "Junctionless multigate field-effect transistor". Applied Physics Letters 94, nr 5 (2.02.2009): 053511. http://dx.doi.org/10.1063/1.3079411.

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Martins, Rodrigo, Diana Gaspar, Manuel J. Mendes, Luis Pereira, Jorge Martins, Pydi Bahubalindruni, Pedro Barquinha i Elvira Fortunato. "Papertronics: Multigate paper transistor for multifunction applications". Applied Materials Today 12 (wrzesień 2018): 402–14. http://dx.doi.org/10.1016/j.apmt.2018.07.002.

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Jayachandran, Remya, Dhanaraj Jagalchandran i Perinkolam Chidambaram Subramaniam. "Planar CMOS and multigate transistors based wide-band OTA buffer amplifiers for heavy resistance load". Facta universitatis - series: Electronics and Energetics 35, nr 1 (2022): 13–28. http://dx.doi.org/10.2298/fuee2201013j.

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Analog buffer amplifier configurations capable of driving heavy resistive load using different operational transconductance amplifier (OTA) are presented in this paper. The OTA CMOS buffer configurations are designed using 0.18 ?m SCL technology library in Cadence Virtuoso tool and multigate transistor OTA buffer in TCAD Sentaurus tool. CMOS OTA buffer configuration using simple OTA outperform the OTA buffer circuits using other OTAs in terms of power dissipation and stability. Measured results show that the OTA buffer circuit works well for resistive load below 100 ?. The gain tuning of up to 5 V/V is achieved with RL equal to 50 ?, output swing of 1 V. OTA buffer configuration implemented using multigate transistor with resistive load below 1 k? exhibits a bandwidth around 5 GHz and tunable gain up to 5 V/V.

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Selvi, K. Kalai, K. S. Dhanalakshmi i Kalaivani Kanagarajan. "Performance Estimation of Recessed Modified Junctionless Multigate Transistor". Journal of Nano- and Electronic Physics 14, nr 1 (2022): 01008–1. http://dx.doi.org/10.21272/jnep.14(1).01008.

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Kohda, S., K. Masuda, K. Matsuzawa i Y. Kitano. "A giant chip multigate transistor ROM circuit design". IEEE Journal of Solid-State Circuits 21, nr 5 (październik 1986): 713–19. http://dx.doi.org/10.1109/jssc.1986.1052599.

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Delgado-Notario, Juan A., Wojciech Knap, Vito Clericò, Juan Salvador-Sánchez, Jaime Calvo-Gallego, Takashi Taniguchi, Kenji Watanabe i in. "Enhanced terahertz detection of multigate graphene nanostructures". Nanophotonics 11, nr 3 (3.01.2022): 519–29. http://dx.doi.org/10.1515/nanoph-2021-0573.

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Abstract Terahertz (THz) waves have revealed a great potential for use in various fields and for a wide range of challenging applications. High-performance detectors are, however, vital for exploitation of THz technology. Graphene plasmonic THz detectors have proven to be promising optoelectronic devices, but improving their performance is still necessary. In this work, an asymmetric-dual-grating-gate graphene-terahertz-field-effect-transistor with a graphite back-gate was fabricated and characterized under illumination of 0.3 THz radiation in the temperature range from 4.5 K up to the room temperature. The device was fabricated as a sub-THz detector using a heterostructure of h-BN/Graphene/h-BN/Graphite to make a transistor with a double asymmetric-grating-top-gate and a continuous graphite back-gate. By biasing the metallic top-gates and the graphite back-gate, abrupt n+n (or p+p) or np (or pn) junctions with different potential barriers are formed along the graphene layer leading to enhancement of the THz rectified signal by about an order of magnitude. The plasmonic rectification for graphene containing np junctions is interpreted as due to the plasmonic electron-hole ratchet mechanism, whereas, for graphene with n+n junctions, rectification is attributed to the differential plasmonic drag effect. This work shows a new way of responsivity enhancement and paves the way towards new record performances of graphene THz nano-photodetectors.

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Ono, Y., H. Inokawa i Y. Takahashi. "Binary adders of multigate single-electron transistors: specific design using pass-transistor logic". IEEE Transactions on Nanotechnology 1, nr 2 (czerwiec 2002): 93–99. http://dx.doi.org/10.1109/tnano.2002.804743.

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Wahid, Syamsudin Nur. "SIMULASI KUANTUM TRANSISTOR EFEK MEDAN MULTI GERBANG (NWFET)". Jurnal Qua Teknika 7, nr 1 (15.03.2017): 53–64. http://dx.doi.org/10.35457/quateknika.v7i1.218.

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Makalah ini membahas metode numerik untuk simulasi kuantum satu dan dua dimensi dari nanowire multigate transistor efek medan. Perangkat dimodelkan berdasarkan teori massa efektif dan formalisme fungsi Green non-ekuilibrium. Simulasi terdiri dari solusi Poisson persamaan tiga dimensi, persamaan Schrodinger dua dimensi pada penampang lintang dan persamaan transport satu dimensi. Dijelaskan detail teknik numerik untuk setiap langkah-langkah simulasi.

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Wahid, Syamsudin Nur. "SIMULASI KUANTUM TRANSISTOR EFEK MEDAN MULTI GERBANG (NWFET)". JURNAL QUA TEKNIKA 7, nr 1 (15.03.2017): 53–64. http://dx.doi.org/10.30957/quateknika.v7i1.218.

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Cheng, Hui-Wen, i Yiming Li. "Comparative Study of Multigate and Multifin Metal–Oxide–Semiconductor Field-Effect Transistor". Japanese Journal of Applied Physics 49, nr 4 (20.04.2010): 04DC09. http://dx.doi.org/10.1143/jjap.49.04dc09.

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Rozprawy doktorskie na temat "Multigate transistor"

Gay, Roméric. "Développement de composants analogiques embarqués dans des microcontrôleurs destinés à l'Internet des Objets (loT)". Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0218.

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L’objectif de ces travaux de thèse a été d'améliorer les performances, le coût et la surface de silicium occupés par un microcontrôleur fabriqué sur la base d’une technologie mémoire embarquée CMOS (eNVM) 40 nm. Ces améliorations ont été réalisées grâce au développement de nouvelles architectures de transistors adaptées au besoin du marché de l’IoT. Dans une première partie, le contexte dans lequel s’inscrit cette thèse est exposé par la présentation des limites technologiques et économiques de technologie CMOS. Dans une deuxième partie, le procédé de fabrication eNVM ainsi que l’architecture et le mode de fonctionnement d’un nouveau composant, appelé transistor triple grille, ont été présentés. Sur la base de cette nouvelle architecture, composée de grilles de contrôle indépendantes, différents transistors multigrilles ont été fabriqués. Par la même occasion, leur comportement électrique a été analysé. Dans la continuité, des études de fiabilité, portant notamment sur les oxydes de grilles, ont été menées. L’objectif de ces études a été d’étudier l’impact d’une contrainte électrique, appliquée sur une grille du transistor, sur les autres grilles non soumises à cette même contrainte. Des caractérisations électriques ainsi que des simulations TCAD, ont permis d’améliorer la compréhension des résultats obtenus. Finalement, la structure du transistor triple grille a été modélisée à l’aide d’un modèle compact de transistor de type PSP. Cette modélisation a pour objectif de permettre l’évaluation du comportement et des performances électriques de ce transistor au niveau circuit
The aim of this work is to improve the performance, cost and area of a microcontroller manufactured in a 40 nm CMOS embedded memory technology (eNVM), by developing new transistor architectures suitable for the IoT market. The context is first presented with a focus on the technological and economical limitations of the CMOS technology. In a second part, the eNVM manufacturing process as well as the architecture and operation mode of a new component called triple gate transistor are presented. Based on this new architecture which provides independent control gates, various multigate transistors are manufactured and their electrical behaviour is analysed. Reliability studies are then carried out, to assess the reliability of the gate’s oxides. The objective is to study the impact of an electrical stress applied to one transistor gate on the gates not subject to this same stress. Electrical characterizations and TCAD simulations are also conducted to improve the understanding. Finally, the structure of the triple gate transistor is modelled using a compact PSP transistor model. The aim is to evaluate the behaviour but also the electrical performance of this transistor at the circuit level

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Chevillon, Nicolas. "Etude et modélisation compacte du transistor FinFET ultime". Phd thesis, Université de Strasbourg, 2012. http://tel.archives-ouvertes.fr/tel-00750928.

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Une des principales solutions technologiques liées à la réduction d'échelle de la technologie CMOS est aujourd'hui clairement orientée vers les transistors MOSFET faiblement dopés à multiples grilles. Ceux-ci proposent une meilleure immunité contre les effets canaux courts comparés aux transistors MOSFET bulk planaires (cf. ITRS 2011). Parmi les MOSFETs à multiples grilles, le transistor FinFET SOI est un candidat intéressant de par la similarité de son processus de fabrication avec la technologie des transistors planaires. En parallèle, il existe une réelle attente de la part des concepteurs et des fonderies à disposer de modèles compacts efficaces numériquement, précis et proches de la physique, insérés dans les " design tools " permettant alors d'étudier et d'élaborer des circuits ambitieux en technologie FinFET. Cette thèse porte sur l'élaboration d'un modèle compact orienté conception du transistor FinFET valide aux dimensions nanométriques. Ce modèle prend en compte les effets canaux courts, la modulation de longueur de canal, la dégradation de la mobilité, leseffets de mécanique quantique et les transcapacités. Une validation de ce modèle est réalisée par des comparaisons avec des simulations TCAD 3D. Le modèle compact est implémenté en langage Verilog-A afin de simuler des circuits innovants à base de transistors FinFET. Une modélisation niveau-porte est développée pour la simulation de circuits numériques complexes. Cette thèse présente également un modèle compact générique de transistors MOSFET SOI canaux long faiblement dopés à multiple grilles. La dépendance à la température est prise en compte. Selon un concept de transformation géométrique, notre modèle compact du transistor MOSFET double grille planaire est étendu pour s'appliquer à tout autre type de transistor MOSFET à multiple grille (MuGFET). Une validation expérimentale du modèle MuGFET sur un transistor triple grille est proposée. Cette thèse apporte enfin des solutions pour la modélisation des transistors MOSFET double grille sans jonction.

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Lu, Wenjie. "Antimonide-based III-V multigate transistors". Thesis, Massachusetts Institute of Technology, 2018. http://hdl.handle.net/1721.1/117833.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged student-submitted from PDF version of thesis.
Includes bibliographical references (pages 159-171).
As Si CMOS technology advances, alternative channel materials are under extensive investigation to replace or augment Si in future generations of nanoelectronics. III-V compound semiconductors, such as InGaAs and InGaSb are promising candidates as channel materials for MOSFETs as a result of their extraordinary transport properties. In the past few years, rapid growth in the research of InGaAs n-channel multi-gate MOSFETs has taken place. However, progress in the InGaSb p-channel device research has remained stagnant. In this thesis, InGaSb multi-gate transistor technology has been pioneered and the first InGaSb FinFET has been demonstrated. Critical technological challenges for realizing InGaSb FinFETs have been overcome. First, a dry etching technique of heterostructures containing antimonide-based compounds has been developed. Etched fins and vertical nanowires show smooth, vertical sidewalls, high aspect ratio, and compatibility with the InGaAs system.
Second, a novel antimonide-compatible digital etch technique has been developed which can improve fin sidewall quality and device performance. Lastly, ohmic contacts have been investigated to reduce the parasitic source-drain resistance. The developed contact system delivers a record low contact resistivity. With the integration of the newly developed technologies, InGaSb p-channel FinFETs are demonstrated for the first time. Three generations of InGaSb FinFETs are fabricated following an optimization path for device design and process technology. The most aggressively scaled InGaSb FinFETs, with a minimum fin width of 10 nm and channel height of 23 nm, have achieved a maximum transconductance per device footprint of 704 μS/μm, a record value for any existing antimonide-based p-channel FETs.
In addition, the fabricated FinFETs have been electrically characterized, and device properties such as scaling behavior, impact of channel strain, and OFF-state leakage current have been studied. The work in this thesis has pushed significantly the state-of-the-art of antimonide-based electronic device technology.
by Wenjie Lu.
Ph. D.

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Chang, Kai-Hsiang, i 張凱翔. "The study of multigate Poly-Si Thin-Film Transistors". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/30168709489216678656.

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碩士
逢甲大學
電子工程所
99
Polycrystalline silicon thin-film transistors (Poly-Si) are used widely in various field, such as active-matrix liquid crystal displays (AMLCDs), solar cell, active matrix organic light emitting diode (AMOLED) and flash memories because of their high mobility and driving current. In recent year, the device is promising candidate to be used in display system-on-panel (SOP) as memory and controller. Then the conventional poly – Si TFT is not enough in term of the speed and the current drive capability. To increase the speed and the current of the poly-Si TFT, a double gate structure was proposed to provide an effective way to enhance the current drive capability of poly- Si TFT. Due to the double gate provides an additional current path. However the double gate is an attractive approach, there has the high electric field near the drain junction. It causes the device a larger leakage current and aggravates the kink effect than the convention structure. Then the light doped drain (LDD) combines the double gate. It has a effective way to improve the high electric field of double gate. Then the LDD also can reduce the leakage and maintain the high on-current. But the structure needs two the process of the expensive CMP. In the past, the dual gate had reported. We know that the gate and the channel relationship. It has a good controlled to the channel and not confer the gate length. It this letter, we propose the dual gate length to effecting the device performance. We only need to change the gate mask. And my structure also effectively reduce the nonideal effect neat the drain junction. My structure requires an extra mask to increase the cost. Keyword: DCTFT, dual gate, nonideal effect.

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Książki na temat "Multigate transistor"

Sivasankaran, K., i Partha Sharathi Mallick. Multigate Transistors for High Frequency Applications. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9.

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Części książek na temat "Multigate transistor"

Sivasankaran, K., i Partha Sharathi Mallick. "Radio Frequency Transistor Stability and Design Challenges". W Multigate Transistors for High Frequency Applications, 9–23. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9_2.

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Sivasankaran, K., i Partha Sharathi Mallick. "Radio Frequency Stability Performance of Silicon Nanowire Transistor". W Multigate Transistors for High Frequency Applications, 61–69. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9_6.

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Sivasankaran, K., i Partha Sharathi Mallick. "Radio Frequency Stability Performance of SELBOX Inverted-T Junctionless FET". W Multigate Transistors for High Frequency Applications, 71–91. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9_7.

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Sivasankaran, K., i Partha Sharathi Mallick. "Radio Frequency Stability Performance of DG MOSFET". W Multigate Transistors for High Frequency Applications, 25–33. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9_3.

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Sivasankaran, K., i Partha Sharathi Mallick. "Radio Frequency Stability Performance of FinFET". W Multigate Transistors for High Frequency Applications, 49–60. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9_5.

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Sivasankaran, K., i Partha Sharathi Mallick. "Radio Frequency Stability Performance of Double-Gate Tunnel FET". W Multigate Transistors for High Frequency Applications, 35–47. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9_4.

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Sivasankaran, K., i Partha Sharathi Mallick. "Introduction". W Multigate Transistors for High Frequency Applications, 1–8. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9_1.

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Rathinam, Ramesh, Adhithan Pon i Arkaprava Bhattacharyya. "Phosphorene Multigate Field-Effect Transistors for High-Frequency Applications". W Sub-Micron Semiconductor Devices, 335–54. Boca Raton: CRC Press, 2022. http://dx.doi.org/10.1201/9781003126393-21.

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Madhulika Sharma, Savitesh, i Avtar Singh. "FinFETs and their Applications". W Nanoscale Field Effect Transistors: Emerging Applications, 47–67. BENTHAM SCIENCE PUBLISHERS, 2023. http://dx.doi.org/10.2174/9789815165647123010006.

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Researchers are motivated to develop novel electronic switches with improved low power properties and reduced short channel effects due to the downscaling of conventional MOSFETs (SCE). Using multi-gate FinFET technology could improve control of the gate over the channel charge. We have discussed FinFETs, or multigate transistors, in this chapter. The chapter will include the classification and detailed physics inside the device. The Fabrication section will explain the steps involved in manufacturing the device. The difficulties with FinFET technologies have also been discussed in order to examine the research gap. The performance improvement engineering techniques will give exposure to further improvement techniques in the device. The circuit applications will address the various analog/digital circuits based on FinFET.

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Streszczenia konferencji na temat "Multigate transistor"

Lou, Haijun, Binghua Li, Xinnan Lin, Jin He i Mansun Chan. "Investigations of fin vertical nonuniformity effects on junctionless multigate transistor". W 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2012. http://dx.doi.org/10.1109/icsict.2012.6467617.

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Gang Wu, Li Cai, Qiang Kang, Sen Wang i Qin Li. "A 8-bit parity code generator based on multigate single electron transistor". W 2008 3rd IEEE International Conference on Nano/Micro Engineered and Molecular Systems. IEEE, 2008. http://dx.doi.org/10.1109/nems.2008.4484314.

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Wu, Gang, i Li Cai. "Ternary multiplier of multigate single electron transistor: Design using 3-T gate". W 2010 8th IEEE International Conference on Control and Automation (ICCA). IEEE, 2010. http://dx.doi.org/10.1109/icca.2010.5524397.

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He, Chenlin, Fei You, Yi Wang, Zehua Xiao, Yaojia Fan i Songbai He. "A 22-32.7 GHz Linearized LNA in 65-nm CMOS Using Multigate Transistor Technique". W 2023 International Conference on Microwave and Millimeter Wave Technology (ICMMT). IEEE, 2023. http://dx.doi.org/10.1109/icmmt58241.2023.10276839.

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Singh, Dipak Kumar, Priyanka Mondal i M. W. Akram. "Bulk multigate junctionless transistor (BMGJLT) with non-uniform doping profile: An attractive device for scaling". W PROCEEDINGS OF INTERNATIONAL CONFERENCE ON RECENT TRENDS IN MECHANICAL AND MATERIALS ENGINEERING: ICRTMME 2019. AIP Publishing, 2020. http://dx.doi.org/10.1063/5.0025667.

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Young, Chadwin D. "Assessing the reliability and performance impact on the three-dimensional structure of multigate field effect transistor (MugFET)". W 2013 IEEE International Integrated Reliability Workshop (IIRW). IEEE, 2013. http://dx.doi.org/10.1109/iirw.2013.6804145.

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Dehdashti, Nima, Abhinav Kranti, Isabelle Ferain, Chi-Woo Lee, Ran Yan, Pedram Razavi, Ran Yu i Jean-Pierre Colinge. "Dissipative transport in Multigate silicon nanowire transistors". W 2010 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2010). IEEE, 2010. http://dx.doi.org/10.1109/sispad.2010.5604559.

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Snelgrove, Ashton, i Pierre-Emmanuel Gaillardon. "Programmable logic elements using multigate ambipolar transistors". W 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE, 2022. http://dx.doi.org/10.1109/ddecs54261.2022.9770137.

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Razavi, P., G. Fagas, I. Ferain, N. D. Akhavan, R. Yu i J. P. Colinge. "Performance investigation of short-channel junctionless multigate transistors". W 2011 12th International Conference on Ultimate Integration on Silicon (ULIS 2011). IEEE, 2011. http://dx.doi.org/10.1109/ulis.2011.5758005.

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Colinge, J. P. "Multigate transistors: Pushing Moore's law to the limit". W 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). IEEE, 2014. http://dx.doi.org/10.1109/sispad.2014.6931626.

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