Gotowe bibliografie tematyczne / MOSFETs

Gotowa bibliografia na temat „MOSFETs”

Autor: Grafiati
Data publikacji: 4 czerwca 2021
Data aktualizacji: 21 lutego 2023

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Artykuły w czasopismach na temat "MOSFETs"

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Funaki, Tsuyoshi, Yuki Nakano i Takashi Nakamura. "Comparative Study of SiC MOSFETs in High Voltage Switching Operation". Materials Science Forum 717-720 (maj 2012): 1081–84. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1081.

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SiC power device is expected to have high breakdown voltage with low on resistance, which cannot be attainable for conventional Si device. This study evaluates the switching performance of high voltage SiC MOSFETs with comparing to that of conventional Si power MOSFET having equivalent breakdown voltage. To this end, turn-on and turn-off switching operation of MOSFETs are assessed with resistive load for same conduction current density. Though the on resistance of SiC MOSFETs are quite lower than Si MOSFET, especially for trench gate type. But, SiC MOSFETs have larger terminal capacitance. Therefore, SiC MOSFETs show slower switching speed than Si MOSFETs for same current density condition.
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Yoshioka, Hironori, Junji Senzaki, Atsushi Shimozato, Yasunori Tanaka i Hajime Okumura. "Characterization of Interface State Density from Subthreshold Slope of MOSFETs at Low Temperatures (≥ 10 K)". Materials Science Forum 821-823 (czerwiec 2015): 745–48. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.745.

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We have evaluated interface state density (DIT) for EC−ET > 0.00 eV from the subthreshold slope deterioration of MOSFETs at low temperatures. We have compared two n-channel MOSFETs on the C- and a-faces with the gate oxide formed by pyrogenic oxidation followed by annealing in H2. The peak field-effect mobility (µFE,peak) for the C-face MOSFET was 57 cm2V-1s-1 at 300 K, which is lower than the half of 135 cm2V-1s-1 for the a-face MOSFET. We have shown that DIT very close to EC can well explain why µFE for C-face MOSFETs is lower than that for a-face MOSFETs. The value of DIT at 0.00 eV corresponding to the subthreshold slope at 11 K was 1.6×1014 cm-2eV-1 for the C-face MOSFET, which is more than the double of 6.4×1013 cm-2eV-1 for the a-face MOSFET.
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Albrecht, Matthaeus, Tobias Erlbacher, Anton J. Bauer i Lothar Frey. "Potential of 4H-SiC CMOS for High Temperature Applications Using Advanced Lateral p-MOSFETs". Materials Science Forum 858 (maj 2016): 821–24. http://dx.doi.org/10.4028/www.scientific.net/msf.858.821.

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In this work, the impact of the n-well doping concentration on the channel mobility and threshold voltage of p-MOSFETs and their applications in CMOS-devices is evaluated. For this purpose lateral p-channel MOSFETs with different channel lengths (L = 800 μm, 10 μm, 5 μm, and 3 μm) and doping concentrations (ND = 1015 cm-3 and 8·1015 cm-3) were fabricated and the respective field-effect mobility was extracted from the transfer-characteristics. Comparable to n-MOSFETs the mobility of p-MOSFETs was found to be the highest for the lowest doping concentration in the channel and the absolute value of the threshold voltage increases with increasing doping concentration [4]. To investigate its suitability for CMOS applications, inverters with different doping concentrations for n-MOSFET (NA = 1015 cm-3 and 1017 cm-3) und p-MOSFET (ND = 1015 cm-3 and 8·1015 cm-3) were built. For logic levels of 0 V and 10 V, the voltage transfer characteristic with the highest input ranges was obtained for a low p-MOSFET and a high n-MOSFET doping concentration. The lowest propagation delay time could be achieved with a low p-MOSFET and a low n-MOSFET doping concentration. At room temperature as well as at high temperatures T = 573 K the drain current of p-MOSFETs with channel lengths below 3 μm is hampered by the series resistance of the source and drain region which limits the performance of CMOS devices.
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Chaudhry, Amit, i Nath Roy. "A comparative study of hole and electron inversion layer quantization in MOS structures". Serbian Journal of Electrical Engineering 7, nr 2 (2010): 185–93. http://dx.doi.org/10.2298/sjee1002185c.

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In this paper, an analytical model has been developed to study inversion layer quantization in nanoscale Metal Oxide Semiconductor Field Effect Oxide p-(MOSFET). n-MOSFETs have been studied using the variation approach and the p-MOSFETs have been studied using the triangular well approach. The inversion charge density and gate capacitance analysis for both types of transistors has been done. There is a marked decrease in the inversion charge density and the capacitance of the p-MOSFET as compared to n-MOSFETs. The results are compared with the numerical results showing good agreement.
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Lichtenwalner, Daniel J., Brett Hull, Vipindas Pala, Edward Van Brunt, Sei-Hyung Ryu, Joe J. Sumakeris, Michael J. O’Loughlin, Albert A. Burk, Scott T. Allen i John W. Palmour. "Performance and Reliability of SiC Power MOSFETs". MRS Advances 1, nr 2 (2016): 81–89. http://dx.doi.org/10.1557/adv.2015.57.

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ABSTRACTDue to the wide bandgap and other key materials properties of 4H-SiC, SiC MOSFETs offer performance advantages over competing Si-based power devices. For example, SiC can more easily be used to fabricate MOSFETs with very high voltage ratings, and with lower switching losses. Silicon carbide power MOSFET development has progressed rapidly since the market release of Cree’s 1200V 4H-SiC power MOSFET in 2011. This is due to continued advancements in SiC substrate quality, epitaxial growth capabilities, and device processing. For example, high-quality epitaxial growth of thick, low-doped SiC has enabled the fabrication of SiC MOSFETs capable of blocking extremely high voltages (up to 15kV); while dopant control for thin highly-doped epitaxial layers has helped enable low on-resistance 900V SiC MOSFET production. Device design and processing improvements have resulted in lower MOSFET specific on-resistance for each successive device generation. SiC MOSFETs have been shown to have a long device lifetime, based on the results of accelerated lifetime testing, such as high-temperature reverse-bias (HTRB) stress and time-dependent dielectric breakdown (TDDB).
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Choi, Cheol-Woong, Jae-Hyeon So, Jae-Sub Ko i Dae-Kyong Kim. "Influence Analysis of SiC MOSFET’s Parasitic Capacitance on DAB Converter Output". Electronics 12, nr 1 (30.12.2022): 182. http://dx.doi.org/10.3390/electronics12010182.

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This paper proposes the influence analysis of silicon carbide (SiC) MOSFET’s parasitic output capacitance on a dual active bridge (DAB) converter. Power converters are required for DC grids and energy storage. Because SiC metal-oxide-semiconductor FETs (MOSFETs) have lower on-state resistance and faster reverse recovery time than Si MOSFETs, they can be controlled with lower losses and higher frequencies. MOSFETs have a parasitic capacitance. Because of the output parasitic capacitance, the switch voltage does not rise instantaneously during switching but has a delay. The output parasitic capacitance of the switch depends on its drain-to-source voltage, and this parasitic capacitance affects the output of the DAB converter by delaying the switch voltage. In this paper, in order to analyze the effect of the parasitic capacitance on the DAB converter output, the delay time was calculated through a formula, and this value was compared with a simulated value. In addition, the effect of the parasitic capacitance of the SiC MOSFET on the output of the DAB converter was presented by comparing the actual output voltage with the ideal output voltage and analyzing the effect of the output voltage according to the delay.
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Huang, W., T. Khan i T. P. Chow. "Geometry and Short Channel Effects on Enhancement-Mode n-Channel GaN MOSFETs on p and n-GaN/Sapphire Substrates". International Journal of High Speed Electronics and Systems 17, nr 01 (marzec 2007): 49–53. http://dx.doi.org/10.1142/s0129156407004230.

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In this paper, we have fabricated and compared the performance of lateral enhancement-mode GaN MOSFETs with linear and circular geometries. Circular MOSFETs show 2 to 4 orders of magnitude lower leakage current than that of linear MOSFETs. We also studied short channel behaviors and found that they are similar to those previously reported Si MOSFET.
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Allen, Scott, Vipindas Pala, E. VanBrunt, Brett Hull, Lin Cheng, S. Ryu, Jim Richmond, M. O’Loughlin, Al Burk i J. Palmour. "Next-Generation Planar SiC MOSFETs from 900 V to 15 kV". Materials Science Forum 821-823 (czerwiec 2015): 701–4. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.701.

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A family of planar MOSFETs with voltage ratings from 900 V to 15 kV are demonstrated. This family of planar MOSFETs represents Cree’s next generation MOSFET design and process, in which we continue to refine and evolve device design and processing to further shrink die sizes and enhance device performance. At voltage ratings of 3.3 kV and above, the specific on-resistance of the MOSFETs is approaching the theoretical limit. MOSFET switching performance in a clamped inductive switching circuit for the full range of voltage ratings is also demonstrated. Finally, improved threshold voltage and body diode stability under long-term stresses are presented.
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Bradford, T., i S. P. McAlister. "The use of multiple-gated MOSFETs in a simple application". Canadian Journal of Physics 74, S1 (1.12.1996): 182–85. http://dx.doi.org/10.1139/p96-855.

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We describe the design and simulation of the use of neuron MOSFETs in a simple application — that of a parallel-carry adder circuit. The neuron MOSFETs are multigated MOSFETs where the multiple coupling to a MOSFET's gate is made capacitatively. By using such devices a multilevel logic is achieved that allows functions in a circuit to be achieved with fewer transistors than in a conventional CMOS design.
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Ahn, Tae Jun, i Yun Seop Yu. "Interface Trap Charge Effects of Monolithic 3D Junctionless Field-Effect Transistors (JLFET) Inverter". Journal of Nanoscience and Nanotechnology 21, nr 8 (1.08.2021): 4252–57. http://dx.doi.org/10.1166/jnn.2021.19388.

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We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively. However, since JLFET and MOSFET have different current paths of bulk and interface in channel, respectively, MOSFET is more affected by the interface trap, and M3DINV-JLFET has almost less effect of interface trap at different thickness of interlayer dielectric, compared to M3DINV-MOSFET.
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Rozprawy doktorskie na temat "MOSFETs"

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Amberetu, Mathew Atekwana. "Lateral superjunction power MOSFETs". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/MQ63012.pdf.

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Dharmawardana, Kahanawita Gamaethiralalage Padmapani. "High performance power MOSFETs". Thesis, University of Cambridge, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.621963.

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Syme, Richard Travers. "Thermal transport in MOSFETs". Thesis, University of Cambridge, 1989. https://www.repository.cam.ac.uk/handle/1810/283665.

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Fard, A. M. "Hot electron currents in MOSFETs". Thesis, University of Surrey, 1994. http://epubs.surrey.ac.uk/843618/.

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Silicon has become the material of choice for fabrication of high circuit density, low defect density and high speed integration devices. CMOS technology has been favoured as an attractive candidate to take advantage of the performance enhancements available through miniturisation. However, hot carrier effects in general, and hot electron currents in particular, are posing as the main obstacle to a new era of sub-micron architecture in semiconductor device technology. Electron transport in modern sub-micron device is often governed by mechanisms that were not relevant to long-channel devices. Many of the classical device models are based upon such convenient assumptions as "thermal equilibrium" and "uniform local electric field". With the downscaling of devices, hot electron currents are becoming increasingly inherent. These currents arise from the fact that electrical fields in small geometry devices can reach very high values and can vary rapidly in space. The large electric field can Impart significant kinetic energies to the carriers. In thermal equilibrium, all elementary excitations in a semiconductor (eg. Electrons, holes, phonons) can be characterised by a temperature that is the same as the lattice temperature. Under the influence of large electric fields, however, the distribution function of these elementally excitations deviate from those in thermal equilibrium. The term "Hot Carriers" is often used to describe these non-equilibrium situations. In this thesis hot electron currents, in particular their physical origins and dependence upon various operational and geometrical parameters, have been discussed and then quantified in a number of models based on the "Lucky Drift" theory of transport. Temperature is then used as a tool to differentiate between the underlying physical processes, and to determine if reliability problems related to hot electron effects would improve under cryogenic operation. It has been the prime objective of this work from the outset to concentrate on the study of N-channel devices. This is primarily due to the fact that N-channel MOSFET's are more prone to hot electron effects, and therefore, studies in the nature of this enhanced susceptibility could prove to be more fruitful.
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Wang, Ping. "Wide band noise in MOSFETs". Thesis, Massachusetts Institute of Technology, 1993. http://hdl.handle.net/1721.1/12345.

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Chen, Xiangdong. "Bandgap engineering in vertical MOSFETs". Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3025006.

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Iqbal, M. M. H. "On the static performance of lateral high voltage MOSFETs and novel nanoscale accumulation mode MOSFETs". Thesis, University of Cambridge, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.604944.

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This research relates to static performance assessment of high voltage lateral MOSFETs and novel nanoscale accumulation mode MOSFETs. The static performance of the power semiconductor devices refers to breakdown voltage (BV) and specific on-resistance (sRon). Devising a relation or a power law between BV and sRon is absolutely crucial, as it determines the design criteria, the scaling of a technology with a voltage rating, the cost and ultimately the wider applicability of the technology in market. Here a technology-specific power law is proposed, which is applied to different Reduced SURface Field (RESURF) technologies for lateral power MOSFETs. The proposed power law introduces two technology-specific parameters, α and β, which are coupled with Baliga’s power law. Whilst in Baliga’s power law, parameters α and β are constant, here it will be demonstrated via comprehensive numerical simulations that parameters α and β can be different in various RESURF technologies. The numerical analysis also includes the variations of parameters α and β at maximum junction temperature of 125°C. First order 1D analytical models are proposed to examine the dependence of parameters α and β on technological process parameters and technology dictated material properties. A close match between the experimental data from the literature and the numerical-analytical results, establishes the validity of the newly proposed sRon vs. BV power law. This work takes into account that state-of-the-art RESURF technologies, i.e. single-, double-, triple-RESURF, partial SOI and linearly graded thin film SOI LDMOSFETs. The static performance of a nanoscale accumulation mode MOSFET incorporates to on-current, off-current, on-off ratio, threshold voltage, and subthreshold swing. A novel nanoscale transistor named Accumulation Metal Oxide Semiconductor Field Effect Transistor (AMOSFET) is proposed and experimentally demonstrated, which reveals excellent static performance. The AMOSFET is a very simple configuration that can have high performance transistors on thin films, a silicon-on-insulator (SOI) and nanowires (NWs). The configuration only requires a single doping type as the active layer, ohmic source and drain contacts spaced at minimum required distance from the gate, a minimum length gate, and a nanoscale dimension perpendicular to the gate. The nanoscale depth dimension forces the current path through an accumulated (on-state) or depleted (off-state) region. The numerical simulation study describes the static state operation, the role of gate capacitance and the importance of contacts’ ohmicity. Furthermore, the optimum device design considerations are also examined in numerical study. It is revealed in numerical study that the drain current has a weak dependence on the magnitude of the gate capacitance and the drive current is closely proportional to the mobility-doping density product.
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Lu, Huaxin. "Compact modeling of Double-Gate MOSFETs". Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3237382.

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Thesis (Ph. D.)--University of California, San Diego, 2006.
Title from first page of PDF file (viewed December 8, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 138-143).
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Herrmann, Tom. "Simulation und Optimierung neuartiger SOI-MOSFETs". Doctoral thesis, Universitätsbibliothek Chemnitz, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-63173.

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Die vorliegende Arbeit beschreibt die Berechnung und Optimierung von Silicon-On-Insulator-Metal-Oxide-Semiconductor-Field-Effect-Transistors, einschließlich noch nicht in Massenproduktion hergestellter neuartiger Transistorarchitekturen für die nächsten Technologiegenerationen der hochleistungsfähigen Logik-MOSFETs mit Hilfe der Prozess- und Bauelementesimulation. Die neuartigen Transistorarchitekturen umfassen dabei vollständig verarmte SOI-MOSFETs, Doppel-Gate-Transistoren und FinFETs. Die statische und dynamische Leistungsfähigkeit der neuartigen Transistoren wird durch Simulation bestimmt und miteinander verglichen. Der mit weiterer Skalierung steigende Einfluss von statistischen Variationen wird anhand der Oberflächenrauheit sowie der Polykantenrauheit untersucht. Zu diesem Zweck wurden Modelle für die Generierung der Rauheit erarbeitet und in das Programmsystem SIMBA implementiert. Die mikroskopische Rauheit wird mit der makroskopischen Bauelementesimulation kombiniert und deren Auswirkungen auf die Standardtransistoren und skalierte Bauelemente aufgezeigt. Zudem erfolgt eine ausführliche Diskussion der Modellierung mechanischer Verspannung und deren Anwendung zur Steigerung der Leistungsfähigkeit von MOSFETs. Die in SIMBA implementierten Modelle zur verspannungs-abhängigen Änderung der Ladungsträgerbeweglichkeit und Lage der Bandkanten werden ausführlich dargestellt und deren Einfluss auf die elektrischen Parameter von MOSFETs untersucht. Weiterhin wird die Verspannungsverteilung für verschiedene Herstellungsvarianten mittels der Prozess-simulation berechnet und die Wirkung auf die elektrischen Parameter dargestellt. Exponential- und Gaußverteilungsfunktionen bilden die Grundlage, um die mechanische Verspannung in der Bauelementesimulation nachzubilden, ohne die Verspannungsprofile aus der Prozesssimulation zu übernehmen. Darüber hinaus werden die Grenzfrequenzen der Logiktransistoren in Bezug auf die parasitären Kapazitäten und Widerstände und zur erweiterten MOSFET-Charakterisierung dargestellt.
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Chen, Chih-Hung. "High-frequency noise modeling of MOSFETs". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/mq24106.pdf.

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Książki na temat "MOSFETs"

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Limited, Ferranti Electronics. Mosfets. Chadderton: Ferranti Electronics Ltd, 1987.

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Zetex. Mosfets. Chadderton: Zetex, 1992.

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(Firm), Harris Semiconductor. Power MOSFETs: Buffered MOSFETs, intelligent discretes. Melbourne, Florida: Harris Semiconductor, 1994.

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Baliga, Jayant. Silicon RF power MOSFETs. Singapore: World Scientific, 2005.

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Silicon RF power MOSFETS. Singapore: World Scientific, 2005.

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Gimenez, Salvador Pinillos. Layout Techniques for MOSFETS. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-031-02031-5.

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Korec, Jacek. Low Voltage Power MOSFETs. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9320-5.

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Amberetu, Mathew Atekwana. Lateral superjunction power MOSFETs. Ottawa: National Library of Canada, 2001.

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Corporation, Toshiba. Power MOSFETs: SMD, high-voltage. Tokyo: Toshiba Corporation, 1992.

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Haddara, Hisham, red. Characterization Methods for Submicron MOSFETs. Boston, MA: Springer US, 1996. http://dx.doi.org/10.1007/978-1-4613-1355-7.

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Części książek na temat "MOSFETs"

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Iwai, Hiroshi, Simon Min Sze, Yuan Taur i Hei Wong. "MOSFETs". W Guide to State-of-the-Art Electron Devices, 21–36. Chichester, UK: John Wiley & Sons, Ltd, 2013. http://dx.doi.org/10.1002/9781118517543.ch2.

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Bhushan, Manjul, i Mark B. Ketchen. "MOSFETs". W Microelectronic Test Structures for CMOS Technology, 139–72. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9377-9_5.

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Singh, Ranbir, i B. Jayant Baliga. "Power Mosfets". W Cryogenic Operation of Silicon Power Devices, 65–81. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5751-7_6.

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Balestra, Francis, i Gérard Ghibaudo. "SOI MOSFETs". W Device and Circuit Cryogenic Operation for Low Temperature Electronics, 37–67. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3318-1_3.

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Khanna, Vinod Kumar. "SOI-MOSFETs". W NanoScience and Technology, 95–107. New Delhi: Springer India, 2016. http://dx.doi.org/10.1007/978-81-322-3625-2_6.

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Baliga, B. Jayant. "Power MOSFETs". W Fundamentals of Power Semiconductor Devices, 276–503. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-47314-7_6.

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Baliga, B. Jayant. "Power MOSFETs". W Fundamentals of Power Semiconductor Devices, 283–520. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-93988-9_6.

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Siu, Christopher. "Introduction to MOSFETs". W Electronic Devices, Circuits, and Applications, 65–84. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-80538-8_5.

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Klös, Alexander. "Alternative Nanostruktur-MOSFETs". W Nanoelektronik, 282–307. München: Carl Hanser Verlag GmbH & Co. KG, 2018. http://dx.doi.org/10.3139/9783446456969.010.

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Gimenez, Salvador Pinillos. "Octo Layout Style (Octagonal Gate Shape) for MOSFET". W Layout Techniques for MOSFETS, 21–29. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-031-02031-5_4.

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Streszczenia konferencji na temat "MOSFETs"

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Ye, Hua, i Pradeep Haldar. "Development of Cryogenic Power Modules for Superconducting Hybrid Power Electronic System". W ASME 2008 International Mechanical Engineering Congress and Exposition. ASMEDC, 2008. http://dx.doi.org/10.1115/imece2008-69274.

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This paper presents the developments of high-performance integrated cryogenic power modules, where both driver components and power MOSFETs are integrated in a single package. These modules are designed to be used in liquid nitrogen environment with extreme thermal cycling for the cryogenic power inverters. Compact high-voltage, cryogenic integrated power modules with single power MOSFET that exhibited more than 14x improvement in on-resistance and continuous current-carrying capability exceeding 40A. A multi-power MOSFETs integrated cryogenic power module is then developed in order to further increase the power density and reduce the size and weight of the cryogenic power system. The multi-power MOSFETs module was demonstrated to be able to carry a current above 100A with only a small increase in footprint compared with the single power MOSFET module. At the current level of 100A, the multi-power MOSFETs module has an on-resistance of 5.5mU` at 77K, which is 6 times smaller than that of the single power MOSFET integrated module developed. Two different design approaches taken in the developments of these modules are discussed in this paper.
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Hatakeyama, Tomoyuki, Kazuyoshi Fushinobu i Ken Okazaki. "Effect of the Device Structure in Electro-Thermal Analysis of Si CMOS". W ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/ipack2005-73151.

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Numerical calculation of submicron silicon MOSFET and CMOS device is performed. In order to have a higher degree of integration, the distance between two MOSFETs in CMOS structure can be decreased. But decreasing the distance between two MOSFETs results in an electrical interaction. In this research, by comparing the calculation result of n-type and p-type MOSFET and that of CMOS, we examine the interaction mechanism between n-type and p-type MOSFET in CMOS device when the distance between n-type and p-type MOSFET is decreased. From the calculated results, we investigate that the reason of the interaction between two MOSFET in CMOS is the forward bias at the p-n junction of substrate. Furthermore, we can estimate the distance, at the case of interaction, from the results of n-type and p-type MOSFET separately model, not from the results of CMOS model.
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Liu, Yong, Howard Allen i Stephen Martin. "Power Stack Die Package Design, Simulation and Reliability Analysis". W ASME 2010 International Mechanical Engineering Congress and Exposition. ASMEDC, 2010. http://dx.doi.org/10.1115/imece2010-40725.

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This paper presents a power stack die package design for a point of load buck converter. The buck converter system in package (SiP) consists of a lower side Mosfet and a high side Mosfet together with an IC controller. Its structure includes a premolded leadframe with an IC controller. The two Mosfets (both low side and higher side) are stacked on the premolded leadfrrame (LF) and IC controller. Solder balls are placed on the leadframe’s exposed lands, and together with the two drains of Mosfets, to form the stacked die power package. The thermal cycling simulations for the solder balls to connect the PCB and solder joints of the two Mosfet die to the leadframe pads are studied. The failure mechanism and reliability analysis of the power package in TMCL test are discussed.
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Kearney, Ian, i Hank Sung. "Integrated ESD Robustness through Device Analysis of Ultra-Small Low Voltage Power MOSFETs". W ISTFA 2014. ASM International, 2014. http://dx.doi.org/10.31399/asm.cp.istfa2014p0350.

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Abstract Low voltage power MOSFETs often integrate voltage spike protection and gate oxide ESD protection. The basic concept of complete-static protection for the power MOSFETs is the prevention of static build-up where possible and the quick, reliable removal of existing charges. The power MOSFET gate is equivalent to a low voltage low leakage capacitor. The capacitor plates are formed primarily by the silicon gate and source metallization. The capacitor dielectric is the silicon oxide gate insulation. Smaller devices have less capacitance and require less charge per volt and are therefore more susceptible to ESD than larger MOSFETs. A FemtoFETTM is an ultra-small, low on-resistance MOSFET transistor for space-constrained handheld applications, such as smartphones and tablets. An ESD event, for example, between a fingertip and the communication-port connectors of a cell phone or tablet may cause permanent system damage. Through electrical characterization and global isolation by active photon emission, the authors identify and distinguish ESD failures. Thermographic analysis provided additional insight enabling further separation of ESD failmodes. This paper emphasizes the role of failure analysis in new product development from the create phase through to product ramp. Coupled with device electrical simulation, the analysis observations led to further design enhancement.
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Yining, Liu, Wang Renze, Yang Yapeng, Zhang Jiangang, Wang Ning, Feng Zongyang, Jia Linsheng i Liang Boning. "The Choice of MOSFET Manufacturing Technique Used in Emergency Response Robot". W 2020 International Conference on Nuclear Engineering collocated with the ASME 2020 Power Conference. American Society of Mechanical Engineers, 2020. http://dx.doi.org/10.1115/icone2020-16222.

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Abstract For the aim of helping the development of robots used in Radiological Emergency Planning and Preparedness, the Total Ionizing Dose (TID) effects on the threshold voltage shift (ΔVth) of different kinds of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) with different geometry and different scaling technology was compared. The different gate width and length dependent between bulk Complementary Metal-Oxide-Semiconductor Transistor (CMOS) process and nanowire (NW) MOSFET as well as higher and lower technology node is noticed. The reason of this difference is explained from the aspects of Radiation Induced Narrow channel effect (RINCE) and Radiation Induced Short channel effect (RISCE). It is found that some studies in recent years have corrected the influence of negative bias temperature instability (NBTI) when considering radiation effects. The TID effects on ΔVth of several kinds of new devices such as MOSFETs with new layout geometry as well as Ge-channel and GaN channel MOSFETs are described which can be investigated more deeply.
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Xu, Dongyan, Yuejun Kang, Dongqing Li, Deyu Li, Manoj Sridhar, Anthony B. Hmelo i Leonard C. Feldman. "Ultra-Sensitive Fluidic Sensors by Integrating Fluidic Circuits and MOSFETs". W ASME 2007 International Mechanical Engineering Congress and Exposition. ASMEDC, 2007. http://dx.doi.org/10.1115/imece2007-42518.

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Nanofluidic sensors have been developed over the past decade and demonstrated the capability of sensing single DNA molecules. One important and promising class of nanofluidic devices detects single molecules by inserting a nanopore or nanochannel between two fluid cells and inducing an ionic current by applying an electric bias across the nanopore or nanochannel. When molecules are translocated through the nanopore/nanochannel, a modulation of the baseline ionic current can be observed. In this scheme, the ionic current modulation is approximately the same as the channel resistance modulation, requiring the channel size to be comparable to the molecules to be detected. Here we report on a new sensing scheme to detect the translocation of particles through a fluidic channel, which amplifies the resistance modulation by up to 75 times. In this scheme, the device connects the gate of a MOSFET with a fluidic circuit and monitors the modulation of MOSFET’s drain current to detect particles. We demonstrate that amplification can be achieved from both the fluidic circuit and the MOSFET. For a 9.86 μm diameter polystyrene bead that occupies 0.7% of the total volume of the sensing channel, results show that the drain current of the MOSFET is blocked by 30–46%. We also demonstrate the capability of this device to distinguish particles with similar sizes but different surface charges as they translocate through the sensing channel. More interestingly, the experiments with CD4+ T lymphocyte cells show another modulation pattern: the MOSFET’s drain current is first enhanced and then blocked, which is not fully understood and needs further investigation. Although at this moment the device is based on microchannels and the particles detected are micron-size beads and cells, we expect that the same scheme can be applied to nanofluidic circuits for single molecule detection.
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Tiwari, Ankit, Trevor Davey i Matthew Willis. "CFD Analysis of Transient Heat Conduction in the Electronic Control Circuitry of Steering Wheel Column Adjustment System". W ASME 2021 Heat Transfer Summer Conference collocated with the ASME 2021 15th International Conference on Energy Sustainability. American Society of Mechanical Engineers, 2021. http://dx.doi.org/10.1115/ht2021-63973.

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Abstract Automotive grade 3 electronic components are expected to meet their functional, performance and thermal safety requirements within the ambient temperature range from −40-degree C to +85-degree C. In this study, CFD and thermal analysis of electronic control circuitry of a power steering wheel column adjustment system is performed. It consists of 6 MOSFETs (Metal Oxide Semi-Conductor Field Effect Transistor) packaged in 3 Dual package MOSFET casings (Q6, Q7 and Q8) that are arranged in two H-bridge configurations for dependent control of the two motors. Two of these MOSFETs cause thermal power dissipation during the normal operation of the system. There are also other thermally significant devices such as a reverse polarity protection MOSFET (Q1), two inductors used in a low pass filter and one current sense resistor. Because of cost and packaging limitations, there are no external heat sinks to enhance heat transfer. The components will rely on the Printed Circuit Board (PCB) and plated-through-holes/thermal vias for heat transfer to maintain operation within the thermal safety limits. The inherent transient nature of operation of the power steering wheel column adjustment system causes the circuit to draw high current for a short duration of time. This necessitates temperature dependent heat source formulation. In this study, an initial CFD study was performed to assess the thermal safety of all the electronic components in the control circuitry. It was found that the electronic components such as MOSFETs and inductors were below the maximum operating junction temperature under the hot limit condition (+85degree C) for the entire duration of operation. However, under the cold limit condition (−40-degree C), both the MOSFETs and the inductors were significantly hotter than the maximum junction temperature. Based on CFD results, the sizing and placement of thermal vias may be optimized. Further, a comparative analysis was performed to assess the different levels of fidelity offered by lumped PCB model, multi-layer PCB model and explicit modeling of thermal vias in PCB.
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Popov, Dmitry. "TCAD SIMULATION OF SELBOX AND DSOI CMOS SRAM FAILURE". W International Forum “Microelectronics – 2020”. Joung Scientists Scholarship “Microelectronics – 2020”. XIII International conference «Silicon – 2020». XII young scientists scholarship for silicon nanostructures and devices physics, material science, process and analysis. LLC MAKS Press, 2020. http://dx.doi.org/10.29003/m1608.silicon-2020/227-229.

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A mixed TCAD-SPICE simulation of the heavy ion impact into a SRAM on SOI CMOS transistors was carried out. The dependence of the threshold LET on temperature was investigated for three configurations of 0.24 μm SOI MOSFET: traditional SOI, Selective BOX and Double SOI. The radiation hardness of SRAM on Double SOI MOSFETs is significantly improved by applying a negative bias to the additional silicone layer has been shown.
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Petrosyants, Konstantin. "INTRODUCTION INTO TCAD AND SPICE MODELING OF SEMICONDUCTOR DEVICES AND IC COMPONENTS." W International Forum “Microelectronics – 2020”. Joung Scientists Scholarship “Microelectronics – 2020”. XIII International conference «Silicon – 2020». XII young scientists scholarship for silicon nanostructures and devices physics, material science, process and analysis. LLC MAKS Press, 2020. http://dx.doi.org/10.29003/m1550.silicon-2020/35-40.

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Conventional BJT, MOSFET, JFET, DMOST, IGBT structures fabricated on bulk silicon and SOI/SOS substrates are characterized as the object of modeling. Popular TCAD simulators and SPICE device models libraries are presented. The model parameters extraction strategies for TCAD device and SPICE circuit simulation based on data proceeding of physical and electrical measurements are described. The typical examples of TCAD and SPICE modeling of BJTs and MOSFETs fabricated by conventional silicon IC technologies are presented.
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Ni, Chunjian, Zlatan Aksamija, Jayathi Y. Murthy i Umberto Ravaioli. "Coupled Electro-Thermal Simulation of MOSFETs". W ASME 2009 InterPACK Conference collocated with the ASME 2009 Summer Heat Transfer Conference and the ASME 2009 3rd International Conference on Energy Sustainability. ASMEDC, 2009. http://dx.doi.org/10.1115/interpack2009-89182.

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Thermal transport in metal-oxide-semiconductor field effect transistors (MOSFETs) due to electron-phonon scattering is simulated using phonon generation rates obtained from an electron Monte Carlo device simulation. The device simulation accounts for a full band description of both electrons and phonons considering 22 types of electron-phonon scattering events. Detailed profiles of phonon emission/absorption rates in the physical and momentum spaces are generated and are used in a MOSFET thermal transport simulation with a recently-developed anisotropic relaxation time model based on the Boltzmann transport equation (BTE). Comparisons with a Fourier conduction model reveal that the anisotropic heat conduction model predicts higher maximum temperatures because it accounts for the bottlenecks in phonon scattering pathways. Heat fluxes leaving the boundaries associated with different phonon polarizations and frequencies are also examined to reveal the main modes responsible for transport. It is found that though the majority of the heat generation is in the optical modes, the heat generated in the acoustic modes is not negligible. The modes primarily responsible for the transport of heat are found to be medium-to-high frequency acoustic phonon modes.
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Raporty organizacyjne na temat "MOSFETs"

1

Ferry, David K. Transport in Submicron MOSFETS. Fort Belvoir, VA: Defense Technical Information Center, wrzesień 1986. http://dx.doi.org/10.21236/ada173156.

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Wu, Jian, J. Hu, J. H. Zhao, X. Wang, X. Li i T. Burke. High Mobility 4H-SiC Trenched Gate MOSFETs. Fort Belvoir, VA: Defense Technical Information Center, sierpień 2006. http://dx.doi.org/10.21236/ada507271.

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Matocha, Kevin. High-Current SiC MOSFETs for Automotive Applications (non-proprietary). Office of Scientific and Technical Information (OSTI), styczeń 2018. http://dx.doi.org/10.2172/1416749.

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Wilson, Charles L., i James L. Blue. MOS1 a program for two-dimensional analysis of Si MOSFETs. Gaithersburg, MD: National Bureau of Standards, 1985. http://dx.doi.org/10.6028/nbs.sp.400-77.

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Offord, Bruce, C. Milligan, H. Jazo i J. Meloling. An Ultra Low Power 180-Degree, 1-Bit Phase Shifter using MOSFETS. Fort Belvoir, VA: Defense Technical Information Center, wrzesień 2009. http://dx.doi.org/10.21236/ada513799.

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Hall, Douglas C., Gregory L. Snider i Bruce A. Bunker. III-V Compound Semiconductor Native Oxide Mosfets With Focus on Interface Studies. Fort Belvoir, VA: Defense Technical Information Center, lipiec 2001. http://dx.doi.org/10.21236/ada388295.

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Peršun, Marijan. Scaling of the Silicon-on-Insulator Si and Si1-xGex p-MOSFETs. Portland State University Library, styczeń 2000. http://dx.doi.org/10.15760/etd.6810.

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Gampa, Ravi. High Voltage Multiplier: A New, Compact Design using SiC High Frequency MOSFETs. Office of Scientific and Technical Information (OSTI), październik 2021. http://dx.doi.org/10.2172/1863893.

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Cooper, James A., i Jr. Development of SiC Power MOSFETs with Low On-Resistance for Military and Commercial Applications. Fort Belvoir, VA: Defense Technical Information Center, marzec 2003. http://dx.doi.org/10.21236/ada414680.

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Cook, E. Improving Switching Performance of Power MOSFETs Used in High Rep-Rate, Short Pulse, High-Power Pulsers. Office of Scientific and Technical Information (OSTI), wrzesień 2006. http://dx.doi.org/10.2172/896001.

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