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Gotowa bibliografia na temat „Modern processors”

Autor: Grafiati

Data publikacji: 6 września 2023

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Artykuły w czasopismach na temat "Modern processors"

Chen, Kuo Yi, Fuh Gwo Chen i Jr Shian Chen. "A Cost-Effective Hardware Approach for Measuring Power Consumption of Modern Multi-Core Processors". Applied Mechanics and Materials 110-116 (październik 2011): 4569–73. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.4569.

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Multiple processor cores are built within a chip by advanced VLSI technology. With the decreasing prices, multi-core processors are widely deployed in both server and desktop systems. The workload of multi-threaded applications could be separated to different cores by multiple threads, such that application threads can run concurrently to maximize overall execution speed of the applications. Moreover, for the green trend of computing nowadays, most of modern multi-core processors have a functionality of dynamic frequency turning. The power-level tuning techniques are based on Dynamic Voltage and Frequency Scaling (DVFS). In order to evaluate the performance of various power-saving approaches, an appropriate technique to measure the power consumption of multi-core processors is important. However, most of approaches estimate CPU power consumption only from CMOS power consumption data and CPU frequency. These approaches only estimate the dynamic power consumption of multi-core processors, the static power consumption is not be included. In this study, a hardware approach for the power consumption measurement of multi-core processors is proposed. Thus the power consumption of a CPU could be measured precisely, and the performance of CPU power-saving approaches can be evaluated well.

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Muralidharan, K., i S. Uma Maheswari. "Design of Low Power Cam Memory Cell for the Next Generation Network Processors". IRO Journal on Sustainable Wireless Systems 3, nr 4 (3.12.2021): 208–18. http://dx.doi.org/10.36548/jsws.2021.4.001.

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In the modern world, high performance embedded applications in the field of multimedia, networking, and imaging are increasing day by day. These applications require high performance and more complex out-of-order superscalar processor. These complex dynamic instructions scheduling superscalar processors need higher levels of on-chip integration designs which are often associated with power dissipation. These out-of-order superscalar processors achieve higher performance compared to other processors by simultaneous fetching, decoding and execution for multiple instructions in out-of-order that are used in the next generation network processors. The main data path resources of the processor use CAM+RAM structure which is the major power consuming unit in the overall out-of-order processor design. The proposed new design of CAM+RAM with power-gating technique reduces the overall average power consumption compared to the conventional design without any significant impact on their performance.

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Sharma, Anuj, i Elias S. Manolakos. "Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures". BioMed Research International 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/563674.

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Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel’s experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel’s Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a highF-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlyingrckskelalgorithmic skeletons library, is available via GitHub.

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Kidwai, Hashir Karim, Fadi N. Sibai i Tamer Rabie. "Parallelization and Performance Evaluation of an Edge Detection Algorithm on a Streaming Multi-Core Engine". Journal of Information Technology Research 2, nr 4 (październik 2009): 81–91. http://dx.doi.org/10.4018/jitr.2009062906.

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In the world of multi-core processors, the STI Cell Broadband Engine (BE) stands out as a heterogeneous 9-core processor with a PowerPC host processor (PPE) and 8 synergic processor engines (SPEs). The Cell BE architecture is designed to improve upon conventional processors in graphics and related areas by integrating 8 computation engines each with multiple execution units and large register sets to achieve a high performance per area return. In this paper, we discuss the parallelization, implementation and performance evaluation of an edge detection image processing application based on the Roberts edge detector on the Cell BE. The authors report the edge detection performance measured on a computer with one Cell processor and with varying numbers of synergic processor engines enabled. These results are compared to the results obtained on the Cell’s single PPE with all 8 SPEs disabled. The results indicate that edge detection performs 10 times faster on the Cell BE than on modern RISC processors.

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Vyukova, N. I., V. A. Galatenko i S. V. Samborskij. "Exploiting Vector Extensions of Modern Processors". PROGRAMMNAYA INGENERIA 7, nr 4 (12.04.2016): 147–57. http://dx.doi.org/10.17587/prin.7.147-157.

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Deris, Kaveh Jokar, i Amirali Baniasadi. "Power-aware BTB for modern processors". Computers & Electrical Engineering 36, nr 5 (wrzesień 2010): 902–11. http://dx.doi.org/10.1016/j.compeleceng.2008.04.008.

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Hanafi Por, Porya Soltani, Abbas Ramazani i Mojtaba Hosseini Toodeshki. "Temperature and performance evaluation of multiprocessors chips by optimal control method". Bulletin of Electrical Engineering and Informatics 12, nr 2 (1.04.2023): 749–59. http://dx.doi.org/10.11591/eei.v12i2.4291.

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Multi-core processors support all modern electronic devices nowadays. However, temperature and performance management are one of the most critical issues in the design of today’s microprocessors. In this paper, we propose a framework by using an optimal control method based on fan speed and frequency control of the multi-core processor. The goal is to optimize performance and at the same time avoid violating an expected temperature. Our proposed method uses a high-precision thermal and power model for multi-core processors. This method is validated on asymmetric ODROID-XU4 multi-core processor. The experimental results show the ability of the proposed method to achieve the adequate trade-off between performance and temperature control.

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Kuzminsky, Mikhail Borisovich. "Modern server ARM processors for supercomputers: A64FX and others. Initial data of benchmarks". Program Systems: Theory and Applications 13, nr 1 (22.02.2022): 131–94. http://dx.doi.org/10.25209/2079-3316-2022-13-1-131-194.

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A comparative analysis of the performance of ARM server processors used on supercomputers or also aimed at high-performance computing (HPC) is given. Fujitsu A64FX, Marvell ThunderX2 and Huawei Kunpeng 920 were selected for the initial performance analysis. The HPC performance review focuses primarily on benchmarks and applications for the A64FX, which supports longer vectors than other ARM processors and has higher peak performance. The performance of the A64FX is compared against corresponding data for Intel Xeon Skylake and Cascade Lake, and AMD EPYC with Zen 2 and 3 (Roma and Milan), as well as Nvidia V100 and A100 GPUs. A short set of potential pros and cons of the A64FX microarchitecture has been formulated. Comparison of performance data obtained using different compilers for A64FX. Features have been formed when A64FX usually gives advantages in performance over x86-64, and when it concedes to x86-64. It is clear that the use of A64FX in supercomputers can grow further. There is an assumption that x86-64 hegemony in HPC will decrease, in particular, due to the increased use of server ARM processors. But the analysis of A64FX and new AArch64 processors expected in the near future showed that A64FX will not necessarily lead in this process.

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Faeq, Mays K., i Safaa S. Omran. "Cache coherency controller for MESI protocol based on FPGA". International Journal of Electrical and Computer Engineering (IJECE) 11, nr 2 (1.04.2021): 1043. http://dx.doi.org/10.11591/ijece.v11i2.pp1043-1052.

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In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each processor called a core. The new chips of processors called a multi-core processor. This new design makes the processors to work simultanously for more than one job or all the cores working in parallel for the same job. All cores are similar in their design, and each core has its own cache memory, while all cores shares the same main memory. So if one core requestes a block of data from main memory to its cache, there should be a protocol to declare the situation of this block in the main memory and other cores.This is called the cache coherency or cache consistency of multi-core. In this paper a special circuit is designed using very high speed integrated circuit hardware description language (VHDL) coding and implemented using ISE Xilinx software. The protocol used in this design is the modified, exclusive, shared and invalid (MESI) protocol. Test results were taken by using test bench, and showed all the states of the protocol are working correctly.

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Chattra, Eka, i Obrin Candra Brillyant. "Implementation of Meltdown Attack Simulation for Cybersecurity Awareness Material". ACMIT Proceedings 7, nr 1 (7.07.2021): 6–13. http://dx.doi.org/10.33555/acmit.v7i1.102.

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One of the rising risk in cybersecurity is an attack on cyber physical system. Today’s computer systems has evolve through the development of processor technology, namely by the use of optimization techniques such as out-of-order execution. Using this technique, processors can improve computing system performance without sacrificing manufacture processes. However, the use of these optimization techniques has vulnerabilities, especially on Intel processors. The vulnerability is in the form of data exfiltration in the cache memory that can be exploit by an attack. Meltdown is an exploit attack that takes advantage of such vulnerabilities in modern Intel processors. This vulnerability can be used to extract data that is processed on that specific computer device using said processors, such as passwords, messages, or other credentials. In this paper, we use qualitative research which aims to describe a simulation approach with experience meltdown attack in a safe environment with applied a known meltdown attack scheme and source code to simulate the attack on an Intel Core i7 platform running Linux OS. Then we modified the source code to prove the concept that the Meltdown attack can extract data on devices using Intel processors without consent from the authorized user.

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Rozprawy doktorskie na temat "Modern processors"

Ljungkvist, Karl. "Techniques for finite element methods on modern processors". Licentiate thesis, Uppsala universitet, Avdelningen för beräkningsvetenskap, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-242186.

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In this thesis, methods for efficient utilization of modern computer hardware for numerical simulation are considered. In particular, we study techniques for speeding up the execution of finite-element methods. One of the greatest challenges in finite-element computation is how to efficiently perform the the system matrix assembly efficiently in parallel, due to its complicated memory access pattern. The main difficulty lies in the fact that many entries of the matrix are being updated concurrently by several parallel threads. We consider transactional memory, an exotic hardware feature for concurrent update of shared variables, and conduct benchmarks on a prototype processor supporting it. Our experiments show that transactions can both simplify programming and provide good performance for concurrent updates of floating point data. Furthermore, we study a matrix-free approach to finite-element computation which avoids the matrix assembly. Motivated by its computational properties, we implement the matrix-free method for execution on graphics processors, using either atomic updates or a mesh coloring approach to handle the concurrent updates. A performance study shows that on the GPU, the matrix-free method is faster than a matrix-based implementation for many element types, and allows for solution of considerably larger problems. This suggests that the matrix-free method can speed up execution of large realistic simulations.
UPMARC
eSSENCE

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Picciau, Andrea. "Concurrency and data locality for sparse linear algebra on modern processors". Thesis, Imperial College London, 2017. http://hdl.handle.net/10044/1/58884.

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Graphics processing units (GPUs) are used as accelerators for algorithms in which the same instructions are carried out on different data. Algorithms for sparse linear algebra can achieve good performance on GPU, although they tend to have an irregular pattern of accesses to memory. The performance of these algorithms is highly dependent on input data. In fact, the parallelism these algorithms can achieve is limited by the opportunities for concurrency given by the data. Focusing on the solution of sparse riangular linear systems of equations, this thesis shows that a good partitioning of the data and a good scheduling of the computation can greatly improve performance on GPUs. For this class of algorithms, a partition of the data that maximises concurrency in the execution does not necessarily achieve the best performance. Instead, improving data locality by reducing concurrency reduces the latency of memory access and consequently the execution time. First, this work characterises the problem formally using graph theory and performance models. Then, algorithms that can be used effectively to partition the data are described. These algoritms aim to balance concurrency and data locality automatically. This approach is evaluated experimentally on the solution of linear equations with the preconditioned conjugate gradient method. Also, the thesis shows that the proposed approach can be used in the case when a matrix changes during the execution of an algorithm from one iteration to the other, like in the simplex method. In this case, the approach proposed in this thesis allows to update the partition of the matrix from one iteration to the other. Finally, the algorithms and performance models developed in the thesis are used to discuss the limitations of the acceleration of the simplex method with GPUs.

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Deb, Abhishek. "HW/SW mechanisms for instruction fusion, issue and commit in modern u-processors". Doctoral thesis, Universitat Politècnica de Catalunya, 2012. http://hdl.handle.net/10803/81561.

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In this thesis we have explored the co-designed paradigm to show alternative processor design points. Specifically, we have provided HW/SW mechanisms for instruction fusion, issue and commit for modern processors. We have implemented a co-designed virtual machine monitor that binary translates x86 instructions into RISC like micro-ops. Moreover, the translations are stored as superblocks, which are a trace of basic blocks. These superblocks are further optimized using speculative and non-speculative optimizations. Hardware mechanisms exists in-order to take corrective action in case of misspeculations. During the course of this PhD we have made following contributions. Firstly, we have provided a novel Programmable Functional unit, in-order to speed up general-purpose applications. The PFU consists of a grid of functional units, similar to CCA, and a distributed internal register file. The inputs of the macro-op are brought from the Physical Register File to the internal register file using a set of moves and a set of loads. A macro-op fusion algorithm fuses micro-ops at runtime. The fusion algorithm is based on a scheduling step that indicates whether the current fused instruction is beneficial or not. The micro-ops corresponding to the macro-ops are stored as control signals in a configuration. The macro-op consists of a configuration ID which helps in locating the configurations. A small configuration cache is present inside the Programmable Functional unit, that holds these configurations. In case of a miss in the configuration cache configurations are loaded from I-Cache. Moreover, in-order to support bulk commit of atomic superblocks that are larger than the ROB we have proposed a speculative commit mechanism. For this we have proposed a Speculative commit register map table that holds the mappings of the speculatively committed instructions. When all the instructions of the superblock have committed the speculative state is copied to Backend Register Rename Table. Secondly, we proposed a co-designed in-order processor with with two kinds of accelerators. These FU based accelerators run a pair of fused instructions. We have considered two kinds of instruction fusion. First, we fused a pair of independent loads together into vector loads and execute them on vector load units. For the second kind of instruction fusion we have fused a pair of dependent simple ALU instructions and execute them in Interlock Collapsing ALUs (ICALU). Moreover, we have evaluated performance of various code optimizations such as list-scheduling, load-store telescoping and load hoisting among others. We have compared our co-designed processor with small instruction window out-of-order processors. Thirdly, we have proposed a co-designed out-of-order processor. Specifically we have reduced complexity in two areas. First of all, we have co-designed the commit mechanism, that enable bulk commit of atomic superblocks. In this solution we got rid of the conventional ROB, instead we introduce the Superblock Ordering Buffer (SOB). SOB ensures program order is maintained at the granularity of the superblock, by bulk committing the program state. The program state consists of the register state and the memory state. The register state is held in a per superblock register map table, whereas the memory state is held in gated store buffer and updated in bulk. Furthermore, we have tackled the complexity of Out-of-Order issue logic by using FIFOs. We have proposed an enhanced steering heuristic that fixes the inefficiencies of the existing dependence-based heuristic. Moreover, a mechanism to release the FIFO entries earlier is also proposed that further improves the performance of the steering heuristic.
En aquesta tesis hem explorat el paradigma de les màquines issue i commit per processadors actuals. Hem implementat una màquina virtual que tradueix binaris x86 a micro-ops de tipus RISC. Aquestes traduccions es guarden com a superblocks, que en realitat no és més que una traça de virtuals co-dissenyades. En particular, hem proposat mecanismes hw/sw per a la fusió d’instruccions, blocs bàsics. Aquests superblocks s’optimitzen utilitzant optimizacions especualtives i d’altres no speculatives. En cas de les optimizations especulatives es consideren mecanismes per a la gestió de errades en l’especulació. Al llarg d’aquesta tesis s’han fet les següents contribucions: Primer, hem proposat una nova unitat functional programmable (PFU) per tal de millorar l’execució d’aplicacions de proposit general. La PFU està formada per un conjunt d’unitats funcionals, similar al CCA, amb un banc de registres intern a la PFU distribuït a les unitats funcionals que la composen. Les entrades de la macro-operació que s’executa en la PFU es mouen del banc de registres físic convencional al intern fent servir un conjunt de moves i loads. Un algorisme de fusió combina més micro-operacions en temps d’execució. Aquest algorisme es basa en un pas de planificació que mesura el benefici de les decisions de fusió. Les micro operacions corresponents a la macro operació s’emmagatzemen com a senyals de control en una configuració. Les macro-operacions tenen associat un identificador de configuració que ajuda a localitzar d’aquestes. Una petita cache de configuracions està present dintre de la PFU per tal de guardar-les. En cas de que la configuració no estigui a la cache, les configuracions es carreguen de la cache d’instruccions. Per altre banda, per tal de donar support al commit atòmic dels superblocks que sobrepassen el tamany del ROB s’ha proposat un mecanisme de commit especulatiu. Per aquest mecanisme hem proposat una taula de mapeig especulativa dels registres, que es copia a la taula no especulativa quan totes les instruccions del superblock han comitejat. Segon, hem proposat un processador en order co-dissenyat que combina dos tipus d’acceleradors. Aquests acceleradors executen un parell d’instruccions fusionades. S’han considerat dos tipus de fusió d’instructions. Primer, combinem un parell de loads independents formant loads vectorials i els executem en una unitat vectorial. Segon, fusionem parells d’instruccions simples d’alu que són dependents i que s’executaran en una Interlock Collapsing ALU (ICALU). Per altra aquestes tecniques les hem evaluat conjuntament amb diverses optimizacions com list scheduling, load-store telescoping i hoisting de loads, entre d’altres. Aquesta proposta ha estat comparada amb un processador fora d’ordre. Tercer, hem proposat un processador fora d’ordre co-dissenyat efficient reduint-ne la complexitat en dos areas principals. En primer lloc, hem co-disenyat el mecanisme de commit per tal de permetre un eficient commit atòmic del superblocks. En aquesta solució hem substituït el ROB convencional, i en lloc hem introduït el Superblock Ordering Buffer (SOB). El SOB manté l’odre de programa a granularitat de superblock. L’estat del programa consisteix en registres i memòria. L’estat dels registres es manté en una taula per superblock, mentre que l’estat de memòria es guarda en un buffer i s’actulitza atòmicament. La segona gran area de reducció de complexitat considerarada és l’ús de FIFOs a la lògica d’issue. En aquest últim àmbit hem proposat una heurística de distribució que solventa les ineficiències de l’heurística basada en dependències anteriorment proposada. Finalment, i junt amb les FIFOs, s’ha proposat un mecanisme per alliberar les entrades de la FIFO anticipadament.

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Welin-Berger, Robert, i Anton Bäckström. "Optimizing Strassen's multiplication algorithm for modern processors : A study in optimizing matrix multiplications for large matrices on modern CPUs". Thesis, KTH, Skolan för datavetenskap och kommunikation (CSC), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-186418.

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This paper examines how to write code to gain high performance on modern computers as well as the importance of well planned data structures. The experiments were run on a computer with an Intel i5-5200U CPU, 8GB of RAM running Linux Mint 17.For the measurements Winograd's variant of Strassen's matrix multiplication algorithm was implemented and eventually compared to Intel's math kernel library (MKL). A quadtree data structure was implemented to ensure good cache locality. Loop unrolling and tiling was combined to improve cache performance on both L1 and L2 cache taking into regard the out of order behavior of modern CPUs. Compiler hints were partially used but a large part of the time critical code was written in pure assembler. Measurements of the speed performance of both floats and doubles were performed and substantial differences in running times were found.While there was a substantial difference between the best implementation and MKL for both doubles and floats at smaller sizes, a difference of only 1\% in execution time was achieved for floats at the size of 2^14. This was achieved without any specific tuning and could be expected to be improved if more time was spent on the implementation.

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Price, Daniel Kenneth. "Development of an accelerated finite-difference time-domain solver using modern graphics processors". Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 111 p, 2009. http://proquest.umi.com/pqdweb?did=1654487621&sid=4&Fmt=2&clientId=8331&RQT=309&VName=PQD.

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Krepis, Dimitrij. "A study of simulation and verification of a many-core architecture on two modern reconfigurable platforms". Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 70 p, 2007. http://proquest.umi.com/pqdweb?did=1407501151&sid=8&Fmt=2&clientId=8331&RQT=309&VName=PQD.

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Gammon, J. "An investigation into the use of word processors in the teaching of modern languages at a tertiary college". Thesis, University of Surrey, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.383517.

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Pinheiro, Maicon Aparecido. "Processos pontuais no modelo de Guiol-Machado-Schinazi de sobrevivência de espécies". Universidade de São Paulo, 2015. http://www.teses.usp.br/teses/disponiveis/45/45133/tde-01062016-191528/.

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Recentemente, Guiol, Machado e Schinazi propuseram um modelo estocástico para a evolução de espécies. Nesse modelo, as intensidades de nascimentos de novas espécies e de ocorrências de extinções são invariantes ao longo do tempo. Ademais, no instante de nascimento de uma nova espécie, a mesma é rotulada com um número aleatório gerado de uma distribuição absolutamente contínua. Toda vez que ocorre uma extinção, apenas uma espécie morre - a com o menor número vinculado. Quando a intensidade com que surgem novas espécies é maior que a com que ocorrem extinções, existe um valor crítico f_c tal que todas as espécies rotuladas com números menores que f_c morrerão quase certamente depois de um tempo aleatório finito, e as rotuladas com números maiores que f_c terão probabilidades positivas de se tornarem perpétuas. No entanto, espécies menos aptas continuam a aparecer durante o processo evolutivo e não há a garantia do surgimento de uma espécie imortal. Consideramos um caso particular do modelo de Guiol, Machado e Schinazi e abordamos estes dois últimos pontos. Caracterizamos o processo pontual limite vinculado às espécies na fase subcrítica do modelo e discorremos sobre a existência de espécies imortais.
Recently, Guiol, Machado and Schinazi proposed a stochastic model for species evolution. In this model, births and deaths of species occur with intensities invariant over time. Moreover, at the time of birth of a new species, it is labeled with a random number sampled from an absolutely continuous distribution. Each time there is an extinction event, exactly one existing species disappears: that with the smallest number. When the birth rate is greater than the extinction rate, there is a critical value f_c such that all species that come with number less than f_c will almost certainly die after a finite random time, and those with numbers higher than f_c survive forever with positive probability. However, less suitable species continue to appear during the evolutionary process and there is no guarantee the emergence of an immortal species. We consider a particular case of Guiol, Machado and Schinazi model and approach these last two points. We characterize the limit point process linked to species in the subcritical phase of the model and discuss the existence of immortal species.

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Frencl, Victor Baptista 1983. "Técnicas de filtragem utilizando processos com saltos markovianos aplicados ao rastreamento de alvos móveis". [s.n.], 2010. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260016.

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Orientadores: João Bosco Ribeiro do Val, Rafael Santos Mendes
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação
Made available in DSpace on 2018-08-16T00:17:25Z (GMT). No. of bitstreams: 1 Frencl_VictorBaptista_M.pdf: 1147363 bytes, checksum: 3933c461f1a19d86a46afeaba7057140 (MD5) Previous issue date: 2010
Resumo: Esta dissertação possui como tema o estudo do problema de rastreamento de alvos manobrantes a partir da modelagem de sistemas dinâmicos com utilização da teoria de saltos markovianos nas transições entre modelos, da utilização de filtros estocásticos recursivos e de técnicas de filtragem. Foram feitos estudos e análises de dois tipos de modelos dinâmicos, o de velocidade constante e o de giro constante. Baseados nestes modelos, elaboraram-se algumas variações em cima destes. Também foram estudados modelos de observações, propondo a inclusão da velocidade radial nas observações do alvo. Os filtros estudados foram o filtro de Kalman estendido, que lida com modelos matemáticos não-lineares, e filtro BLUE, que trata de dinâmicas lineares e modelos de observações que envolvam conversões de coordenadas. As técnicas de filtragem de modelos múltiplos interagentes, que envolve chaveamento entre filtros, e de filtro de partículas, que baseia-se em simulações de Monte Carlo, foram estudados, propondo algumas variações destas técnicas. Foi desenvolvida uma metodologia, através de simulações numéricas no software MATLAB, para comparar desempenhos das propostas de técnicas de filtragem baseadas nestes estudos
Abstract: The dissertation's theme is the study of the maneuvering target tracking problem from dynamic systems modeling using markovian jumps on the transitions between models, recursive stochastic filters and filtering techniques. Surveys and analysis of two types of dynamic models were made: the constant velocity model and the constant turn model. Based on these models, some variations were prepared. Observations models were also studied, proposing the inclusion of the radial velocity in the target observations. The studied filters were the extended Kalman filter, which deals with nonlinear mathematical models, and the BLUE filter, which deals with linear dynamics and observations models which envolves coordinates conversions. The filtering techniques of the interacting multiple models, which involves the switching between models, and the particle filter, which is based on Monte Carlo simulations, were studied, proposing some variation of these techniques. We developed a methodology, using numerical simulations on MATLAB software, to compare performances of some of the filtering techniques based on these studies
Mestrado
Automação
Mestre em Engenharia Elétrica

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Campos, Antonio Marcos Ferraz de. "Modelo para avaliação preditiva de desempenho de processos e aplicação para linhas digitais de dados". [s.n.], 2003. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259661.

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Orientador: Oseas Valente de Avilez Filho
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
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Książki na temat "Modern processors"

H, Lipasti Mikko, red. Modern processor design: Fundamentals of superscalar processors. Boston: McGraw-Hill, 2005.

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Wagner, Ilya, i Valeria Bertacco. Post-Silicon and Runtime Verification for Modern Processors. Boston, MA: Springer US, 2011. http://dx.doi.org/10.1007/978-1-4419-8034-2.

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Koç, Muammer, i Tuğrul Özel, red. Modern Manufacturing Processes. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2019. http://dx.doi.org/10.1002/9781119120384.

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Modern manufacturing processes. Belmont, Ca: Delmar Publishers, 1991.

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Goetsch, David L. Modern manufacturing processes. New York: Delmar Publishers, 1991.

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Modern manufacturing processes. Albany, NY: Delmar Publishers, 1991.

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Modern manufacturing processes. New York, N.Y: Industrial Press, 1991.

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1939-, Athreya Krishna B., i Jagers Peter 1941-, red. Classical and modern branching processes. New York: Springer, 1997.

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B, Draper Alan, i Wysk Richard A. 1948-, red. Modern manufacturing process engineering. New York: McGraw-Hill, 1990.

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B, Draper Alan, i Wysk Richard A. 1948-, red. Modern manufacturing process engineering. New York: McGraw-Hill, 1989.

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Części książek na temat "Modern processors"

Lu, Priscilla M., Don E. Blahut i Kevin S. Grant. "Architecture of Modern VLSI Processors". W The Kluwer International Series in Engineering and Computer Science, 381–406. Boston, MA: Springer US, 1987. http://dx.doi.org/10.1007/978-1-4613-1985-6_13.

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Haj-Yahya, Jawad, Avi Mendelson, Yosi Ben Asher i Anupam Chattopadhyay. "Power Management of Modern Processors". W Energy Efficient High Performance Processors, 1–55. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8554-3_1.

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Haj-Yahya, Jawad, Avi Mendelson, Yosi Ben Asher i Anupam Chattopadhyay. "Static Power Modeling for Modern Processor". W Energy Efficient High Performance Processors, 135–65. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8554-3_5.

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Wagner, Ilya, i Valeria Bertacco. "Verification of a Modern Processor". W Post-Silicon and Runtime Verification for Modern Processors, 3–12. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-8034-2_1.

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Aly, Hassan, i Mohammed ElGayyar. "Attacking AES Using Bernstein’s Attack on Modern Processors". W Progress in Cryptology – AFRICACRYPT 2013, 127–39. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-38553-7_7.

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Sato, Shigeyuki, Wei Hao i Kiminori Matsuzaki. "Parallelization of XPath Queries Using Modern XQuery Processors". W Communications in Computer and Information Science, 54–62. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-00063-9_7.

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Deng, Yangdong, Yuhao Zhu i Wang Bo. "Asynchronous Parallel Logic Simulation on Modern Graphics Processors". W Lecture Notes in Earth System Sciences, 517–41. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-16405-7_32.

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Wagner, Ilya, i Valeria Bertacco. "Post-Silicon Verification of Multi-Core Processors". W Post-Silicon and Runtime Verification for Modern Processors, 75–93. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-8034-2_4.

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Driesen, Karel. "Measurement of Virtual Function Call Overhead on Modern Processors". W Efficient Polymorphic Calls, 69–96. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4615-1681-1_6.

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Kreutzer, Moritz, Dominik Ernst, Alan R. Bishop, Holger Fehske, Georg Hager, Kengo Nakajima i Gerhard Wellein. "Chebyshev Filter Diagonalization on Modern Manycore Processors and GPGPUs". W Lecture Notes in Computer Science, 329–49. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-92040-5_17.

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Streszczenia konferencji na temat "Modern processors"

Agten, Pieter, Raoul Strackx, Bart Jacobs i Frank Piessens. "Secure Compilation to Modern Processors". W 2012 IEEE 25th Computer Security Foundations Symposium (CSF). IEEE, 2012. http://dx.doi.org/10.1109/csf.2012.12.

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Schlegel, Benjamin, Rainer Gemulla i Wolfgang Lehner. "k-ary search on modern processors". W the Fifth International Workshop. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1565694.1565705.

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Ross, Kenneth A. "Efficient Hash Probes on Modern Processors". W 2007 IEEE 23rd International Conference on Data Engineering. IEEE, 2007. http://dx.doi.org/10.1109/icde.2007.368997.

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Noll, Stefan, Jens Teubner, Norman May i Alexander Böhm. "Analyzing memory accesses with modern processors". W SIGMOD/PODS '20: International Conference on Management of Data. New York, NY, USA: ACM, 2020. http://dx.doi.org/10.1145/3399666.3399896.

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Hemani, Rakhi, Subhasis Banerjee i Apala Guha. "On the applicability of simple cache models for modern processors". W 2016 2nd International Conference on Green High Performance Computing (ICGHPC). IEEE, 2016. http://dx.doi.org/10.1109/icghpc.2016.7508062.

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Witharana, Hasini, i Prabhat Mishra. "Speculative Load Forwarding Attack on Modern Processors". W ICCAD '22: IEEE/ACM International Conference on Computer-Aided Design. New York, NY, USA: ACM, 2022. http://dx.doi.org/10.1145/3508352.3549417.

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Lee, Kyuho. "Trends of Modern Processors for AI Acceleration". W 2021 18th International SoC Design Conference (ISOCC). IEEE, 2021. http://dx.doi.org/10.1109/isocc53507.2021.9613902.

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Valerievich, Bakulev Aleksandr, Pyurova Tatiana Anatolievna, Bakuleva Marina Alekseevna, Skvortsov Sergei Vladimirovich, Kozlov Maksim Aleksandrovich i Hrukin Vladimir Ivanovich. "Modern approaches to the development parallel programs for modern multicore processors". W 2017 6th Mediterranean Conference on Embedded Computing (MECO). IEEE, 2017. http://dx.doi.org/10.1109/meco.2017.7977232.

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Kaushik, Prakhar, i Rana Majumdar. "Timing attack analysis on AES on modern processors". W 2017 6th International Conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions) (ICRITO). IEEE, 2017. http://dx.doi.org/10.1109/icrito.2017.8342471.

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Nilsen, Kelvin D., i Bernt Rygg. "Worst-case execution time analysis on modern processors". W the ACM SIGPLAN 1995 workshop. New York, New York, USA: ACM Press, 1995. http://dx.doi.org/10.1145/216636.216650.

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Raporty organizacyjne na temat "Modern processors"

Kailas, Krishnan K., Bao Trinh i Ashok K. Agrawala. Temporal Accuracy and Modern High Performance Processors: A Case Study Using Pentium Pro. Fort Belvoir, VA: Defense Technical Information Center, październik 1998. http://dx.doi.org/10.21236/ada605280.

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Villacis, Alexis, Victor Barrera, Jeffrey Alwang, Carlos Caicedo i James Quiroz. Strategies to strengthen Ecuador's high-value cacao value chain. Inter-American Development Bank, styczeń 2022. http://dx.doi.org/10.18235/0003960.

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Since the early nineteenth century, cacao has been an important export earner for Ecuador. Today the importance of this sector remains, as Ecuador is the main producer and exporter of Fine and Flavor cacao worldwide. Motivated by the main transformations of the global food systems and the increasing demand for multidimensional credence attributes, this study examines the present state of Ecuador's cacao industry, identifies areas of opportunity, and discusses how the private and public sectors can work together to meet existing and emerging challenges. Findings are supported by interviews conducted with the principal actors in the Ecuadorian cacao industry and two case studies. The first case study focuses on how associativity can help cacao farmers producing high-quality beans to differentiate themselves and succeed in modern agri-food markets. The second case study explores the success of a local chocolate firm and its links with local cacao farmers. Findings suggest that market trends have created new business opportunities for cacao producers and chocolate processors. These opportunities are most open to firms who can personalize and differentiate their products, for example, through the use of quality certifications such as organic, fair trade, reduced carbon load, etc. More importantly, market developments are driving exporters to enhance the performance of cacao value chains in the country, but the sector requires coordination to capture reputation and credence-based demands for the local cacao.

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Соловйов, В. М., В. В. Соловйова i Д. М. Чабаненко. Динаміка параметрів α-стійкого процесу Леві для розподілів прибутковостей фінансових часових рядів. ФО-П Ткачук О. В., 2014. http://dx.doi.org/10.31812/0564/1336.

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Modem market economy of any country cannot successfully behave without the existence of the effective financial market. In the conditions of growing financial market, it is necessary to use modern risk-management methods, which take non-gaussian distributions into consideration. It is known, that financial and economic time series return’s distributions demonstrate so-called «heavy tails», which interrupts the modeling o f these processes with classical statistical methods. One o f the models, that is able to describe processes with «heavy tails», are the а -stable Levi processes. They can slightly simulate the dynamics of the asset prices, because it consists o f two components: the Brownian motion component and jump component. In the current work the usage of model parameters estimation procedure is proposed, which is based on the characteristic functions and is applied for the moving window for the purpose of financial-economic system’ s state monitoring.

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Amos, C. L. Chapter 11: Modern Sedimentary Processes. Natural Resources Canada/ESS/Scientific and Technical Publishing Services, 1990. http://dx.doi.org/10.4095/132718.

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Berger, E. L., J. C. Collins, D. E. Soper i G. Sterman. Hard diffractive processes: QCD models. Office of Scientific and Technical Information (OSTI), lipiec 1986. http://dx.doi.org/10.2172/7251803.

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Gardner, Daniel. Symbolic Processor Based Models of Neural Networks. Fort Belvoir, VA: Defense Technical Information Center, maj 1988. http://dx.doi.org/10.21236/ada200200.

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Abdel-Hameed, M. Markovian Shock Models, Deterioration Processes, Stratified Markov Processes Replacement Policies. Fort Belvoir, VA: Defense Technical Information Center, grudzień 1985. http://dx.doi.org/10.21236/ada174646.

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Collins, John W., i Kenneth D. Forbus. Building Qualitative Models of Thermodynamic Processes. Fort Belvoir, VA: Defense Technical Information Center, styczeń 2007. http://dx.doi.org/10.21236/ada465196.

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Pommersheim, James M., i James R. Clifton. Models of transport processes in concrete. Gaithersburg, MD: National Institute of Standards and Technology, 1990. http://dx.doi.org/10.6028/nist.ir.4405.

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Newell, Alan. Markovian Shock Models, Deterioration Processes, Stratified Markov Processes and Replacement Policies. Fort Belvoir, VA: Defense Technical Information Center, maj 1986. http://dx.doi.org/10.21236/ada174995.

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