Rozprawy doktorskie: „Millimeter-Wave Circuit Design”

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Song, Peter. "Millimeter-wave integrated circuit design in silicon-germanium technology for next generation radars". Thesis, Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/53450.

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In this thesis, the circuits which comprise the front-end of a millimeter-wave transmit-receive module are investigated using a state-of-the-art 90 nm SiGe BiCMOS process for use in radar remote sensing applications. In Chapter I, the motivation for a millimeter-wave radar in the context of space-based remote sensing is discussed. In addition, an overview of Silicon-germanium technology is presented, and the chapter concludes with a discussion of design challenges at millimeter-wave frequencies. In Chapter II, a brief history of radar technology is presented - the motivations leading to the development of the transmit-receive module for active electronically scanned arrays are discussed, and the critical components which reside in nearly every high-frequency transmit-receive module are introduced. In Chapter III, the design and results of a W-band single-pole, double-throw switch using SiGe p-i-n diodes are discussed. In particular, the design topology and methods used to achieve low-loss and high power handling over a wide matching bandwidth without sacrificing isolation are described. In Chapter IV, the design and results of a W-band low-noise amplifier using SiGe HBT's are discussed. The design methodologies used to achieve high gain and exceptional noise performance over a wide matching bandwidth are described. Concluding remarks and a discussion of future work are in Chapter V.

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Lauterbach, Adam Peter. "Low-cost SiGe circuits for frequency synthesis in millimeter-wave devices". Australia : Macquarie University, 2010. http://hdl.handle.net/1959.14/76626.

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"2009"
Thesis (MSc (Hons))--Macquarie University, Faculty of Science, Dept. of Physics and Engineering, 2010.
Bibliography: p. 163-166.
Introduction -- Design theory and process technology -- 15GHz oscillator implementations -- 24GHz oscillator implementation -- Frequency prescaler implementation -- MMIC fabrication and measurement -- Conclusion.
Advances in Silicon Germanium (SiGe) Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technology has caused a recent revolution in low-cost Monolithic Microwave Integrated Circuit (MMIC) design. -- This thesis presents the design, fabrication and measurement of four MMICs for frequency synthesis, manufactured in a commercially available IBM 0.18μm SiGe BiCMOS technology with ft = 60GHz. The high speed and low-cost features of SiGe Heterojunction Bipolar Transistors (HBTs) were exploited to successfully develop two single-ended injection-lockable 15GHz Voltage Controlled Oscillators (VCOs) for application in an active Ka-Band antenna beam-forming network, and a 24GHz differential cross-coupled VCO and 1/6 synchronous static frequency prescaler for emerging Ultra Wideband (UWB) automotive Short Range Radar (SRR) applications. -- On-wafer measurement techniques were used to precisely characterise the performance of each circuit and compare against expected simulation results and state-of-the-art performance reported in the literature. -- The original contributions of this thesis include the application of negative resistance theory to single-ended and differential SiGe VCO design at 15-24GHz, consideration of manufacturing process variation on 24GHz VCO and prescaler performance, implementation of a fully static multi-stage synchronous divider topology at 24GHz and the use of differential on-wafer measurement techniques. -- Finally, this thesis has llustrated the excellent practicability of SiGe BiCMOS technology in the engineering of high performance, low-cost MMICs for frequency synthesis in millimeterwave (mm-wave) devices.
Mode of access: World Wide Web.
xxii, 166 p. : ill (some col.)

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Choi, Man Soo. "Computer-aided design models for millimeter-wave suspended-substrate microstrip line". Thesis, Monterey, California : Naval Postgraduate School, 1990. http://handle.dtic.mil/100.2/ADA227259.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 1990.
Thesis Advisor(s): Atwater, H.A. Second Reader: Lee, H. M. "March 1990." Description based on signature page as viewed on August 26, 2009. DTIC Descriptor(s): Strip Transmission Lines, Computer Aided Design, Computerized Simulation, Parameters, Microwave Equipment, Radar, Full Wave Rectifiers, Transmittance, Resonant Frequency, Construction, Wave Propagation, Coefficients, Boundary Value Problems, Resonators, Circuits, Discontinuities, Ka Band, Models, Scattering, Equivalent Circuits, Frequency. Author(s) subject terms: Millimeter wave, suspended substrate, design model. Includes bibliographical references (p. 78-79). Also available online.

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Severino, Raffaele Roberto. "Design methodology for millimeter wave integrated circuits : application to SiGe BiCMOS LNAs". Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14284/document.

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Grace aux récents développements des technologies d’intégration, il est aujourd’hui possible d’envisager la réalisation de circuits et systèmes intégrés sur Silicium fonctionnant à des fréquences auparavant inatteignables. Par conséquence, depuis quelques années, on assiste à la naissance de nouvelles applications en bande millimétrique, comme la communication sans fil à haut-débit à 60GHz, les radars automobiles à 76-77 et 79-82GHz, et l’imagerie millimétrique à 94GHz.Cette thèse vise, en premier lieu, à la définition d’une méthodologie de conception des circuits intégrés en bande millimétrique. Elle est par la suite validée au travers de son application à la conception des amplificateurs faible-bruit en technologie BiCMOS SiGe. Dans ce contexte, une attention particulière a été portée au développement d’une stratégie de conception et de modélisation des inductances localisées. Plusieurs exemples d’amplificateurs faible-bruit ont été réalisés, à un ou deux étages, employant des composants inductifs localisés ou distribués, à 60, 80 et 94 GHz. Tous ces circuits présentent des caractéristiques au niveau de l’état de l’art dans le domaine, ainsi en confirmant l’exactitude de la méthodologie de conception et son efficacité sur toute la planche de fréquence considérée. En outre, la réalisation d’un récepteur intégré pour applications automobiles à 80GHz est aussi décrite comme exemple d’une possible application système, ainsi que la co-intégration d’un amplificateur faible-bruit avec une antenne patch millimétrique intégrée sur Silicium
The interest towards millimeter waves has rapidly grown up during the last few years, leading to the development of a large number of potential applications in the millimeter wave band, such as WPANs and high data rate wireless communications at 60GHz, short and long range radar at 77-79GHz, and imaging systems at 94GHz.Furthermore, the high frequency performances of silicon active devices (bipolar and CMOS) have dramatically increased featuring both fT and fmax close or even higher than 200GHz. As a consequence, modern silicon technologies can now address the demand of low-cost and high-volume production of systems and circuits operating within the millimeter wave range. Nevertheless, millimeter wave design still requires special techniques and methodologies to overcome a large number of constraints which appear along with the augmentation of the operative frequency.The aim of this thesis is to define a design methodology for integrated circuits operating at millimeter wave and to provide an experimental validation of the methodology, as exhaustive as possible, focusing on the design of low noise amplifiers (LNAs) as a case of study.Several examples of LNAs, operating at 60, 80, and 94 GHz, have been realized. All the tested circuits exhibit performances in the state of art. In particular, a good agreement between measured data and post-layout simulations has been repeatedly observed, demonstrating the exactitude of the proposed design methodology and its reliability over the entire millimeter wave spectrum. A particular attention has been addressed to the implementation of inductors as lumped devices and – in order to evaluate the benefits of the lumped design – two versions of a single-stage 80GHz LNA have been realized using, respectively, distributed transmission lines and lumped inductors. The direct comparison of these circuits has proved that the two design approaches have the same potentialities. As a matter of fact, design based on lumped inductors instead of distributed elements is to be preferred, since it has the valuable advantage of a significant reduction of the circuit dimensions.Finally, the design of an 80GHz front-end and the co-integration of a LNA with an integrated antenna are also considered, opening the way to the implementation a fully integrated receiver

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Lämmle, Benjamin [Verfasser]. "Design and Applications of Integrated Millimeter-Wave Six-Port Circuits / Benjamin Lämmle". München : Verlag Dr. Hut, 2012. http://d-nb.info/1028784112/34.

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Hwang, Seunghyun Eddy. "Characterization and design of embedded passive circuits for applications up to millimeter-wave frequency". Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/41146.

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The goal of the research in this dissertation is to develop techniques for 1) system-on-package integration of passive circuits using ultra-thin advanced polymers called RXP (Rogers experimental polymer), 2) extraction of frequency-dependent material properties up to millimeter-wave frequency, 3) development and synthesis of high-rejection filter topologies, 4) design and characterization of high performance miniaturized embedded passive circuits for microwave and millimeter-wave applications, and 5) development of via and through-silicon via (TSV) enhanced filter design method for integration in high-loss substrate. The RXP material is developed to reduce the layer-count for multi-layer configuration and adoption of advanced fabrication technologies. Frequency-dependent material properties of RXP, ceramic, and other materials have been extracted up to millimeter-wave frequency using parallel-plate resonator method. An automated extraction algorithm has been proposed to handle a large number of frequency samples efficiently. The accuracy of the extraction result has been improved by including the surface roughness effect for conductor operating at high frequency. Using extracted RXP material properties, 2.4/5 GHz WLAN bandpass filters have been designed and characterized. High-rejection bandpass filter topologies for narrow 2.4 GHz and wide 5 GHz have been proposed. The proposed topologies have been synthesized to provide design equations as well as graphical design methodologies using Z-parameters. A new capacitor design called 3D stitched capacitor has been proposed to achieve more symmetric layout by providing balanced shunt parasitics. The proposed topologies and design methodologies have been verified through the measurement of high-rejection RXP bandpass filters. Good correlation between the simulation and measurement was observed demonstrating an effective design methodology and embedding bandpass filters with good performance. Dual-band bandpass filters for WLAN applications have been implemented and measured. Instead of connecting two bandpass filter circuits, a new single bandpass filter topology has been developed with a compact size as well as high isolation between passbands. High-rejection duplexer has been designed in RXP substrate for chip-last embedded IC technology, and a novel matching circuit has been applied for the miniaturization as well. The 60 GHz V-band has special interest for wireless applications because of its high attenuation characteristics because of atmospheric oxygen. Millimeter-wave passive circuits such as bandpass filter, dual-band filter, and duplexer have been designed, and self-resonant frequency of passive components has been carefully avoided using the proposed method. For low-cost system integration, silicon interposer with through-silicon-via (TSV) technology has been studied. The filter design method for high-loss substrate has been proposed. The coupling characteristic of TSV has been investigated for obtaining good insertion loss in lossy substrates such as silicon, and TSV characteristics has been used to design bandpass and highpass filters. To demonstration of concept, bandpass filters with good insertion loss have been realized on high-loss FR4 substrate.

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Sen, Padmanava. "Estimation and optimization of layout parasitics for silicon-based millimeter-wave integrated circuits". Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/26585.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.
Committee Chair: Dr. Joy Laskar; Committee Member: Dr. Chang- Ho Lee; Committee Member: Dr. Federico Bonetto; Committee Member: Dr. John D. Cressler; Committee Member: Dr. John Papapolymerou; Committee Member: Dr. Linda S. Milor. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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Kim, Jihwan. "High performance radio-frequency and millimeter-wave front-end integrated circuits design in silicon-based technologies". Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/44704.

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Design techniques and procedures to improve performances of radio-frequency and millimeter-wave front-end integrated circuits were developed. Power amplifiers for high data-rate wireless communication applications were designed using CMOS technology employing a novel device resizing and concurrent power-combining technique to implement a multi-mode operation. Comprehensive analysis on the efficiency degradation effect of multi-input-single-output combining transformers with idle input terminals was performed. The proposed discrete resizing and power-combining technique effectively enhanced the efficiency of a linear CMOS power amplifier at back-off power levels. In addition, a novel power-combining transformer that is suitable to generate multi-watt-level output power was proposed and implemented. Employing the proposed power-combining transformer, a high-power linear CMOS power amplifier was designed. Furthermore, receiver building blocks such as a low-noise amplifier, a down-conversion mixer, and a passive balun were implemented using SiGe technology for W-band applications.

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Pepe, Domenico. "Deep sub-micron RF-CMOS design and applications of modern UWB and millimeter-wave wireless transceivers". Thesis, Bordeaux 1, 2009. http://www.theses.fr/2009BOR13815/document.

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L'activité de recherche scientifique effectuée dans le cadre de mon doctorat de sciences s'est déroulée dans le secteur de la conception de circuits intégrés radiofréquences pour des systèmes ultra-wideband (UWB) et aux ondes millimétriques, et s'est articulée comme suit: (i) circuits intégrés radiofréquences pour émetteur-récepteurbasse puissance pour réseaux locaux wireless; (ii) radar UWB complètement intégré pour la surveillance cardio-pulmonaire en technologie 90nm CMOS; (iii) amplificateurs faible bruit (LNA) à 60 GHz en technologie standard 65nm CMOS
The research activity carried out during this PhD consists on the design of radio- frequency integrated circuits, for ultra-wideband (UWB) and millimeter-wave sys- tems, and covers the following topics: (i) radio-frequency integrated circuits for low-power transceivers for wireless local networks; (ii) fully integrated UWB radar for cardio-pulmonary monitoring in 90nm CMOS technology; (iii) 60-GHz low noise amplifer (LNA) in 65nm CMOS technology

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Thompson, Dane C. "Characterization and Design of Liquid Crystal Polymer (LCP) Based Multilayer RF Components and Packages". Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10498.

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This thesis discusses the investigation and utilization of a new promising thin-film material, liquid crystal polymer (LCP), for microwave and millimeter-wave (mm-wave [>30 GHz]) components and packages. The contribution of this research is in the determination of LCP's electrical and mechanical properties as they pertain to use in radio frequency (RF) systems up to mm-wave frequencies, and in evaluating LCP as a low-cost substrate and packaging material alternative to the hermetic materials traditionally desired for microwave circuits at frequencies above a few gigahertz (GHz). A study of LCP's mm-wave material properties was performed. Resonant circuit structures were designed to find the dielectric constant and loss tangent from 2-110 GHz under both ambient and elevated temperature conditions. Several unique processes were developed for the realization of novel multilayer LCP-based RF circuits. These processes include thermocompression bonding with tight temperature control (within a few degrees Celsius), precise multilayer alignment and patterning, and LCP laser processing with three different types of lasers. A proof-of-concept design that resulted from this research was a dual-frequency dual-polarization antenna array operating at 14 and 35 GHz. Device characterization such as mechanical flexibility testing of antennas and seal testing of packages were also performed. A low-loss interconnect was developed for laser-machined system-level thin-film LCP packages. These packages were designed for and measured with both RF micro-electromechanical (MEM) switches and monolithic microwave integrated circuits (MMICs). These research findings have shown LCP to be a material with uniquely attractive properties/capabilities for vertically integrated, compact multilayer LCP circuits and modules.

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Alzahrani, Saeed A. "A Systematic Low Power, Wide Tuning Range, and Low Phase Noise mm-Wave VCO Design Methodology for 5G Applications". The Ohio State University, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1578037481545091.

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Wu, Kun-Long, i 吳坤龍. "Millimeter-wave CMOS Power Amplifier and Transceiver Circuit Design". Thesis, 2016. http://ndltd.ncl.edu.tw/handle/82389038966126220454.

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博士
國立交通大學
電信工程研究所
104
React to the demand of developing next-generation wideband communication and high-resolution radar. This thesis proposes millimeter-wave wideband power amplifier (PA), transmitter (TX), receiver (RX) which are all designed in CMOS process. Due to high network loss and low power gain of the transistor at millimeter-wave band. Designing of CMOS wideband power amplifier become a bottleneck in millimeter-wave system. This thesis explores the bandwidth and loss of n-way in-phase power combiner under different loading condition. It shows that under capacitive loading, the combiner’s electrical length can be shrunk with reaching the intended power matching impedance. Consequently, the loss of the combiner can be reduced. In 77-110GHz band, 4-way power combiner adopting capacitive loading can have 1dB loss improvement comparing to Wilkinson power combiner. To demonstrate this concept, a 4-way 77-110GHz power amplifier is designed and fabricated in 65nm CMOS process; a 8-way 77-100GHz power amplifier is designed and fabricated in 40nm CMOS process. The power amplifiers are measured on wafer. In 65nm CMOS power amplifier, with 1.2V supply voltage, the in-band power gain is large than 18dB, and 24dB at 106GHz. The output 1dB compression point (OP1dB) is around 12dBm across 77-110GHz. The maximum power added efficiency (PAE) is large than 5%. The power amplifier reach 18dBm output power under 2.5V supply voltage, while it ends up with breakdown beyond 2.6V supply voltage. While in 40nm CMOS power amplifier, with 1.8V supply voltage, the in-band power gain is large than 18dB. The saturation output power achieves 15dBm at 77GHz. The maximum PAE is 5.7%. Furthermore, in order to develop highly-integrated millimeter-wave circuit, this thesis also includes a 34-42GHz 90nm-CMOS transceiver circuit design.

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Chang, Chia-Wei, i 張家維. "Design of Millimeter-wave Reconfigurable CMOS-MEMS Front-end Circuit". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/cqm65k.

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碩士
國立中正大學
電機工程研究所
102
In this thesis, four CMOS-MEMS circuits, including two low pull-in voltage, DC-70 GHz CMOS-MEMS switches, an actuators-driven tunable capacitors, and a V-Band voltage controlled oscillator, are designed and implemented using TSMC 0.18-μm CMOS process and UMC 0.18-μm CMOS process.With parallel fishbone-like cantilever beams, the driving voltage can be effectively reduced. In switch design,the traditional T-shape contact tip can’t simultaneously contact RF ground due to the cantilever tilt. To overcome this issue, an I-shape contact tip was proposed in this work so that it can well contact the ground, thereby shortening the RF signals. To investigate the newly-released UMC 0.18-μm CMOS-MEMS process, a tunable interdigital capacitor based on the fishbone actuator has been fabricated and tested. By extracting the capacitance value, the capacitor’s characteristics as well as the process parameters can be further learned, which will be essentially useful in future design. The third circuit is V-Band voltage controlled oscillator in TSMC CMOS 0.18-μm process. The actuator-driven varactor has been employed in LC tank so that the frequency range can be further improved. The simulation result shows that the frequency can be tuned from 54.19 GHz to 55.28 GHz. Output power is better than -8.4 dBm, and phase noise is -98 dBc/Hz on 1 MHz offset. Unfortunately, the measurement results show that the actuators fabricated using TSMC process did work as expected, and this issue still needs further investigation before being resolved.

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Lin, Hao-Ting, i 林浩廷. "Design of Full-Duplex Millimeter-wave Self-interference Cancellation Circuit". Thesis, 2019. http://ndltd.ncl.edu.tw/handle/h97x82.

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碩士
國立交通大學
電子研究所
107
As the evolution of 5th generation mobile network, the techniques of phased array beamforming and full-duplexing are critical to fulfill high-speed wireless transmission in millimeter-wave. In this thesis, a proposed 5-bit switched-type phase shifter and full-duplexer receiver front end with self-interference canceller are implemented in TSMC 90 nm process. The architecture of a high order pi-type low-pass filter with switches is adopted for miniaturizing design of phase shifter. The measurement results show the return loss above 10 dB, the rms phase error of 8.2 degree, and the insertion loss of 13 to 23 dB at the operating frequency of 36 GHz. To identify the signal between transmitter and receiver of full-duplex system, an electrical balanced transformer is proposed which can handle the common-mode and differential-mode signal. Additional active self-interference canceller is designed for further suppressing the leakage signal. From the simulation, the isolation is improved from 32 dB to 56 dB at 39 GHz. For system integration, wire-bonding transition is designed for interconnect between the chip and carrier with well impedance matching and low loss characteristic.

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Yang, Yi-Tzu, i 楊宜澤. "UWB and millimeter wave voltage control oscillator circuit design and fabricateon". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/48577768409141293854.

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碩士
長庚大學
電子工程研究所
95
This thesis discusses the VCO for UWB and Ka band by utilizing TSMC RF CMOS 0.18um process. We proposed the analysis of design and fabrication. There are six Chapters in my thesis and illustrate as follow: Chapter1 We illustrate the research motion and the introduction of this thesis . Chapter2 To introduce the architecture of the VCO and the consideration that to design circuits of the RF. Chapter3 To introduce and define the analysis of the active inductor which in CMOS VCO. Chapter4 To introduce and define the analysis of the differential Colpitts oscillator. Chapter5 To introduce and define the analysis of the Ka band oscillator which in complementary Colpitts oscillator. Chapter6 Finally , a brief conclusion and future work are given here.

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Chu, Kun-Da, i 褚坤達. "CMOS Millimeter Wave Circuit Design Techniques for W-band Receiver Front-End". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/18954700401113395210.

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碩士
國立臺灣大學
電子工程學研究所
96
New sensor technology enables the generation of passive millimeter-wave (PMMW) imaging at video-rate, which has the ability to form images in low-visibility condition such as haze, fog, clouds, or smoke. In recent years, many critical circuits operated at W-band have been fabricated in CMOS technology to demonstrate the potential of CMOS circuits at W-band. For the demand of low cost, low power and high integration, this thesis presents the V-band and W -band LNAs and W-band receiver in 0.13-μm and 65-nm CMOS technologies. A V-band LNA is fabricated in a 0.13-μm CMOS technology. This LNA employs gm-boosted and current reused techniques to achieve better noise performance and lower power consumption under the same gain requirement. The measured peak voltage gain is 20.4dB at 54GHz excluding the loss of balun and open-drain stage. The measured average noise figure is 9dB with a minimum of 7dB at 59GHz. The IIP3 is –15dBm while the core area of LNA is 0.4 x 0.37 mm2 and consumes 7.2mW with supply voltage of 1.2V. Using the same current reused technique, the W-bandLNA is designed in a 65-nm CMOS technology. The measured S21 is 11dB at 103GHz with 10dB noise figure. The IIP3 is about –14dBm while the area is 0.17 x 0.38 mm2 and consumes 25mW with 1.5V supply. The W-band receiver is designed in CMOS 65-nm technology with 1V supply. This highly integrated receiver, which employs the heterodyne architecture, provides the function of PMMW imaging and data communication. The proposed frequency doubler using an injection-locked oscillator operated at the voltage-limited region can reduce the complexity of frequency synthesizer. The simulated maximum conversion gain is 42dB at 102GHz with bandwidth of 4GHz and noise figure of 12.2dB. The IIP3 is about -26dBm while the area is 0.95 x 0.8 mm2 and consumes 110mW.

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Lin, Yu-Chih, i 林宇志. "Design of Microwave and Millimeter Wave Integrated Circuit Packages Using 3D Technology". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/85601955381763582894.

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碩士
國立中山大學
通訊工程研究所
100
There are three parts in this thesis: In the first part (Chapter 2), we discuss the port excitation (Wave port vs Lumped port) suitable for sub-millimeter wave operations. We realized on printed circuit board a grounded coplanar waveguide (CPWG) and on gallium arsenic (GaAs) a microstrip line. We performed simulation on these structures using high frequency structure simulator (HFSS), and compared the results with measured ones. From the comparison, we found close match for CPWG insertion loss from 10 MHz to 67 GHz using the Wave port. However, for G-S-G lumped port, only matched up to 40 GHz. The wave port not only was more accurate, but also consumed less time in simulation. Consequently, we employed wave port as our simulation excitation for our sub-millimeter wave QFN design. In the second part (Chapter 3), we focused on design of low cost QFN for sub-millimeter wave applications. We fabricated test structures, which include IC pads and transmission lines, wire bonds, QFN leads, and G-S-G structures on printed circuit board. In HFSS simulation, our specially designed ribbon bonds and QFN configuration show return loss less than -20dB and insertion loss less than -0.4 dB up to 60 GHz. Using the same design principles, we strived to improve the performance of a commercially available QFN, which normally operates at 3 to 6 GHz. The extraction method to obtain the high frequency characteristics was introduced first, and the characteristics of a commercially available QFN (with our wire bond configuration) were then obtained. The insertion loss was less than -20 dB and insertion loss less than -0.5 dB up to 20 GHz. In Chapter 5, we discuss the performance discrepancies between the simulated ribbon bond results and that for fabricated wire bonds. In the third part (Chapter 4), we introduced a method to extract the characteristics of a single backside via and investigated the effects of die attachment on the performance of a single and multiple backside via(s). Using silver epoxy and Cu blank layer as die attach methods, we found it was important to provide a broad path (Cu blank layer), as opposed to a restrict path (like silver epoxy) to reduce the inductance of the backside vias. The conclusion and future work are provided in Chapter 5.

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Hsieh, Yi-Chun, i 謝宜君. "Design and Analysis of Circuit Blocks in Millimeter-Wave Phase-Locked Loop". Thesis, 2018. http://ndltd.ncl.edu.tw/handle/t2arg2.

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Su, Jen-Yi, i 蘇珍儀. "Millimeter-Wave HEMT Transceiver With Analog Circuit Design Approach and Flip-Chip Technology". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/97557622070013790980.

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博士
國立交通大學
電信工程系所
97
In this dissertation, all analog integrated circuits and monolithic microwave integrated circuits (MMICs) are demonstrated using 0.15-�慆 pseudomorphic high electron mobility transistor (pHEMT) and metamorphic high electron mobility transistor (mHEMT) technologies. These GaAs-based technologies have the advantages of a high breakdown voltage, cutoff frequency, low noise figure, higher output power, and semi-insulating substrate. Furthermore, a package technique is an important key for high-frequency circuits. The flip-chip technique is demonstrated that the performances of V-band amplifiers with and without flip-chip are almost the same. In Chapter 2, three kinds of Ka/Ku-band Gilbert mixers are demonstrated using pHEMT technology. Thanks to the semi-insulating GaAs substrate, microwave passive components have a low-loss feature, and polyphase filters work up to higher frequencies. Highly accurate Tantalum Nitride (TaN) thin film resistors utilized in polyphase filters result in perfect quadrature operation. Therefore, our proposed single-sideband up-converter operates at 15 GHz with a 63-dB sideband rejection ratio, and another 34-GHz I/Q subharmonic down-converter reaches < 0.4-dB magnitude and < 1° phase errors. More than 50-dB LO leakage suppression is achieved in the I/Q subharmonic mixer. On the other hand, a 40-GHz stacked-LO subharmonic mixer with a novel compensation technique is also proposed and demonstrated to improve LO speed and reduce the amount of transistors as compared to the previous work. Chapter 3 makes a comparison between Q-band 0.15 μm pHEMT and mHEMT stacked-LO subharmonic upconversion mixers in terms of gain, isolation and linearity. In general, a 0.15 μm mHEMT device has a higher transconductance and cutoff frequency than a 0.15 μm pHEMT does. Thus, the conversion gain of the mHEMT is higher than that of the pHEMT in the active Gilbert mixer design. The Q-band stacked-LO subharmonic upconversion mixers using the pHEMT and mHEMT technologies have conversion gain of -7.1 dB and -0.2 dB, respectively. The pHEMT upconversion mixer has an OIP3 of -12 dBm and an OP1dB of -24 dBm, while the mHEMT one shows a 4 dB improvement on linearity for the difference between the OIP3 and OP1dB. In Chapter 4, the V-band coplanar waveguide (CPW)-microstrip line (MS)-CPW two-stage amplifier with the flip-chip bonding technique is demonstrated. The CPW is used at input and output ports for flip-chip assemblies and the MS transmission line is employed in the interstage to reduce chip size. This two-stage amplifier employs transistors as the CPW-MS transition and the MS-CPW transition in the first stage and the second stage, respectively. The CPW-MS-CPW two-stage amplifier has a gain of 14.8 dB, input return loss of 10 dB and output return loss of 22 dB at 53.5 GHz. After the flip-chip bonding, the measured performances have almost the same value. A 60 GHz single-chip receiver MMIC using 0.15-μm mHEMT technology is demonstrated in Chapter 5. The receiver consists of an LO multiplier chain, a 60 GHz three-stage low noise amplifier, and 60 GHz image rejection diode mixer. The LO chain is formed with a tripler and a 28 GHz three-stage feedback amplifier. Furthermore, the 60 GHz image rejection mixer is a symmetrical subharmonic diode mixer and integrated with IF and 3 × LO quadrature hybrids. The mHEMT receiver has the conversion gain of 4 dB, the noise figure of 7.0 dB, and the image rejection ratio of 22 dB at 60 GHz. The -24 dBm IP1dB and -16 dBm IIP3 are measured. Chapter 6 reports a Ka-band quadrature-output divide-by-two Miller divider using the 0.15-μm pHEMT technology. The circuit topology consists of one Marchand balun, two active multipliers and LC-tank filters with a positive feedback loop. The divider includes a single side-band (SSB) up-converter to verify the quadrature accuracy of the divider’s outputs. A 35-dB side-band rejection ratio is achieved. The minimum input sensitivity equals 2.7 dBm. The stable division from 32 to 36 GHz in a bandwidth of 12 % can be obtained.

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20

Yeh, Jin-Fu, i 葉景富. "Research on 24-GHz RF Front-End CMOS RFICs and Millimeter-Wave Circuit Design". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/96719357851488666787.

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碩士
國立成功大學
電腦與通信工程研究所
97
This thesis presents the research on 24-GHz CMOS RFICs and millimeter-wave circuit design for short-range vehicular collision-avoidance radar application. The RFICs are fabricated with TSMC 0.18 μm 1P6M standard and TSMC RF CMOS 0.13μm process. Agilent ADS is used to integrate the co-simulation design. A 24-GHz single-in differential-out (SIDO) CMOS low-noise amplifier (LNA) integrated a trifilar transformer is designed. The trifilar transformer in the SIDO LNA can achieve a good balanced characteristics, inter-stage matching and reduction of the bias-circuits. The designed 24-GHz double-balance dual-gate CMOS mixer uses a multi-bias technique to enhance the linearity.

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21

Liou, Jie-Kang, i 劉介剛. "Design and Measurement of Millimeter-Wave Contactless Transition between Active Chip and Printed-Circuit Board". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/a94r78.

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碩士
國立交通大學
電信工程研究所
103
In this thesis, two circuits are designed for 77GHz automotive radar system; one is a novel contactless transition of the chip to the printed circuit board and the other is an integration of low noise amplifier (LNA) and resonator in TN90GUTM CMOS technology. LNA is used as the validation of the first transition. The contactless transition of the chip to the printed circuit board is designed. With the theory of the resonator and filter, half-wavelength resonators are designed on the chip and printed circuit broad (PCB), and then the signal on the chip can be transmitted to the PCB via a low loss coupling mechanism. In addition, I consider the high frequency measurement, tolerance, measurement environment and implement results, and then summarize various methods of high-frequency measurement. The other circuit is a low noise amplifier (LNA) integrated with a coupled resonator on the chip. A low noise amplifier is using inductive degeneration architecture in cascade. This architecture provides the high gain, low noise figure and good isolation.

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22

Lin, Guan-Wei, i 林冠瑋. "Design of Millimeter-wave Front-end Circuit With TSMC & UMC 0.18 μm CMOS-MEMS Process". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/8362xy.

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碩士
國立中正大學
電機工程研究所
103
This thesis presents the design of three millimeter-wave front-end circuits using TSMC 0.18 μm and UMC 0.18 μm CMOS-MEMS technologies, including a broadside coupler-based reflection-type phase shifter with continuous-phase-tuning mechanism, a DC-70 GHz CMOS-MEMS SPST switch with low operating voltage, and an active-circulator-based reflection-type phase shifter. The broadside coupler-based reflection-type phase shifter with continuous-phase-tuning mechanism is implemented in TSMC 0.18 μm CMOS-MEMS process. In this design, the number of switching states is increased, leading to larger achievable phase tuning range. With 47-volt actuation voltage, the simulation result shows that the ~134°phase tuning range can be achieved while the insertion loss is 4.3 0.5dB at 70-GHz. The second circuit is a DC-70 GHz CMOS-MEMS SPST switch, which is implemented in both UMC and TSMC 0.18 μm CMOS-MEMS process. The electrical-driven actuator was carefully designed to reduce the operating voltage down to 12 V. The measurement result shows that the insertion loss is less than 0.4 dB in ON-state, but the isolation is not good in OFF-state due to the unexpected silicon oxide accumulation. The last one is an active-circulator-based reflection-type phase shifter. The active quasi-circulator is constructed by CMOS transistors, while the MEMS-driven capacitance is adopted as reflective load. It is implemented in TSMC 0.18 μm CMOS-MEMS process. The Simulation result shows that the phase tuning range is 102° under a 35-volt supply voltage at 24-GHz.

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23

曾柏森. "Design of millimeter-wave mixer circuits". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/50456307430526940298.

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Yen, Hsuan-Der, i 顏玄德. "Design and Reliability Studies of CMOS RF/Millimeter Wave Circuits". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/07041216896163084152.

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博士
國立清華大學
電子工程研究所
102
For this dissertation, the radio frequency (RF) and millimeter wave circuits of transceivers were considered in order to analyze reliability issues with regard to the complementary-metal–oxide–semiconductor (CMOS) process. Three circuits were considered: a power amplifier (PA), voltage control oscillator (VCO), and mixer. In a stress experiment, the operation voltage was varied for the stress source, and the degradation of the circuit was monitored to analyze phenomena that degraded the device and circuit performance. The stress source conditions were controlled by the input power and voltage of instruments that were biased towards the gate and drain of the CMOS device on the circuits. In reliability experiments, acceptable values for the stress source were applied to the circuits to induce long-term stress. In the PA circuit topology, stage 1 was a driver stage, and stage 2 was a cascode structure. The circuit operation frequency was 5.2 GHz for a TSMC CMOS 0.18 µm 1P6M process. A cascode class-E PA was designed for fabrication because the amplifier was operated under high input power conditions. The input power, gain, gate–source voltages, and drain–source voltages had large values when switching during the transient state. Thus, the cascode transistor could suffer from the hot-electron effect and the degradation of the circuit performance. The experimental results were compared with those of a technology computer-aided design (TCAD) simulation to examine the reasons for the degradation of the circuit performance. The design and reliability of a CMOS current-reuse LC-loaded VCO based on the TSMC CMOS 0.18 µm 1P6M process were considered. The circuit comprised an n-channel MOS and p-channel MOS cross pair with a single current path oscillator structure, which allowed it to have low power consumption. The varactor component of the LC resonator was designed with a P-MOS device having low noise characteristics. The operation frequency was determined by the LC resonator, and a suitable VDD voltage led to low power consumption and low phase noise for the VCO. The negative-bias temperature instability (NBTI) affected the current for the reused VCO, which consisted of p-channel transistors. Previous studies had not examined the circuit topology experimentally, which provided motivation for this dissertation. Hot carrier issues for the degradation of the phase noise, transconductor, and threshold were considered. Finally, a millimeter wave mixer was considered for the TSMC CMOS 65 nm 1P6M process at conversion gains of larger than -5 dB. The coverage frequency was from 64 GHz to 75 GHz, and the maximum conversion gain was -0.96 dB. Two built-in Marchand baluns were used to convert the LO and RF port from single to differential. This can simplify the external passive parts and instruments used for the millimeter-wave band. The IF port provided excellent performance characteristic for the external passive parts and instruments. The IF port retained differential characteristics, which can be advantageous for circuit measurement during experiments. In this experiment, the mixer was operated at millimeter wave frequency range. Long-term and dynamic stresses on the n-channel metal–oxide–semiconductor field-effect transistor (MOSFET) device resulted in the hot carrier effect, which degraded the mixer performance. This increased the threshold voltage and gate leakage current and decreased the drain current. A stress measurement experiment was performed under different stress conditions for the n-channel MOSFET. The results showed how mechanisms such as a hot carrier and high electric field influenced the device characteristics under long-term stress.

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25

Chen, Shih-Yu, i 陳詩喻. "Power Amplifier Nonlinearity Analysisand Millimeter-wave Sub-harmonically PumpedMixer Circuit Designs". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/90118322446111674000.

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碩士
國立臺灣大學
電信工程學研究所
94
Due to interests in Multi-media services and personal wireless communication systems, fast and wideband data transmission is getting demanded than ever before. However, frequency band is getting crowded as well. To utilize the limited bandwidth effectively, modern digital communication systems tend to use complex digital modulation schemes which have stringent linearity specifications for the transceivers. Power amplifier nonlinearity analysis and Millimeter-wave nonlinear circuit design and are the main research point of this thesis. We present an analytical expression to show correlation between the IM3R and the ACPR for W-CDMA signal based on PDF observation. The calculable constant correlation applies to all kinds of amplifiers and applies to distorted region above P1dB as long as the IM5R is 10dB lower than IM3R. For up-link W-CDMA, the constant correlation Co is fixed at 8 dB, while the constant Co is fixed at 2 dB for down-link W-CDMA. Besides W-CDMA, PDF influence other kinds of signals. For QPSK signal, the constant Co is 6 dB, while the constant Co is 4 dB for 16-QAM, 64-QAM and 128-QAM signals. After all the discussion and derivation for signals at microwave frequency, we apply our expression to millimeter-wave frequency band. The measured results show all the constant correlation for different modulated signals hold even if the carrier frequency is at millimeter-wave frequency, and our prediction of ACPR by IM3R measurements achieves. To conclude all the measurement and calculation, the value of constant Co does not vary with circuits, carrier frequency and channel bandwidth of signals, but does vary with modulation types of signal of different PDF. On the other hand, for circuit designs, a 38-48-GHz miniature sub-harmonically pumped diode mixer with low LO input power is presented. Quasi-lumped matching topology is employed to minimize the chip size which is 0.72mm2. Additionally, a miniature Q-band monolithic subharmonically pumped resistive mixer was developed. The compact RF/IF diplex circuit and a reduced-size balun were used to minimize the chip size which results 0.72 mm2 as well. From the measurement results, the resistive mixer has the same conversion loss as the diode mixer, but has better linearity characteristics than the diode mixer.

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26

Hung, Ruei-Yun, i 洪芮妘. "Design of Microwave and Millimeter-wave Phase Array Transceiver Integrated Circuits". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/52225946835455553960.

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碩士
國立中央大學
電機工程研究所
97
In this thesis, the microwave and millimeter-wave (MMW) phase array transceiver integrated circuits are presented. First, the design of a slot antenna and a voltage controlled oscillator are proposed using a MMIC technology. The substrate loss is more and more high when the operation frequency is high. To enhance the radiation efficiency of the MMW transmitter, an antenna can be further integrated in the MMIC chip, and also the chip size and the loss are both reduced. Second, a 24-GHz amplifier by using a third-order transconductance (gm3) cancellation technique is presented. The linearity effect of the CMOS device is generally degraded by the gm3 and the gate-to-source capacitor. The characteristic of the gm3 can be adjusted by appling a dc bias to the bulk of the device. The cancellation of gm3 can be achived combining a negative peak gm3 transistor in parallel with a positive peak gm3 transistor. The measured input third-order intercept point (IIP3) is improved over 6 dB. Therefore, the distortion and the communication quality can be both improved. Finally, a phase array receiver, including a low noise amplifier and an IQ modulator, is proposed for the MMW applications. The phase can be controlled by adjusting the bias of the IQ modulator. The topology of the 2×1 receiver can be further extended to 4×1 or 8×1 phase array receiver with a Wilkinson power combiner.

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27

Pan, Hou-Ru, i 潘厚儒. "Design of Millimeter-Wave Concurrent Dual-Band Transceiver Front-End Circuits". Thesis, 2018. http://ndltd.ncl.edu.tw/handle/z352q7.

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林繼揚. "Design of 77 GHz Millimeter-Wave Integrated Circuits for Anticollison Radar Applications". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/62376881671513758166.

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碩士
國立臺灣師範大學
應用電子科技研究所
100
The subject is design of 77 GHz millimeter-wave integrated circuits for Anticollison radar applications. The presented low noise amplifier, power amplifier, down/up-conversion ring mixers are designed and fabricated on TSMC 90 nm 1P9M CMOS process. The Contents divide into two parts. The first part is the background of Millimeter-wave auticollision radar. The second part is simulation and measurement data. The paper presents three circuits. One is low noise amplifier. The LNA utilizes three-stage configuration amplifier. The first stage is common source due to small low noise figure. The second and third stages are cascade because of the high gain. The low noise amplifier is simulated at 71-77 GHz. Noise figure is 6.17 dB at frequency 74 GHz. The gain is 20 dB. The chip size is 0.596 ╳ 0.583 mm2. The second is power amplifier . the amplifier utilizes three-stage configuration and large size transistors to design. the result of gain measurement is 20 dB. The chip size is 0.596 ╳ 0.596 mm2. the final part is down/up-conversion ring mixers. The OP1dB of down-conversion mixer is -0.5 dBm @ -3 dBm.

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29

Chen, Pang-Ning, i 陳邦寧. "Design of Wireless Front-End Circuits for Microwave and Millimeter-Wave Applications". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/09328199175217858688.

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碩士
國立臺灣大學
電機工程學研究所
99
Millimeter-wave front-end circuits including power amplifier, low-noise amplifier, mixer, and active power splitter are demonstrated in 24-GHz, 60-GHz and 87-GHz bands in this Thesis. With different considerations for each application, the front-ends are designed and integrated to be FMCW radar, OOK transceiver, QPSK transceiver respectively. The 24-GHz power amplifier reveals a Psat of 14.6 dBm with maximum PAE of 17 % while consuming 162 mW under 1.2-V supply. The low-noise amplifier provides power gain of 18 dB and 2.5 dB noise figure at 24 GHz. The 60-GHz power amplifier reveals a Psat of 11.2 dBm with PAE of 21 % while consuming 50 mW under 1.0-V supply. This PA also provides P1dB of 7 dBm and PAE1dB of 10 % in 1 dB gain compression. The transformer-based power amplifier reveals a Psat of 13.7 dBm with maximum PAE of 23 % while consuming 85 mW under 1.0 V supply. The active power splitter also provides a power gain of 8.4 dB and P1dB of 0 dBm. The 87-GHz power amplifier presents a Psat of 10.2 dBm with PAE of 8.0 % while consuming 115 mW under 1.2-V supply　and low-noise amplifier provides gain of 19 dB and noise figure of 6.9 dB. Under system level, the 24-GHz FMCW radar system is capable of detecting multiple objects and exhibiting their positions and relative speeds in real time within 200 meters. The 60-GHz OOK transceiver achieves 2-m communication distance with 1.5-Gb

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30

Shih-Yu, Chen. "Power Amplifier Nonlinearity Analysis and Millimeter-wave Sub-harmonically Pumped Mixer Circuit Designs". 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2307200619221900.

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31

Wang, Chao-Shiun, i 王照勳. "CMOS Millimeter-Wave Circuits and Architecture Design Techniques for High Date Rate Receiver". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/40409668674990742741.

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博士
國立臺灣大學
電子工程學研究所
99
Recently, the interest in millimeter-wave radio links has increased. This is caused by application that needs wireless radio links with high data rates. By using today''s advanced CMOS technologies, it allows relatively cheap implementations for such radio links. The short wavelength of the millimeter-wave signals suffer from the serious attenuation in the atmosphere and multi-path channels, which hinders the wireless communication from achieving high SNR performance required by high throughput system specifications. This puts special requirements on system design, architecture and circuits. This dissertation investigated circuit design techniques operating at the millimeter-wave frequency using advanced 65nm, 90nm and 130nm CMOS technologies. The goal of the research is to realize high-speed, low-power, and compact integrated wireless communication key blocks operating at 60 GHz frequency. The various current-reused and noise cancelling LNA circuits and receiver building blocks toward the realization of the low power and low noise millimeter-wave systems are presented in this dissertation. On the system side, a fully integrated dual-antenna phased-array RF front-end receiver including the active phase shifter has been demonstrated. A less complex analog FSK demodulator using an injection-locked technique to achieve a gigabit data rate without suffering from process variation is also exhibited. The proposed dual-antenna phased-array RF front-end receiver was designed and fabricated in a 0.13um RF CMOS process. In order to obtain good common-mode noise rejection, the receiver front-end employs fully differential architecture. The proposed gm-boosted current-reuse LNA circuit mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down conversion mixer alleviates the problem of the third harmonic of the LO as well. An active all-pass filter is employed to adjust the phase shift of each LO signal. This architecture exhibits a measured SNR improvement of 4.5 dB with an overall measured gain of 34.5 dB. Overall chip power consumption is 93mW. The proposed injection-locked high data-rate FSK/MSK demodulator is fabricated in a 0.13um CMOS RF technology. Compared with the conventional LC tank discriminator, the injection-locked oscillator provides a process insensitive frequency-to-phase transformation for analog non-coherent FSK/MSK demodulation. The measured demodulation input sensitivity is -12dBm at BER less than 10^-9 for uncoded 2.5Gbps 2^31-1 PRBS data with 0.5 modulation index. The whole chip consumes 20mW from a 1.2V supply voltage, where the FSK/MSK demodulator core circuit only consumes 6mW.

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32

Chiu, Ching-Hung, i 邱景鴻. "Design and Implementation of RF Receiver Front-end Integrated Circuits for Millimeter-wave Applications". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/fbv6fw.

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碩士
國立中央大學
電機工程研究所
94
The thesis investigates the design and implementation of RF receiver front-end circuits, such as low noise amplifier, mixer, and voltage-controlled oscillator. A K-band variable-gain low noise amplifier (VGLNA) is designed and implemented using TSMC 0.18-μm CMOS technology. Coplanar waveguide (CPW) transmission lines are adopted as matching elements to reduce the effect of lossy silicon substrate at high frequency. In high-gain mode, the measured small signal gain of VGLNA is 8.1 dB and noise figure of 6 dB at 21.7 GHz. The gain control range of the VGLNA is 7.2 dB. A 3-34 GHz distributed drain mixer using CPW technology is demonstrated in this thesis. This MMIC mixer uses a simple distributed topology that is composed of common-source single-gate 0.15-μm PHEMT, and it shows a conversion loss of better than 6.7 dB from 3 to 34 GHz. This distributed mixer achieves low dc power consumption and high linearity for broadband applications. Afterward, the 26-GHz PMOS cross-coupled push-push VCO using 0.18-μm CMOS technology is design for low phase noise and wide tuning range. The PMOS-only cross-coupled pair is used to lower the phase noise, and the measured 2nd harmonic phase noise is -102.86 dBc/Hz at 1-MHz offset. The push-push VCO achieves a wide tuning range of 14%. Another 50-GHz push-push VCO uses 0.15-μm PHEMTs technology and the λg/2 microstrip line resonator to form a common resonator for push-push oscillation. This type of push-push VCO has the advantages of simple configuration and good performances. From simulated results, the VCO achieves the frequency tuning range of 1.2 GHz and the phase noise of -111.8 dBc/Hz at 1-MHz offset.

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33

Cheng, Kan-Jen, i 鄭淦仁. "Design and Implementation of SVCO/MIXER and Related Passive Circuits for Millimeter-wave Applications". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/90067390610729516596.

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碩士
國立中央大學
通訊工程研究所
93
This thesis investigates millimeter-wave mixer, oscillator and theirs correlated passive circuits. The topology of mixer is resistive type with the center frequency of 28GHz. The topology of local oscillator is cross-coupled scheme and its negative resistance is designed to compensate the loss of tapped resonator with the center frequency of 43GHz. Then the signal can be taken out by standing wave mode. These active circuits are implemented with WIN 0.15μm pHEMT. The millimeter-wave resonators and filters are fabricated with Al2O3 thin film process. The λ/4 shunt and series matching stubs are intentionally placed inside the center conductor to reduce the size and insertion loss of CPW filter. The λ/2 ring resonators replace the conventional rectangular resonators to reduce the size. The measured results of millimeter-wave circuits are as follows; for the sub-harmonic mixer, conversion loss is 12 dB, input power at the 1-dB gain compression point is 9 dBm, isolations among all ports are greater than 30dB; for the standing wave voltage-controlled oscillator, the operating frequency is 43 GHz, the phase noise is -101 dBc/Hz at 1MHz offset frequency, output power is 6 dBm, tuning range is 1 GHz; for the millimeter-wave band pass filter, insertion loss is smaller than 3dB, return loss is larger than 15dB, size is reduced to 35﹪, bandwidth is 10 GHz; for the CPW shunt short stub, insertion loss is smaller than 3dB, return loss is larger than 9dB, size is reduced to 25﹪, bandwidth is 5.7 GHz; for the CPW shunt open stub, insertion loss is larger than 15dB, return loss is smaller than 1dB, size is reduced to 25﹪, bandwidth is 7 GHz;for the CPW feed ring resonator, insertion loss is larger than 15dB, return loss is smaller than 2.5dB, bandwidth is 10 GHz; for the slotline feed ring resonator, insertion loss is larger than 14dB, return loss is smaller than 2.5dB, bandwidth is 1.5 GHz.

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Chen, Min-Chiao, i 陳旻珓. "The Analysis and Design of Millimeter-Wave CMOS Circuits for 60-GHz Communication Systems". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/97842609261432245279.

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博士
國立交通大學
電子工程系所
97
In this thesis, the design methodologies and implementations of millimeter-wave CMOS circuit for 60-GHz low-power communication system are presented. There are three parts: (1) the analysis, modeling, and design of the subharmonic injection-locked frequency tripler (ILFT); (2) the analysis and design of 60-GHz phase-locked loop (PLL) integrated with injection-locked frequency multiplier (ILFM); and (3) the design of 60-GHz direct-conversion receiver integrated with ILFT. At first, K-band and V-band CMOS differential subharmonic ILFTs are proposed, analyzed, and designed. Based on the proposed ILFT structure, models for the locking range and the output phase noise are developed. A K-band ILFT is designed and fabricated using 0.18-μm CMOS technology. The measured locking range is 1092 MHz with a dc power consumption of 0.45 mW and an input power of 4 dBm. The harmonic rejection-ratios are 22.65, 30.58, 29.29, 40.35 dBc for the first, second, fourth, and fifth harmonics, respectively. The total locking range of the K-band ILFT can achieve 3915 MHz when the varactors are used and the dc power consumption is increased to 2.95 mW. A V-band ILFT is also designed and fabricated using 0.13-μm CMOS technology. The measured locking range is 1422 MHz with 1.86-mW dc power consumption and 6-dBm input power. It can be seen that the locking range of the proposed ILFT is similar to the tuning range of a conventional varactor-tuned bulk-CMOS voltage-controlled oscillator (VCO). Secondly, a novel CMOS PLL integrated with ILFM that generates the 60-GHz output signal is proposed. The proposed 60-GHz PLL is composed of VCO, ILFM, 1/32 frequency divider, phase/frequency detector, charge pump, and loop filter. Because the proposed ILFM can generate the fifth-order harmonic frequency of VCO output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. The PLL is designed and fabricated in 0.18-μm CMOS technology. The output frequency range of the proposed PLL is from 53.04 GHz to 58.0 GHz with output power of –37.85 dBm. The measured phase noises at 1 MHz and 10 MHz offset from the carrier are –85.2 and –90.9 dBc/Hz, respectively. The reference spur level of –40.16 dBc is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. The chip area including pads is 0.96 mm × 0.84 mm. Finally, a 60-GHz direct-conversion receiver integrated with ILFT is proposed. The proposed direct-conversion receiver front-end is composed of a low-noise amplifier (LNA), I/Q quadrature down-conversion mixers, a 20-GHz QVCO, two ILFTs, two IF amplifiers, and two output buffers. In the proposed receiver, the local oscillator (LO) signals are generated by QVCO operated at only one-third of carrier frequency cascade with the two ILFTs. Due to the frequency shift of QVCO, the maximum RF frequency is only 55.03 GHz. The measured results show a receiver gain of 18.2 dB, a noise figure of 16.96 dB with RF frequency of 55.03 GHz and IF frequency of 100 MHz, channel bandwidth of 2 GHz with LO frequency of 55.02 GHz, an input-referred 1-dB compression point (P1dB) of –17.0 dBm, and input third-order inter-modulation intercept point (IIP3) of –7.6 dBm. The proposed receiver is implemented using 0.13-μm CMOS technology and draws 25.84 mA from a 1.2-V supply. The total chip area, including testing pads, is only 1.21 mm × 1.03 mm. It is believed that the proposed ILFT can be used in low-power high-performance transceiver design in the millimeter-wave band. Further research for low-power single chip transceiver and frequency synthesizer can be integrated in the future.

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Hsieh, Sheng-Chi, i 謝盛祺. "Design Of Millimeter-Wave Reconfigurable Front-End Circuits Using The Standard CMOS-MEMS Technology". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/76068389371663634226.

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博士
國立中正大學
電機工程研究所
100
This dissertation describes the designs of millimeter-wave reconfigurable front-end circuits using standard CMOS-MEMS technology. To fully integrate with the readily developed CMOS transceiver into a single chip, CMOS-MEMS devices are more compatible than the traditional MEMS devices. However, the demonstrations presented in current literature are primarily focused on frequencies below 30 GHz. For that reason, the major task of this work is to investigate the optimum solutions in designing the CMOS-MEMS frond-end circuitry for V-/W-band applications. Firstly, three kinds of direct-contact MEMS switches are studied A triple-mode SPDT switch and a quadro-mode SPDT switch are designed based on electrostatic-actuated cantilevers to achieve sidewall-contact. To reach a low pull-in voltage, a SPST switch is designed with a fishbone-like actuator using numerous fingers. The static electric force can be increased owing to those fingers so that the drive voltage can be dramatically reduced. The measured pull-in voltage is only 6 V. However, the full contact can’t be achieved due to the surface roughness, leading to the performance failure in on-state. In addition, mmwave CMOS-MEMS front-ends circuitry with reconfigurability of dual/multiple-state actuators, including a bandstop filter, two filter-integrated switches and one slot antenna are presented. By varying the gap between the open-stubs and grounded-interdigital structures, the stop-band frequency of the proposed bandpass filter alters simultaneously. The measurement results show that the stop-band frequency can be switched from 60 GHz to 50 GHz with 40-V actuation voltage. The isolation is better than 38 dB at 60 GHz and 34 dB at 50 GHz, respectively. The second design is a bandpass filter-integrated SPST switch. In this circuit, the center frequencies of the resonator in the on- and off-states can be properly chosen, the reconfigurable filter can perform passband response in one state and isolation in the other state, resulting in the filter-integrated switch (FIS). The first a V-band FIS measurement results show that insertion loss and return loss better than 3.89 dB and 13.4 dB from 51-62 GHz in the on-state, and isolation better than 29 dB in the off-state with an actuation voltage of 38 V. The second FIS is designed at W-band, where the measurement results show that insertion loss and return loss better than 6.2 dB and 15 dB from 88-100 GHz in the on-state, and isolation better than 21 dB in the off-state with an actuation voltage of 51 V. Finally, a frequency-reconfigurable slot antenna is designed and fabricated using standard CMOS 0.18-m technology. The operation band is reconfigured by changing the capacitance based on comb fingers mechanical structure. By utilizing the multi-state actuators, the frequency of this antenna can be switched to 43, 47, 50.5, 54, 57.5 GHz with return loss better than 20 dB. The measurement results show that the gain is -7.9 dBi to -16 dBi from 42 GHz to 57.5 GHz. The radiation patterns are also shown along with the custom designed on-chip measurement facilities.

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36

Hsieh, Hsieh-Hung, i 謝協宏. "Design and Implementation of CMOS Millimeter-Wave Integrated Circuits near the Transistor Cutoff Frequency". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/73120472982234874695.

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博士
國立臺灣大學
電子工程學研究所
97
Due to recent advances in the fabrication technology, transistors with a cutoff frequency (fT) and a maximum oscillation frequency (fmax) beyond 100 GHz have been commercially available in a deep-submicron CMOS process, motivating RF integrated circuit designs towards higher frequencies. Unfortunately, the development of CMOS millimeter-wave circuits has been long impeded by inherent shortcomings such as parasitic components, substrate losses and inferior device capabilities. It is still a challenging task for the designer to realize CMOS circuits near the transistor cutoff frequency. In this thesis, to alleviate the frequency limitations imposed on CMOS technologies, novel circuit topologies are developed for millimeter-wave operations. In Chapter 3, a gain-enhancement technique is introduced to the low-noise amplifier (LNA) while the small-signal gain is boosted, facilitating circuit operations at higher frequency bands. In Chapter 4, based on the concept of the admittance transformation, the proposed LC-tank voltage-controlled oscillator (VCO) is capable of sustaining the fundamental oscillation at a frequency close to the fT of the transistor. In Chapter 5, by adopting a series-peaking structure, the locking range of the harmonic injection-locked frequency divider is effectively enhanced while the compact integration and reduced dc power can be exhibited since the cascaded divide-by-two stages are avoided.

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37

Chiang, Yun-Chieh, i 蔣昀潔. "Design and Analysis of Millimeter-wave CMOS Phase Shifter and Low Phase Variation Circuits". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/76380264897290714840.

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Streszczenie:

碩士
國立臺灣大學
電信工程學研究所
100
This thesis introduced and investigated some important components in the phased array systems. Two 60-GHz switch-type phase shifters (4-bit and 5-bit), an integrated 60-GHz phase shifter and VGA and a 0-20 GHz low phase variation attenuator are presented in this thesis. As the growing demands for wireless communication, the lower frequency bands are fully occupied with various communication applications. Due to an up to 9-GHz unlicensed wide bandwidth around 60-GHz, the millimeter-wave frequency bands are suitable for high data rate wireless transmission. However, the oxygen absorption causes the dissipation of signal during transmission, especially for non-line-of-sight (NLOS) situation. Besides, the limited noise figure of the receiver and the limited output power of the transmitter also restrict the applications at 60-GHz. Phased array technique is an attractive solution to the problem mentioned above. The advantages of phased array systems include path loss compensation, channel capacity enhancement and signal-to-noise ratio improvement. Therefore, it can relax the requirements of the RF transceiver front-ends. The thesis can be constructed in to three parts. The first part presents a 4-bit switch-type phase shifter using TSMC 90-nmLP CMOS technology. The proposed phase shifter uses all-transmission lines topology to avoid using small-size capacitors which can be easily affected by process variation. The transmission-line topology can alleviate the error caused by process variation and achieve low group delay deviation. The phase shifter is carefully designed to achieve excellent insertion loss flatness of ± 0.8-dB from 57-64 GHz. The measured group delay deviation and maximum insertion loss of the 16 phase-shifting states is ± 6-ps over 57-63 GHz and 14.5-dB at 60-GHz, respectively. The second part consists of a 5-bit switch-type phase shifter and an integrated phase shifter and VGA. Compared to the 4-bit phase shifter, the 5-bit switch-type phase shifter can provide a higher resolution in a phased array system and thus improving the signal-to-noise ratio with a cost of sacrificing a little insertion loss. The 5-bit phase shifter achieve a maximum insertion loss of about 18-dB over 57-64 GHz. The insertion loss flatness and group delay deviation are ± 0.8-dB and ± 8.5-ps from 57-64 GHz, respectively. The integrated phase shifter and VGA features the independent phase and tuning. The low phase variation VGA can provide gain variation of 6.2-dB with only 1.86˚ phase variation, this low phase variation property can ensure the phase of the phase shifter will not be affected by the VGA gain tuning. The third part is a low phase variation attenuator. Compared to the VGA, the attenuators are suitable for systems with high linearity requirements. The attenuator utilizes a spiral inductor to cancel out the parasitic capacitors of a transistor to achieve low phase variation. The measured maximum attenuation is about 34-dB with a phase variation of 6.5˚. In summary, two phase shifters and a phase shifter integrated with VGA operating from 57-64 GHz are presented. The designs are suitable for 60-GHz phased array systems, targeting for high-data-rate wireless transmission. A 0-20 GHz low phase variation attenuator is shown as well.

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38

Pei-KangTsai i 蔡佩剛. "Designs of Key Component Circuits for Microwave and Millimeter-Wave Phase-Locked Loop Applications". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/21512909635504048062.

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博士
國立成功大學
電機工程學系碩博士班
101
In this dissertation, the key component circuits of microwave and millimeter-wave phase-locked loops have been designed and investigated, including a dual-band quadrature voltage-controlled oscillator (QVCO), high-division-ratio and dual-mode injection-locked frequency dividers (ILFDs), and frequency triplers integrated with VCO. All the circuits are implemented and fabricated in 0.18-μm CMOS technology. This dissertation is divided into four parts. In each part, the related novel design concepts are described and demonstrated. In the first part, a dual-band (3 GHz and 7 GHz) QVCO using new differential inner-diamond-structure (IDS) switchable inductors is proposed. Such proposed QVCO can ease the phase noise degradation resulted from a degraded quality factor. In contrast, a QVCO integrated with conventional differential switchable inductors has also fabricated and characterized for comparison. The experimental data highlights that the use of IDS switchable inductor provides a better performance outcome. The second part of this dissertation demonstrates two design cases of high-division-ratio ILFDs. The first ILFD combining the shunt-peaking and current-bleeding techniques can operate from 23 to 27 GHz with a division-by-three function. A maximum locking range of 1 GHz can be obtained with low power consumption. The second ILFD operates at 40 GHz with a division-by-five function. By using a series-LC band-pass filter to bypass the unwanted second harmonic and enhance the fourth harmonic at the common node of the injector transistor pair, a maximum locking range of 0.735 GHz can be achieved. The third part of this dissertation focuses on the new integration methodology of a VCO and a frequency tripler. An 8 GHz wideband VCO provides simultaneously the fundamental and second harmonic signals which are directly fed into the frequency tripler at two specified input nodes for enhancing the frequency mixing. Therefore, the wideband operation frequency range from 22 to 27 GHz can be achieved. Besides, by stacking the VCO and the tripler with a current-reused topology, the power consumption is only 9 mW. The last part of this dissertation presents a wideband dual-mode ILFD design by using a regenerative second-harmonic feedback technique. Wide input locking ranges can be achieved at two operation modes including the injection-locked oscillator (ILO) mode (i.e. divide-by-one) and the divide-by-three ILFD mode, by using the proposed regenerative feedback technique. All above-mentioned component circuits are designed with the consideration of PLL system requirements. All the circuits not only have outstanding performances but also exhibit a high potential of use in high-performance microwave and millimeter-wave PLLs (e.g. wideband, dual-band, and low power consumption).

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39

虞繼堯. "The Design and Analysis of CMOS Millimeter-Wave Integrated Circuits for Ultra-Wideband Communication Systems". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/54879994259156882984.

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博士
國立交通大學
電子工程系所
96
In this thesis, the design methodologies and implementation techniques of CMOS integrated circuits (ICs) for millimeter-wave (MMW) ultra-wideband (UWB) applications are presented. There are four different kinds of MMW ICs presented in this thesis, including: 1) a direct injection-locked frequency divider; 2) a down-conversion third-order sub-harmonic active mixer; 3) a MMW UWB homodyne receiver front-end; and 4) two multi-band voltage-controlled oscillators (VCOs) with a large frequency tuning range in MMW band and RF band for low-voltage applications. At first, direct injection-locked frequency dividers operated in the millimeter-wave band are analyzed. An analytically equivalent model of the direct injection-locked frequency dividers is developed and important design guidelines for a large frequency locking range are obtained. A direct injection-locked frequency divider without varactors is designed and fabricated using 0.13-μm bulk- CMOS process to verify the developed model and design guidelines. The size of the input device is only 3.6μm/0.12μm and the measured frequency locking range is 13.6% at 70GHz with a power consumption of 4.4mW from a supply voltage of 1V. Secondly, a down-conversion third-order sub-harmonic active mixer is analyzed and fabricated with an on-chip VCO using 0.13-μm CMOS technology. The required LO frequency is one third of that required in a fundamental mixer. Because of the decrease in the LO frequency, the frequency tuning range of the integrated VCO can be extended significantly. Moreover, with the essential differential characteristics of the third harmonic components of LO signals, a balanced structure can be achieved without any extra effort as a fundamental mixer. From the measurement results, it can be observed that the tuning range of the VCO is 13.35% at 19.48 GHz with the corresponding RF frequency range from 54.54 to 62.34 GHz. The average gain of the proposed mixer is 7.8 dB and the variation is smaller than 2.2 dB within the tuning range. The input 1-dB compression point is around –10.2 dBm and the power leakage of the 2LO/LO signal at the RF port is smaller than –35/–42.5 dBm, respectively. The average power consumption of the VCO and the mixer core within the operating frequency range are 6.6 and 0.36 mW, respectively. Thirdly, a homodyne receiver using third-order sub-harmonic active mixers is analyzed and designed by using 0.13-μm CMOS technology. The receiver consists of a low-noise amplifier (LNA), sub-harmonic active mixers, baseband amplifiers, output buffers, and a qudrature VCO. Due to the reduction in the required LO frequency by using the sub-harmonic mixers, the frequency tuning range of the integrated quadrature VCO can be significantly extended. From ADS and SpectreRF simulation results, the frequency tuning range of the qudrature VCO is 19.87% at 20.35 GHz and the corresponding RF frequency range is sufficient to cover the entire MMW unlicensed band in the U.S. (i.e. 57 – 64 GHz). The gain of the receiver within the unlicensed band is form 25 to 29.25 dB and the noise figure is from 11.1 to 13.4 dB. The 1-dB compression point occurs around -28 dBm. The phase noise of the quadrature VCO at 1-MHz offset is -96 dBc/Hz. The average power consumption of the receiver is 35.6 mW from a supply voltage of 1.2 V. Finally, two different multi-band VCOs with wide tuning range are proposed. One of them is operated in the MMW band. It employs a single variable inductor for frequency tuning. By employing the proposed frequency tuning scheme, wide-tuning range as well as multi-band operations are achieved without sacrificing its operating frequency. Fabricated in a 90-nm CMOS process, the VCO is capable of covering frequency range from 52.2 to 61.3 GHz. The tuning percentage is 16% at 56.75 GHz. The measured average phase noise within the tuning range is about -102.4 dBc/Hz at 10-MHz offset. The maximum oscillation voltage amplitude is around -4.55 dBV. The VCO core dissipates 8.7 mW from a 0.7-V supply. Chip size is 0.28 × 0.36 mm2. The other VCO is operated around 5 GHz which can be chosen as the intermediate frequency in an MMW heterodyne receiver. In this situation, the designed VCO can be used as the LO signal generator in the MMW heterodyne receiver to downconvert the intermediate frequency signals to the baseband. Inversion-mode MOS (I-MOS) varactors are used in the VCO to maintain a wide tuning range in the situation that the supply and tuning voltage is lower than 1V. Moreover, a large resistor is inserted between ground and bulk terminals of each I-MOS varactor to further improve the tuning capability. Through this resistor, the tuning range is increased by 500 MHz (50%). A bandswitching topology is used to ameliorate the adverse effects of highly sensitive I-MOS varactors. The VCO is designed using 0.18-μm CMOS technology. With a 0.8-V supply, it is shown from simulation results that the VCO has a tuning range of 29.12% from 4.4 to 5.9 GHz when tuned from 0 to 0.8 V. The simulated phase noise is -109.65 dBc/Hz at 1-MHz offset from the 5.52-GHz carrier. The power consumption is 1.2 mW. It is believed that the proposed IC components can be applied to the design of high-performance high-integration all-CMOS wireless communication systems for MMW UWB applications. Further research on the integration of other transceiver components to form all-CMOS MMW UWB systems will be conducted in the future.

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Chen, Wei-Zhi, i 陳威志. "Design of Advanced PCB Circuits and Log Periodic Antennas for Millimeter Wave Ultra-Wideband Applications". Thesis, 2019. http://ndltd.ncl.edu.tw/handle/765z7v.

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碩士
國立臺灣大學
電信工程學研究所
107
This thesis aims to design ultra-wideband baluns, couplers and log periodic antennas. Used to integrate into an ultra-wideband linearly polarized antenna. The directional coupler can produce a phase difference of 90 degrees, which can be converted to circular polarization. Or with a phase difference of 180 degrees to produce a sequential rotation. The balun circuit is used to convert the unbalanced feed into a balanced output, which reduces the field offset and stabilizes the system gain. Log periodic antennas are commonly used ultra-wideband antennas with stable gain and linear polarization in ultra-wideband designs. Such antennas require an additional design to connect the unbalanced feed. In the coupler section, design the coupled line and use the even/odd mode analysis to adjust the coupling coefficient so that the magnitude imbalance is within 0 dB plus or minus 6 dB. The simulated frequency band falls between 3 GHz and 38 GHz, and the measured frequency band is from 3 GHz to 30 GHz. In the ultra-wideband balun section, analyze the architecture of the marchand balun and map it to the equivalent transmission line model. Design the impedance of each segment of the transmission line and expand its bandwidth. The simulated frequency band is from 3 GHz to 40 GHz. In order to integrate the circuit with the log periodic antenna, we use printed circuit board technology. Not only can the design be simplified, but also the advantages of reducing the size. After the log periodic antenna is integrated, the frequency band falls between 5 GHz and 40 GHz, and the simulated peak gain is about 2 dBi to 6 dBi. The measured peak gain is from 2 dBi to 6 dBi, but its starting frequency is 12 GHz. The millimeter-wave log periodic antenna integration has a frequency band of 11 GHz – 35 GHz and the simulated peak gain of approximately 2 dBi to 4 dBi.

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41

Hsiao, Yu-Hsuan, i 蕭宇軒. "The Design and Implementation of Monolithic Microwave Integrated Circuits for WiMAX, K-Band, and 60 GHz Millimeter Wave Application". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/14032145785291787044.

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碩士
逢甲大學
通訊工程所
98
Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 um SiGe BiCMOS, TSMC 0.18 um CMOS and WIN Semiconductors corporation (WIN) 0.15 um PHEMT processes are used for the RF front-end circuit design, the advantages and disadvantages of these processes will be analysis and discussed in the thesis. All processes are provided by the National Chip Implementation Center (CIC) For more and more high-speed transmission need, three kinds of circuit are designed for the WiMAX, K-Band and 60 GHz millimeter wave, the first is 0.35 um SiGe BiCMOS low noise amplifier (LNA) and mixer for WiMAX application, the second is CMOS 0.18 um LNA for WiMAX, satellite broadcasting system, and ACMRC (asymmetrical compact microstrip resonator cell) band-pass filter for K-Band application, the third is using PHEMT 0.15 um to design LNA and ACMRC filter for 60 GHz millimeter wave application.

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42

Lu, Cheng-han, i 呂承翰. "Design and Analysis of Microwave and Millimeter-Wave Low Phase Noise Signal Source Integrated Circuits using Injection-locked Technique". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/82720147288882797053.

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碩士
國立中央大學
電機工程學系
101
Design and analysis of low phase noise signal source integrated circuits using injection-locked technique is presented in this dissertation. A 24-GHz high output power and high efficiency power oscillator (POSC) is proposed using a 0.15-µm GaAs PHEMT process in Chapter 2. It also can be used as an active injection-locked phase shifter. By tuning the ratio between the input resistance and load resistance, the proposed POSC achieves a maximum output power of 21.3 dBm and a maximum efficiency 32%. Besides, using the same way, a U-band high efficiency POSC using a 0.1-µm GaAs PHEMT process is also presented. These two works demonstrate good figure-of-merit (FOM) among all the reported fully integrated POSCs. In Chapter 3, two fully integrated K-band multi-phase voltage-controlled oscillators are presented. First one is a parallel-coupled quadrature-phase voltage-controlled oscillator (P-QVCO) using a 0.5-µm BiFET process. The second is an eight-phase VCO with current-reused configuration and transformer-feedback using a standard bulk 90-nm COMS process. Besides, the characterization of the amplitude and phase errors for the multi-phase VCO is successfully demonstrated using the proposed innovative method. As compared with the previously reported state-of-the-art multi-phase VCOs, these works feature low phase and amplitude errors. A 2.5-GHz SILPLL with delay-locked loop (DLL) self-aligned injection using 65-nm CMOS technology is presented in Chapter 4. With the proposed innovative topology, the phase between the injection signal and the sub-harmonically injection-locked voltage controlled oscillator (SILVCO) in the PLL can be dynamically aligned to minimize the jitter over the variation. The in-band phase noise of the SILPLL can be significantly improved using the SIL technique. As the operation frequency is 2.3 GHz, the measured phase noise of the proposed SILPLL with self-aligned injection is -123.1 dBc/Hz at 1 MHz offset with a rms jitter of 356 fs. Finally, we summarize the conclusion in Chapter 5.

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