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Brodie, Alan David. "An electron optical line source for microelectronic engineering". Thesis, University of Cambridge, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.357743.
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Goodson, Kenneth E. (Kenneth Eugene). "Thermal conduction in microelectronic circuits". Thesis, Massachusetts Institute of Technology, 1993. http://hdl.handle.net/1721.1/12615.
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Balla, Tobias. "Modelling of microelectronic processes and materials". Thesis, University of Southampton, 2011. https://eprints.soton.ac.uk/348865/.
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Organic electronics promises the creation of electronic components on flexible materials at low temperatures, by fast techniques and more environmentally friendly processes. The research followed two directions. The first part focused on the manufacturing technique nanoimprint lithography (NIL). A comprehensive review was undertaken and process capabilities were compared for trends. It was seen that small feature sizes (< 50 nm) have not been replicated over areas greater than 4 mm2, while aspect ratios greater than 10 have not been achieved. A questionnaire addressing market opportunities suggested NIL is likely to compete for the production of devices that currently use electron beam lithography and laser writing processes that are seeking to change their business strategy from a differentiation base to a cost reduction. NIL must also prove to customers that it is an economical investment. However, improvements in stamp creation, analysis techniques and overlay alignment need to be addressed for a larger share of the microfabrication market. It was apparent that physical limits exist to which imprints can be produced and an analytical model could predict these. A model was created to describe the de-embossing step and to explore how the various material properties and process variables interact. It showed a very strong dependence on the achievable aspect ratio on the pattern area ratio and the interfacial shear stress; that de-embossing using fluorinated coatings and current standard polymers is unlikely to fail for post radii on the order of 100 nm due to adhesion and that large area ratios and aspect ratios are more easily achieved by maintaining the polymer/stamp Young’s moduli ratio (RE) in the range 0.003 to 5. The second part of the research looked at the formation of crescent singularities in thin sheet materials, which affects the production of polymer electronic based devices produced by the sponsoring company. The author compared an analytical model by Cerda and Mahadevan for the formation of developable cones (d-cones) to a finite element (FE) model and showed that explicit elements could mimic the formation of a d-cone. Different elements were analysed for their suitability and the Belytschko-Lin-Tsay (BT) element was chosen based on its speed, robustness and similarity to the analytical results. An adapted three-point bend test set-up was conceived that would enable specific attributes to be independently varied, to understand their effect on d-cone formation in thin sheets. Digital image correlation (DIC) was used to calculate the displacements and strains. The same set-up was modelled using an FE model with the chosen BT element. The DIC results showed a variation in strain with plunger displacement before the visual appearance of a developable cone and that it occurred between 0.1 and 0.4 % in-plane strain. The FE data showed a similar trend to the DIC results, showing a change in strain once a d-cone began to form. Improvements and suggestions were then made advising how to make the DIC and FE models more accurate.
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Maseeh, Fariborz. "Characterization of mechanical properties of microelectronic thin films". Thesis, Massachusetts Institute of Technology, 1990. http://hdl.handle.net/1721.1/14081.
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Tsuk, Michael James. "Propagation and interference in lossy microelectronic integrated circuits". Thesis, Massachusetts Institute of Technology, 1990. http://hdl.handle.net/1721.1/14024.
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Kulkarni, Milind Sudhakar. "Tribochemical investigation of microelectronic materials". Thesis, [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1831.
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Laval, Stuart S. (Stuart Sean) 1980. "A microelectronic design for low-cost disposable chemical sensors". Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/28424.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 57).
This thesis demonstrates the novel concept and design of integrated microelectronics for a low-cost disposable chemical sensor. The critical aspects of this chemical sensor are the performance of the microelectronic chip and how this chip integrates and interfaces with the resistive sensors that detect chemicals. The design, simulation, and implementation of a low-power CMOS microelectronic analog measurement system and integration with the resistive chemical sensors is described. The overall goal is to produce a microelectronic design that can be fabricated, tested, and manufactured by an outside semiconductor vendor.
by Stuart S. Laval.
M.Eng.
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Hou, Chih-Sheng Johnson. "An integrated microelectronic device for biomolecular amplification and detection". Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/38676.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 133-154).
The extraordinarily high sensitivity, large dynamic range and reproducibility of polymerase chain reaction (PCR) have made it one of the most widely used techniques for analyzing nucleic acids. As a result, considerable effort has been directed towards developing miniaturized systems for PCR, but most rely on off-chip optical detection modules that are difficult to miniaturize into a compact analytical system and fluorescent product markers that can require extensive effort to optimize. This thesis presents a robust and simple method for direct label-free PCR product quantification using a microelectronic sensor. The thesis covers the design, fabrication, and characterization of the sensing technique and its integration with PCR microfluidics into a monolithic detection platform. The sensor used in this thesis study is an electrolyte-insulator-silicon (EIS) device fabricated on planar silicon substrates. Based on electronic detection of layer-by-layer assembly of polyelectrolytes, the sensing technique can specifically quantify double-stranded DNA product in unprocessed samples and monitor the product concentration at various stages of PCR to generate readout analogous to that of a real-time fluorescent measurement.
(cont.) Amplification is achieved with integrated metal resistive heaters, temperature sensors, and microfluidic valves. Direct electronic quantification of the product on-chip yields analog surface potential signals that can be converted to a digital true/false readout. A silicon field-effect sensor for direct detection of heparin by its intrinsic negative charge has also been developed. Detection of heparin and heparin-based drugs in buffer and serum has been studied, and a study demonstrating strong correlation between electronic heparin sensing measurements and those from a colorimetric assay for heparin-mediated anti-Xa activity has been performed.
by Chih-Sheng Johnson Hou.
Ph.D.
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Guzek, John S. (John Stephen). "Fatigue crack propagation along polymer-metal interfaces in microelectronic packages". Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/41401.
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Solis, Adrian (Adrian Orbita). "MIT Device Simulation WebLab : an online simulator for microelectronic devices". Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/33364.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2005.Includes bibliographical references (p. 149-157).
In the field of microelectronics, a device simulator is an important engineering tool with tremendous educational value. With a device simulator, a student can examine the characteristics of a microelectronic device described by a particular model. This makes it easier to develop an intuition for the general behavior of that device and examine the impact of particular device parameters on device characteristics. In this thesis, we designed and implemented the MIT Device Simulation WebLab ("WeblabSim"), an online simulator for exploring the behavior of microelectronic devices. WeblabSim makes a device simulator readily available to users on the web anywhere, and at any time. Through a Java applet interface, a user connected to the Internet specifies and submits a simulation to the system. A program performs the simulation on a computer that can be located anywhere else on the Internet. The results are then sent back to the user's applet for graphing and further analysis. The WeblabSim system uses a three-tier design based on the iLab Batched Experiment Architecture. It consists of a client applet that lets users configure simulations, a laboratory server that runs them, and a generic service broker that mediates between the two through SOAP-based web services. We have implemented a graphical client applet, based on the client used by the MIT Microelectronics WebLab.
(cont.) Our laboratory server has a distributed, modular design consisting of a data store, several worker servers that run simulations, and a master server that acts as a coordinator. On this system, we have successfully deployed WinSpice, a circuit simulator based on Berkeley Spice3F4. Our initial experiences with WeblabSim indicate that it is feature-complete, reliable and efficient. We are satisfied that it is ready for beta deployment in a classroom setting, which we hope to do in Fall 2004.
by Adrian Solis.
M.Eng.
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Akerson, Jerome Jeffrey 1961. "Numerical techniques for electromagnetic applications in microelectronic and radar imaging systems". Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/46116.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (p. 227-242).
by Jerome J. Akerson.
Ph.D.
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How, Yew Seng. "Modeling of impression testing to obtain mechanical properties of lead-free solders microelectronic interconnects". Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2005. http://library.nps.navy.mil/uhtbin/hyperion/05Dec%5FHow.pdf.
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Thesis (M.S. in Engineering Science (Mechanical Engineering))--Naval Postgraduate School, December 2005.Thesis Advisor(s): Indranath Dutta. Includes bibliographical references (p. 79-80). Also available online.
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Randrianandrasana, Michel F. "Finding structures in information networks using the affinity network". Thesis, Aston University, 2011. http://publications.aston.ac.uk/15684/.
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This thesis proposes a novel graphical model for inference called the Affinity Network,which displays the closeness between pairs of variables and is an alternative to Bayesian Networks and Dependency Networks. The Affinity Network shares some similarities with Bayesian Networks and Dependency Networks but avoids their heuristic and stochastic graph construction algorithms by using a message passing scheme. A comparison with the above two instances of graphical models is given for sparse discrete and continuous medical data and data taken from the UCI machine learning repository. The experimental study reveals that the Affinity Network graphs tend to be more accurate on the basis of an exhaustive search with the small datasets. Moreover, the graph construction algorithm is faster than the other two methods with huge datasets. The Affinity Network is also applied to data produced by a synchronised system. A detailed analysis and numerical investigation into this dynamical system is provided and it is shown that the Affinity Network can be used to characterise its emergent behaviour even in the presence of noise.
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Vargheese, K. Deenamma. "ECR Assisted Deposition of Tin And Si3N4 Thin Films For Microelectronic Applications". Thesis, Indian Institute of Science, 2000. http://hdl.handle.net/2005/202.
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The broad theme of the present research investigation is Ion Assisted Deposition of thin films and its effect on the properties of thin films. Though this activity has been of interest to researchers for more than a decade, the development of different types of ion sources with control over the ion flux and energy, makes it a current topic of interest. Ion assisted deposition was successful in depositing thin films of many material with desired qualities, however, there are certain class of materials whose deposition has been rather difficult. This has mainly been attributed to higher energies and low ion flux of conventional ion sources. The advent of ECR ion sources for thin film deposition has given impetus to the deposition of such materials. This is due to the low energy high-density plasma generated in this type of sources. Hitherto, these sources were widely used in PECVD techniques and only recently the importance of ECR sources in PVD techniques has been realized. This thesis is on the development of ECR plasma source for ion assisted deposition of thin films using PVD techniques. This thesis is organized into six chapters.
The first chapter gives an introduction on the ion assisted growth of thin films and the importance of ECR plasma. A detailed discussion on various aspects of ECR sources has been included.
The design details on the development of ECR source have been discussed in the second chapter. The performance of ECR source as analyzed by the Langmuir probe are also discussed. Variation of plasma parameters like ion density, electron temperature, plasma potential and floating potential as a function of pressure and microwave power have been studied using Langmuir probe analysis. An ion density of the order of 1011/cm3 was measured at a distance of 8 cm from the plasma source with a microwave power of 400 watts. This was comparable to the ion density reported in downstream plasma of ECR sources. The behavior of plasma parameters with variation in microwave power and pressure was explained on the basis of microwave transmission above critical ion density and the microwave power absorption. The uniformity of the plasma parameters at the substrate position (29 cm from the ECR source) was found to be ± 2% over a diameter of 12 cm, which makes the ion source suitable for ion assisted deposition.
The third chapter deals with the simulation and experimental study of the ECR sputtering process. ECR sputter type sources are equipped with cylindrical targets. The sputtered flux distribution on the substrate depends on target geometry, sputtering pressure and target-substrate distance. The effect of cylindrical geometry on the distribution of sputtered flux has been simulated by Monte Carlo methods. It is found that the sputtered flux distribution at different pressures and target-substrate distances in ECR sputter type source differs from the conventional glow discharge sputtering system equipped with planar targets. The simulated results are compared with the experimental results. The simulated data agree very well with the experimental data.
The deposition and characterization of the TiN thin films for diffusion barrier applications in copper metallization have been discussed in the fourth chapter. Titanium nitride films are prepared by ECR sputtering. The effect of high density ion bombardment on the morphology, orientation and resistivity of the films was studied. It was observed that films with atomic smoothness could be prepared by ECR sputtering. Also the high density ion bombardment has been found to be effective for the film growth in (100) orientation. The behavior of TiN films deposited by this method as a diffusion barrier in copper metallization has been investigated. The resistivity measurements and RBS depth profile studies showed that up to 700°C there is no diffusion of copper into silicon. This shows that ECR sputtered TiN can be used as an effective diffusion barrier in copper metallization.
The fifth chapter contains investigations on the ECR assisted growth of silicon nitride films. The films are characterized for composition, morphology and chemical bonding using AES, RBS, AFM, XPS and FTIR. AFM studies revealed that ion bombardment results in the reduction of surface roughness, which indicates dense film growth. The effect of ion assistance on the optical and electrical properties is studied in detail. Films prepared with microwave power ranging from 100 to 200 watts are having bandgap and refractive index of 4.9 eV and 1.92 respectively. Interface state density of silicon nitride films prepared in the above mentioned range was found to be 5x10 10 eVcm2. These films exhibited a resistivity of 10 13 Ω, cm and critical field of 4 MV/cm. The electrical conductivity in these films has been explained on the basis of Poole and Frenkel conduction. The low value of interface state density, higher resistivity, and critical field show that good quality SiN4 films can be deposited with low energy high density ECR plasma.
A detailed summary of this research investigation has been discussed in the last chapter. The thesis is concluded with a discussion on the need of focused ECR source to establish ECR assisted deposition as a versatile technique for the growth of thin films.
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Xue, Hao. "Hardware Security and VLSI Design Optimization". Wright State University / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=wright1546466777397815.
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Li, Kecheng. "Direct Liquid Evaporation Chemical Vapor Deposition(DLE-CVD) of Nickel, Manganese and Copper-Based Thin Films for Interconnects in Three-Dimensional Microelectronic Systems". Thesis, Harvard University, 2016. http://nrs.harvard.edu/urn-3:HUL.InstRepos:33493366.
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Electrical interconnects are an intrinsic part of any electronic system. These interconnects have to perform reliably under a wide range of environmental conditions and survive stresses induced from thermal, mechanical, corrosive and electrical factors. Semiconductor technology is predominantly planar in nature, posing a severe limitation to the degree of device integrations into systems such as micro-processors or memories. 3D transistor FinFET (Fin type Field Effect Transistors) has been used by Intel since the advent of its 22 nm technology node, and has now advanced further down to 14 nm. While the technology nodes have consistently been shrinking in line with Moore’s law, increasing difficulties in scaling down the feature sizes in transistors is urging the industry to seek alternative fabrication approaches for the extension of Moore’s law. The most promising solution thus far is 3D heterogeneous integration, which will stack logical and analog chips together to enable multi functions chip without the need to scale the size of transistors with Moore’s law. Furthermore, as wearable electronics are fast growing in the next big wave in consumer electronics after the smartphone era, interconnects face the unique challenge of having to be embedded into fashion and withstand the mechanical stresses from everyday activity. This makes the role interconnects even more important as well as making it the main bottleneck to unleashing the full performance of the 3D microelectronics systems.
This thesis explores the fabrication, characterization and application of Nickel, Manganese, Copper based thin films for the interconnects of 3D microelectronics systems. Direct Liquid Evaporation-Chemical Vapor Deposition (DLE-CVD) technique has been proven to be a high-throughput process for high-quality Nickel, Manganese, Copper based thin films with excellent conformality in complex architectures as the interconnects for state-of-the-art 3D microelectronics systems.
Chapter 2 introduces the advantages of DLE-CVD process and its application in deposition of Nickel, Manganese and Copper based thin films. DLE-CVD process is used to deliver consistent and high vapor concentrations of Nickel, Manganese and Copper precursors to coat nanostructures with high aspect ratios.
Chapter 3 demonstrates the atom probe tomography (APT) as an effective method for understanding the 3D microstructure and compositional properties in thin films at an atomic scale. 3D compositional information of DLE-CVD NiNx, NiSi thin films from inside and outside regions of the trench structures have been investigated using APT. The APT characterization technique provides a unique tool that can be applied both to the design of 3D nanostructured microelectronic devices and to the further understanding of the fundamental physical properties.
Chapter 4 highlights the application of DLE-CVD manganese and copper based thin film process in the complex nanostructures for 3D microelectronic systems. Narrow trenches with width under 30 nm are the key nanostructure in the local interconnects in 3D FINFET with technology node smaller than 14 nm for use in microelectronic chips. It can be filled with DLE-CVD copper and copper-manganese alloy in a bottom-up fashion using a surfactant-catalyzed CVD process. An ultrathin manganese nitride layer (~ 3 nm) acts as a diffusion barrier and an adhesion layer. Through-silicon vias (TSVs) plays a crucial role in advancing the 3D integration of semiconductor devices by improving the performances of interconnections between chips. Using DLE-CVD processes, conformal, smooth and continuous copper/copper-manganese seed layers can be prepared in TSVs with aspect ratio greater than 25:1. manganese Nitride film is deposited via the DLE-CVD process to serve as an adhesion and barrier layer. Dow Chemicals achieved void-free TSV filling through the electroplating process.
Chapter 5 shows the application of the DLE-CVD manganese and copper based thin film process in the metallization of polyaramids for the application in the interconnects embedded in wearable electronic systems. Conformal and conductive coatings of copper-manganese have been successfully deposited on Kevlar fibers using the DLE-CVD process with complete film coverage. The mechanical resistance of copper-manganese coated Kevlar was tested via our in-house robotic arm system, demonstrating how the electrical resistance of the wire remains unchanged despite being flexed repeatedly to a bend of 5mm radius for half a million times.Engineering and Applied Sciences - Applied Physics
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Cheong, Kuan Yew, i n/a. "Silicon Carbide as the Nonvolatile-Dynamic-Memory Material". Griffith University. School of Microelectronic Engineering, 2004. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20050115.101233.
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This thesis consists of three main parts, starting with the use of improved nitridation processes to grow acceptable quality gate oxides on silicon carbide (SiC)[1][7], to the comprehensive investigation of basic electron-hole generation process in 4H SiC-based metaloxidesemiconductor (MOS) capacitors [8], [9], and concluding with the experimental demonstration and analysis of nonvolatile characteristics of 4H SiC-based memory devices [10][15]. In the first part of the thesis, two improved versions of nitridation techniques have been introduced to alleviate oxide-growth rate and toxicity problems. Using a combination of nitridation and oxidation processes, a sandwich technique (nitridationoxidationnitridation) has been proposed and verified to solve the lengthy and expensive oxide-growing process in direct nitric oxide (NO) gas [1]. The nitrogen source from the toxic-NO gas has been replaced by using a nontoxic nitrous oxide (N2O) gas. The best combination of process parameters in this gas is oxide-growing temperature at 1300oC with 10% N2O [2], [3]. The quality of nitrided gate oxides obtained by this technique is lower than the sandwich technique [6], [13]. Using 4H SiC-based MOS with nitrided gate oxides grown by either of the abovementioned nitridation techniques, the fundamentals of electron-hole generation have been investigated using high-temperature capacitancetransient measurements. The contributions of carrier generation, occurring at room temperature, in the bulk and at the SiCSiO2 interface are evaluated and compared using a newly developed method [8], [9]. The effective bulk-generation rates are approximately equal for both types of nitrided oxides, whereas the effective surface-generation rates have been shown to exhibit very strong dependencies on the methods of producing the nitrided gate oxide. Based on analysis, the prevailing generation component in a SiC-based MOS capacitor with nitrided gate oxide is at SiCSiO2 interface located below the gate. Utilizing the understanding of electron-hole generation in SiC, the nonvolatile characteristics of memory device fabricated on SiC have been explored. The potential of developing a SiC-based one-transistor one-capacitor (1T/1C) nonvolatile-dynamic memory (NDM) has been analyzed using SiC-based MOS capacitors as storage elements or test structures. Three possible leakage mechanisms have been evaluated [10][16]: (1) leakage via MOS capacitor dielectric, (2) leakage due to electron-hole generation in a depleted MOS capacitor, and (3) junction leakage due to generation current occurred at a reverse-biased pn junction surrounding the drain region of a select metaloxide semiconductor fieldeffecttransistor (MOSFET). Among them, leakage through capacitor oxide remains an important factor that could affect the nonvolatile property in the proposed device, whereas others leakage mechanisms are insignificant. Based on the overall results, the potential of developing a SiC-based 1T/1C NDM is encouraging.
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Cheong, Kuan Yew. "Silicon Carbide as the Nonvolatile-Dynamic-Memory Material". Thesis, Griffith University, 2004. http://hdl.handle.net/10072/367177.
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This thesis consists of three main parts, starting with the use of improved nitridation processes to grow acceptable quality gate oxides on silicon carbide (SiC)[1]–[7], to the comprehensive investigation of basic electron-hole generation process in 4H SiC-based metal–oxide–semiconductor (MOS) capacitors [8], [9], and concluding with the experimental demonstration and analysis of nonvolatile characteristics of 4H SiC-based memory devices [10]–[15]. In the first part of the thesis, two improved versions of nitridation techniques have been introduced to alleviate oxide-growth rate and toxicity problems. Using a combination of nitridation and oxidation processes, a sandwich technique (nitridation–oxidation–nitridation) has been proposed and verified to solve the lengthy and expensive oxide-growing process in direct nitric oxide (NO) gas [1]. The nitrogen source from the toxic-NO gas has been replaced by using a nontoxic nitrous oxide (N2O) gas. The best combination of process parameters in this gas is oxide-growing temperature at 1300oC with 10% N2O [2], [3]. The quality of nitrided gate oxides obtained by this technique is lower than the sandwich technique [6], [13]. Using 4H SiC-based MOS with nitrided gate oxides grown by either of the abovementioned nitridation techniques, the fundamentals of electron-hole generation have been investigated using high-temperature capacitance–transient measurements. The contributions of carrier generation, occurring at room temperature, in the bulk and at the SiC–SiO2 interface are evaluated and compared using a newly developed method [8], [9]. The effective bulk-generation rates are approximately equal for both types of nitrided oxides, whereas the effective surface-generation rates have been shown to exhibit very strong dependencies on the methods of producing the nitrided gate oxide. Based on analysis, the prevailing generation component in a SiC-based MOS capacitor with nitrided gate oxide is at SiC–SiO2 interface located below the gate. Utilizing the understanding of electron-hole generation in SiC, the nonvolatile characteristics of memory device fabricated on SiC have been explored. The potential of developing a SiC-based one-transistor one-capacitor (1T/1C) nonvolatile-dynamic memory (NDM) has been analyzed using SiC-based MOS capacitors as storage elements or test structures. Three possible leakage mechanisms have been evaluated [10]–[16]: (1) leakage via MOS capacitor dielectric, (2) leakage due to electron-hole generation in a depleted MOS capacitor, and (3) junction leakage due to generation current occurred at a reverse-biased pn junction surrounding the drain region of a select metal–oxide– semiconductor field–effect–transistor (MOSFET). Among them, leakage through capacitor oxide remains an important factor that could affect the nonvolatile property in the proposed device, whereas others leakage mechanisms are insignificant. Based on the overall results, the potential of developing a SiC-based 1T/1C NDM is encouraging.Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
School of Microelectronic Engineering
Faculty of Engineering and Information Technology
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Doppalapudi, Ranjeeth. "Design-for-manufacturability (DFM) for system-in-package (SiP) applications". Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26701.
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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Dr. Swaminathan, Madhavan; Committee Member: Dr. Chatterjee, Abhijit; Committee Member: Dr. Lim, Sungkyu. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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BAMIRO, OLUYINKA OLUGBENGA. "ANALYSIS OF THERMAL STRESS AND PLASTIC STRAIN IN STUDS/VIAS OF MULTILEVEL INTEGRATED CIRCUITS". University of Toledo / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1099778888.
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Suzuki, Takeharu, i n/a. "Integrated, Intelligent Sensor Fabrication Strategies for Environmental Monitoring". Griffith University. School of Microelectronic Engineering, 2004. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20040813.131206.
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The humidity, temperature, wind speed/direction micro sensors can be manufactured individually, resulting in three individual substrates. The integration of the three sensors into a single substrate is a vital challenge to achieve an integrated intelligent sensor so called a multiple sensor. This requires the integration of process flows and is a major challenge because adequate sensor performance must be maintained. Polyimide was selected as a humidity sensing material for its compatibility with conventional integrated circuit fabrication technology, negligible temperature dependence and good resistance against contamination. Nickel was selected for the temperature and wind speed/direction sensor because of its useful temperature coefficient and the advantage of its cost. Since the known wet etchant for nickel requires hard-baked photoresist, a method which does not attack the polyimide while removing the photoresist must be developed. The method developed for etching nickel employs hard-bake-free photoresist. Other challenge was ensuring good thermal isolation for the wind speed/direction sensor fabricated on a silicon nitride layer preformed on top of a silicon wafer. Since silicon acts as a good heat sink, the silicon under the sensor was etched entirely away until the silicon nitride layer was reached. This structure achieved good thermal isolation resulting in small power consumption. This low power feature is essential for sensors deployed in fields where power access or replacement of power sources is restricted. This structure was compared with the structure created by polyimide plateau on a silicon nitride layer coated on a silicon substrate as a function of power consumption. Based on the examination of thermal isolation, the multiple sensor utilizing a MEMS technique was fabricated with a single-sided mask aligner. The characteristics of humidity sensors fabricated with polyimide were examined in detail with respect to variations of electrode structures, improvement of sensitivity, effect of process temperature, temperature and frequency dependence, and stability. The humidity sensor constructed with O2 plasma treated polyimide resulted an improvement in sensitivity and hysteresis. The investigation using XPS, FTIR and AFM concluded the chemical modification of polyimide played an important role in this improvement. The design, fabrication and results of a series of humidity sensors are quantified. There is always no unique packaging solution for sensors because of the application-specific nature of the sensors. This intelligent environmental monitoring system was designed to accommodate both an environmental sensor and its signal conditioning electronics circuitry (SICONEC) into a single package. The environmental sensors need direct exposure to the environment while SICONEC needs a sealed encapsulation to avoid environmental damage. A new style of packaging addressing these requirements was demonstrated using a hot embossing machine. The hot embossing machine was used to embed an integrated circuit (IC) in a bare die condition into a polycarbonate (PC) sheet. In this case, the IC was flipped down against the PC, which protects the front side of the IC from the environmental damages. In a test phase, a die containing operational amplifiers was embossed into the PC. A humidity sensor and surface mount resisters were placed on the same surface of the PC to test the validity of this new technique. Interconnection between the embossed die and the humidity sensor was established using bonding wires. Copper tracks were also used to ensure all electrical connections for the die, the humidity sensor and the resistors. The results clarified the method developed. Details of process methods, issues and further potential improvement are reported.
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Suzuki, Takeharu. "Integrated, Intelligent Sensor Fabrication Strategies for Environmental Monitoring". Thesis, Griffith University, 2004. http://hdl.handle.net/10072/367295.
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The humidity, temperature, wind speed/direction micro sensors can be manufactured individually, resulting in three individual substrates. The integration of the three sensors into a single substrate is a vital challenge to achieve an integrated intelligent sensor so called a multiple sensor. This requires the integration of process flows and is a major challenge because adequate sensor performance must be maintained. Polyimide was selected as a humidity sensing material for its compatibility with conventional integrated circuit fabrication technology, negligible temperature dependence and good resistance against contamination. Nickel was selected for the temperature and wind speed/direction sensor because of its useful temperature coefficient and the advantage of its cost. Since the known wet etchant for nickel requires hard-baked photoresist, a method which does not attack the polyimide while removing the photoresist must be developed. The method developed for etching nickel employs hard-bake-free photoresist. Other challenge was ensuring good thermal isolation for the wind speed/direction sensor fabricated on a silicon nitride layer preformed on top of a silicon wafer. Since silicon acts as a good heat sink, the silicon under the sensor was etched entirely away until the silicon nitride layer was reached. This structure achieved good thermal isolation resulting in small power consumption. This low power feature is essential for sensors deployed in fields where power access or replacement of power sources is restricted. This structure was compared with the structure created by polyimide plateau on a silicon nitride layer coated on a silicon substrate as a function of power consumption. Based on the examination of thermal isolation, the multiple sensor utilizing a MEMS technique was fabricated with a single-sided mask aligner. The characteristics of humidity sensors fabricated with polyimide were examined in detail with respect to variations of electrode structures, improvement of sensitivity, effect of process temperature, temperature and frequency dependence, and stability. The humidity sensor constructed with O2 plasma treated polyimide resulted an improvement in sensitivity and hysteresis. The investigation using XPS, FTIR and AFMconcluded the chemical modification of polyimide played an important role in this improvement. The design, fabrication and results of a series of humidity sensors are quantified. There is always no unique packaging solution for sensors because of the application-specific nature of the sensors. This intelligent environmental monitoring system was designed to accommodate both an environmental sensor and its signal conditioning electronics circuitry (SICONEC) into a single package. The environmental sensors need direct exposure to the environment while SICONEC needs a sealed encapsulation to avoid environmental damage. A new style of packaging addressing these requirements was demonstrated using a hot embossing machine. The hot embossing machine was used to embed an integrated circuit (IC) in a bare die condition into a polycarbonate (PC) sheet. In this case, the IC was flipped down against the PC, which protects the front side of the IC from the environmental damages. In a test phase, a die containing operational amplifiers was embossed into the PC. A humidity sensor and surface mount resisters were placed on the same surface of the PC to test the validity of this new technique. Interconnection between the embossed die and the humidity sensor was established using bonding wires. Copper tracks were also used to ensure all electrical connections for the die, the humidity sensor and the resistors. The results clarified the method developed. Details of process methods, issues and further potential improvement are reported.Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
School of Microelectronic Engineering
Full Text
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Zubair, Muhammed 1962. "Aluminoborophosphosilicate glasses for microelectronics packaging". Thesis, The University of Arizona, 1991. http://hdl.handle.net/10150/277898.
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Glasses are used in microelectronic packaging for insulation and passivation purposes. To optimize the performance of these packages, it is necessary to investigate new glasses or improve on properties of the glasses in use. The insulating glass should have low dielectric constant, low dissipation factor, low glass transition temperature, high chemical resistivity, and a thermal expansion coefficient matching the substrate. In this study, various aluminoborophosphosilicate glasses containing Ca(Mg)O, Ca(Mg)F₂, and AlF₃ as flux were investigated. Processing temperatures for these glasses range from 1300°C to 1500°C. The coefficients of thermal expansion range from 4.52 μ/°C to 9.39 μ/°C. The dielectric constant as a function of frequency and composition is in the range of 4.1 to 5.2. The index of refraction for these glasses is in the range of 1.52 to 1.58. Glass transition and softening temperatures as low as 538°C and 622°C, respective, were found. Results of this investigation are discussed in terms of the possible use of aluminoborophosphosilicate glasses in microelectronic packaging.
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Karnaushenko, Daniil. "Shapeable microelectronics". Doctoral thesis, Universitätsbibliothek Chemnitz, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-205489.
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This thesis addresses the development of materials, technologies and circuits applied for the fabrication of a new class of microelectronic devices that are relying on a three-dimensional shape variation namely shapeable microelectronics. Shapeable microelectronics has a far-reachable future in foreseeable applications that are dealing with arbitrarily shaped geometries, revolutionizing the field of neuronal implants and interfaces, mechanical prosthetics and regenerative medicine in general. Shapeable microelectronics can deterministically interface and stimulate delicate biological tissue mechanically or electrically. Applied in flexible and printable devices shapeable microelectronics can provide novel functionalities with unmatched mechanical and electrical performance. For the purpose of shapeable microelectronics, novel materials based on metallic multilayers, photopatternable organic and metal-organic polymers were synthesized.
Achieved polymeric platform, being mechanically adaptable, provides possibility of a gentle automatic attachment and subsequent release of active micro-scale devices. Equipped with integrated electronic the platform provides an interface to the neural tissue, confining neural fibers and, if necessary, guiding the regeneration of the tissue with a minimal impact. The self-assembly capability of the platform enables the high yield manufacture of three-dimensionally shaped devices that are relying on geometry/stress dependent physical effects that are evolving in magnetic materials including magentostriction and shape anisotropy. Developed arrays of giant magnetoimpedance sensors and cuff implants provide a possibility to address physiological processes locally or distantly via magnetic and electric fields that are generated deep inside the organism, providing unique real time health monitoring capabilities. Fabricated on a large scale shapeable magnetosensory systems and nanostructured materials demonstrate outstanding mechanical and electrical performance. The novel, shapeable form of electronics can revolutionize the field of mechanical prosthetics, wearable devices, medical aids and commercial devices by adding novel sensory functionalities, increasing their capabilities, reducing size and power consumption.
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Hunt-Lowery, Alisa. "STATISTICAL ANALYSIS OF NOVEL DIELECTRIC MATERIALS FOR MICROELECTRONICS". NCSU, 2004. http://www.lib.ncsu.edu/theses/available/etd-09212004-100243/.
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This research analyzes the re-oxidation annealing process of Barium titanate thin films on copper foils made by Chemical Solution Deposition. During this anneal, the temperature and oxygen pressure settings must be optimized to ensure the elimination of oxygen vacancies without oxidizing the copper foil substrate. This research utilizes Design of Experiments (DOE) to study the impact of re-oxidation furnace temperature and pressure on the dielectric loss tangent response. Two designs of experiments were run. The first experiment, a 32 DOE, examined a large range of temperature and pressure levels. Due to the high susceptibility of uncontrollable factors such as humidity and film position in the crystallization anneal furnace, an adequate model could not be developed. However, the temperature at 550ºC and a pressure of 10-5 Torr yielded a lower mean and standard deviation of the loss tangent response. A second and smaller scale experiment, a 22 with a center point, was run around 550ºC and 10-5 Torr to determine if more optimal temperature and pressure settings existed in the local area. Two second order response surface models were developed from two crystallization anneals that were statistically significant. The most significant finding was that the optimum level for temperature and pressure in the re-oxidation anneal furnace in this experiment is 550ºC and 2x10-5 Torr. While the models concluded that the temperature, pressure, temperature quadratic, and interaction between pressure and temperature were important effects in the model, there were differences in the curvature of the models due to the temperature quadratic effect.
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Tumne, Pushkraj Satish. "Investigation of bulk solder and intermetallic failures in PB free BGA by joint level testing". Diss., Online access via UMI:, 2009.
Znajdź pełny tekst źródłaStreszczenie:
Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department or Systems Science and Industrial Engineering, 2009.Includes bibliographical references.
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Cukalovic, Boris. "MIT integrated microelectronics device experimentation and simulation iLab". Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/36776.
Pełny tekst źródłaStreszczenie:
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 57-58).
We developed the MIT Integrated Microelectronics Device Experimentation and Simulation iLab, a new online laboratory that combines and significantly upgrades the capabilities of two existing online microelectronics labs: WebLab, a device characterization lab, and WebLabSim, a device simulation lab. The new integrated tool allows users to simultaneously run experiments on actual devices and simulations on the virtual ones, as well as to compare the results of the two. In order to achieve this, we considerably extended the capabilities of the original clients. We added the ability to graph the results of multiple experiments and simulations simultaneously, on top of each other, which allows for much easier comparison. We also added the ability to load, view and graph the results of experiments and simulations that were ran at any point in the past, even when the corresponding lab configurations are no longer available. Our hope is that this new integrated iLab will enrich microelectronics teaching and learning by allowing students to compare real life device behavior with theoretical expectations.
by Boris Cukalovic.
M.Eng.
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Fukasaku, Kotaro. "Explorative study for stochastic failure analysis of a roughened bi-material interface: implementation of the size sensitivity based perturbation method". Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/41114.
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In our age in which the use of electronic devices is expanding all over the world, their reliability and miniaturization have become very crucial. The thesis is based on the study of one of the most frequent failure mechanisms in semiconductor packages, the delamination of interface or the separation of two bonded materials, in order to improve their adhesion and a fortiori the reliability of microelectronic devices. It focuses on the metal (-oxide) / polymer interfaces because they cover 95% of all existing interfaces.
Since several years, research activities at mesoscopic scale (1-10µm) have proved that the more roughened the surface of the interface, i.e., presenting sharp asperities, the better the adhesion between these two materials. Because roughness exhibits extremely complex shapes, it is difficult to find a description that can be used for reliability analysis of interfaces. In order to investigate quantitatively the effect of roughness variation on adhesion properties, studies have been carried out involving analytical fracture mechanics; then numerical studies were conducted with Finite Element Analysis. Both were done in a deterministic way by assuming an ideal profile which is repeated periodically.
With the development of statistical and stochastic roughness representation on the one hand, and with the emergence of probabilistic fracture mechanics on the other, the present work adds a stochastic framework to the previous studies. In fact, one of the Stochastic Finite Element Methods, the Perturbation method is chosen for implementation, because it can investigate the effect of the geometric variations on the mechanical response such as displacement field. In addition, it can carry out at once what traditional Finite Element Analysis does with numerous simulations which require changing geometric parameters each time.
This method is developed analytically, then numerically by implementing a module in a Finite Element package MSc. Marc/Mentat. In order to get acquainted and to validate the implementation, the Perturbation method is applied analytically and numerically to the 3 point bending test on a beam problem, because the input of the Perturbation method in terms of roughness parameters is still being studied. The capabilities and limitations of the implementation are outlined.
Finally, recommendations for using the implementation and for furture work on roughness representation are discussed.
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Kornbluth, Yosef S. "Focused atmospheric-pressure microsputterer for additive manufacturing of microelectronics interconnects". Thesis, Massachusetts Institute of Technology, 2018. http://hdl.handle.net/1721.1/118707.
Pełny tekst źródłaStreszczenie:
Thesis: S.M., Massachusetts Institute of Technology, Department of Mechanical Engineering, 2018.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 45-49).
The past decade has seen a new manufacturing revolution, in the form of additive manufacturing. While recent additive manufacturing processes can produce structural materials in intricate shapes not previously possible, additive manufacturing of functional materials remains a challenge. In particular, functional electronics must still be made via traditional lithographic and etching processes. This thesis introduces a microsputtering method to directly write metals with high resolution. A wire feed enables continuous, extended use of the system. We motivate, simulate, and test a novel electrostatic focusing system to improve the resolution of the imprints; this focusing scheme combines electrostatic and fluid effects to direct the sputtered material into a strip as narrow as 9 pm. The microstructure of the deposits, which affects their conductivity, is also explored and modified. Using gold as printable feedstock, this technology allows for smooth (55 nm roughness) deposits with ~65X the electrical conductivity of bulk metal.
by Yosef S. Kornbluth.
S.M.
30
Chiniwalla, Punit Paresh. "Crosslinking of polynorbornene based dielectrics for application in microelectronics". Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/11313.
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Heidelberger, Christopher. "GaAsP/InGaP heterojunction bipolar transistors for III-V on Si microelectronics". Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/113927.
Pełny tekst źródłaStreszczenie:
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Materials Science and Engineering, 2017.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 129-140).
GaAs-based transistors are capable of operating at high frequency with low noise, and are produced in large volumes for a wide range of applications including microwave frequency ICs for input/output in mobile devices. However, Si CMOS still holds an advantage for digital logic due to wide market penetration resulting in decades of development and lower cost. Monolithic integration of III-V analog circuity and Si CMOS gives circuit designers the best of both materials. In addition, by substituting GaAsxP₁-x (0.8 < x < 1) for GaAs as an active material, we can take advantage of its higher breakdown voltage and reduced lattice mismatch with Si. In this thesis, we study GaAsP/InGaP heterojunction bipolar transistors (HBTs) grown via MOCVD as a test-bed for III-V microelectronics integration with Si. Epitaxial challenges involving growth of GaAsP/InGaP HBT structures on Si substrates were addressed. Heavy C p-type doping of GaAsP via MOCVD, necessary for the HBT base region, was studied. Growth rate, composition, and hole concentration dependence on C precursor (CBrCl₃) input was investigated, yielding GaAsP films with hole concentrations in excess of 2 x 10¹⁹ cm-³. GaAs₀₈₂₅P was grown on Si substrates via a SiGe graded buffer with a threading dislocation density of 3.7 x 106 cm-2 measured by PV-TEM and EBIC. This density is appropriate for fabrication of minority-carrier devices such as HBTs. GaAsP/InGaP HBTs were fabricated on both GaAs and Si substrates with a range of defect densities to measure the effect on DC performance and prove the feasibility of GaAsP transistor growth on Si. Models for the effect of threading dislocation density and misfit dislocation density (in the active device layers) on current gain were developed. A GaAsP/InGaP HBT grown on Si was demonstrated with a current gain as high as 158. Changes in GaAsxP₁-x composition from 0.825 < x < 1 did not have a significant effect on current gain. Collector current was determined not to be controlled by thermionic emission of electrons from the emitter into the base, contrary to prior reports. In addition, GaAsP was shown to support a higher breakdown voltage than GaAs, consistent with modeling.
by Christopher Heidelberger.
Ph. D.
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Ardila, Ricardo. "Optimization of three-dimensional branching networks of microchannels for thermal management of microelectronics". FIU Digital Commons, 2009. http://digitalcommons.fiu.edu/etd/1295.
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The aim of this work is to present a methodology to develop cost-effective thermal management solutions for microelectronic devices, capable of removing maximum amount of heat and delivering maximally uniform temperature distributions. The topological and geometrical characteristics of multiple-story three-dimensional branching networks of microchannels were developed using multi-objective optimization.
A conjugate heat transfer analysis software package and an automatic 3D microchannel network generator were developed and coupled with a modified version of a particle-swarm optimization algorithm with a goal of creating a design tool for 3D networks of optimized coolant flow passages. Numerical algorithms in the conjugate heat transfer solution package include a quasi-ID thermo-fluid solver and a steady heat diffusion solver, which were validated against results from high-fidelity Navier-Stokes equations solver and analytical solutions for basic fluid dynamics test cases.
Pareto-optimal solutions demonstrate that thermal loads of up to 500 W/cm2 can be managed with 3D microchannel networks, with pumping power requirements up to 50% lower with respect to currently used high-performance cooling technologies.
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Lin, Yifung 1978. "A collaboration system and a graphical interface for the MIT Microelectronics WebLab". Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/87271.
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Pharr, Matt Mathews. "Diffusion, Deformation, and Damage in Lithium-Ion Batteries and Microelectronics". Thesis, Harvard University, 2014. http://dissertations.umi.com/gsas.harvard:11593.
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This thesis explores mechanical behavior of microelectronic devices and lithium-ion batteries. We first examine electromigration-induced void formation in solder bumps by constructing a theory that couples electromigration and creep. The theory can predict the critical current density below which voids do not form. Due to the effects of creep, this quantity is found to be independent of the solder size and decrease exponentially with increasing temperature, different from existing theories.Engineering and Applied Sciences
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Williams, Gregory A. (Gregory Alan). "Optimization of kitting operations for an automated microelectronics assembly process". Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/34671.
Pełny tekst źródłaStreszczenie:
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Civil and Environmental Engineering; and, (M.B.A.)--Massachusetts Institute of Technology, Sloan School of Management; in conjunction with the Leaders for Manufacturing Program at MIT, 2006.Includes bibliographical references (p. [73]).
Raytheon's Solid-State Microwave (SSM) manufacturing area produces a low-volume, high mix assortment of Microwave Integrated Circuits (MIC) for airborne radars. The current kitting process for pick-and-place assembly is manually-intensive with significant die handling, resulting in multiple opportunities for damage and loss as well as accidental switching of near-identical components. These defects are difficult to detect and are often not discovered until the completed MICs are tested, by which time significant value has been added. The core of this project was to reduce kitting defects, total process cycle time and overall cost through reduction of "touch" labor and kit screenings. The establishment of customized die packaging requirements will result in the optimization of die packaging before the material is received into the storeroom. These new packaging requirements, in combination with the implementation of a point-of-use store for residual materials on the factory floor, enables in large part the elimination of the kitting process, resulting in significant reduction in handling and correlated reductions in lost or damaged parts and "wrong part" defects.
(cont.) This initiative was piloted on a single MIC line, but the solution was designed to be portable to other areas of SSM/SCM kitting operations. This thesis documents the process by which the new process was developed and piloted at Raytheon, as well as the organizational issues and barriers that made the project implementation challenging. In particular, successful implementation of the new processes will require a major shift in organizational thinking towards Total Cost of Ownership and greater cooperation across the boundary between the Solid-State Microwave and Supply Chain Management organizations.
by Gregory A. Williams.
M.B.A.
S.M.
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Volland, Antoine. "Etude des effets d'échelle sur le comportement mécanique de film mince en verre métallique". Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00872887.
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L'absence de structure cristalline dans les verres métalliques tendrait à suggérer qu'aucun effet d'échelle sur leur comportement mécanique ne pourrait exister. Cependant, la diminution de la taille des éprouvettes de verre métallique, principalement solliciter en micro-compression sur des micro-pilliers usiné au FIB à partir de BMG révèlent une transition entre des mécanismes de déformation localisés dans des bandes de cisaillement pour des échelles supérieures à 400 nm et des mécanismes qui présentent des déformations homogènes en dessous de 400 nm. Des interrogations demeurent cependant sur l'impact des procédés d'élaboration des échantillons. Dans cette thèse, on s'intéresse à une autre voie de caractérisation des effets d'échelle sur le comportement mécanique des verres métalliques par l'élaboration et la caractérisation d'éprouvettes obtenues par des procédés de microélectronique dans des films minces de verre métallique de différentes épaisseurs, sans recours à de l'usinage FIB. La structure amorphe et la composition des dépôts réalisés par MS-PVD ont été confirmées par des analyses DRX et MET. L'homogénéité des dépôts entre les différentes épaisseurs a été confirmée par l'invariance du module de Young et du module de cisaillement déterminé par diffusion Brillouin sur chaque épaisseur. Des mesures de nano indentation ont cependant révélé une diminution de la dureté, une augmentation du module de compressibilité et du coefficient de Poisson avec l'augmentation de l'épaisseur des films. L'observation des déformations d'éprouvettes de flexion et des empreintes en nano indentation confirme l'existence d'une taille critique d'éprouvette. Les relations entre les différentes propriétés mécaniques et les observations sur les effets d'échelle sont discutées à partir du modèle des STZ et d'une loi de comportement élasto-plastique parfaite pour toutes les épaisseurs.
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Chaube, Anay. "Self assembly of block copolymers : applicability in microelectronics and gains for patterned media". Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/45348.
Pełny tekst źródłaStreszczenie:
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2008.Includes bibliographical references (leaves 88-93).
As device size decreases, conventional lithographic methods are finding it increasingly hard to keep up. Introduction of newer method such as E-beam, X-ray lithography etc. has demonstrated possibility of scaling to lower dimensions. However most of these methods are too expensive, too complex or too slow. Hence a method is required which can provide high resolutions at low cost, is easy to implement and can be integrated with current processing technologies. Block copolymer self assembly promises to do just that. An immiscible block copolymer will microphase separate into individual domains due to unfavorable mixing enthalpy. These microphase-separated blocks can have domain sizes of very low dimensions, to the order of 15-20 nms. By careful preparation, microphase-separated thin films of immiscible block copolymers can act as nanomasks for a variety of applications in electronic, optoelectronic and storage media fields. One such application is patterned media. With ever increasing areal densities, there is a limit to which the grain size within a bit can be decreased, for a conventional thin film media. Beyond a certain limit, which is dictated by the superparamagnetic effect, these grains will spontaneously reverse, resulting in undesired data loss. Patterned media has been proposed as an alternative to surpass this thermal instability criterion. In patterned media, lithographically defined nano-scale magnetic elements form single bits onto which the data is stored. Due to its unique structure in which each magnetic dots act as a single magnetic domain it can postpone the arrival of superparamagnetic effect beyond densities much higher than 10 Terabits/inch². However, very high resolutions and strict positioning control is required for its fabrication so as to attain a marketable 1Tb/inch² advantage.
(cont.) Block Copolymer self assembly holds great promise in fabrication of such devices requiring periodic, high resolution pattern generation. If issues such as long range order, pattern uniformity and placement accuracy of magnetic dots can be effectively resolved, block copolymer self assembly enabled lithography can quickly become the main stay of the multimillion dollar hard disk industry.
by Anay Chaube.
M.Eng.
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Arora, Samarth. "Low Power Hybrid CMOS-NEMS for Microelectronics: Implementation in Implantable Pacemaker". Case Western Reserve University School of Graduate Studies / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1310676370.
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Smarra, Devin A. "Low Temperature Co-Fired Ceramic (LTCC) Substrate for High Temperature Microelectronics". University of Dayton / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1493386231571894.
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Tavernier, Aurélien. "Développement d'un procédé innovant pour le remplissage des tranchées d'isolation entre transistors des technologies CMOS avancées". Phd thesis, Université de Grenoble, 2014. http://tel.archives-ouvertes.fr/tel-00987019.
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Réalisées au début du processus de fabrication des circuits intégrés, les tranchées d'isolation permettent d'éviter les fuites de courant latérales qui pourraient avoir lieu entre les transistors. Les tranchées sont remplies par un film d'oxyde de silicium réalisé par des procédés de dépôt chimiques en phase vapeur (aussi appelés CVD). Le remplissage des tranchées est couramment réalisé par un procédé CVD à pression sub-atmosphérique (SACVD TEOS/O3). Cependant, la capacité de remplissage de ce procédé pour les nœuds technologiques CMOS 28 nm et inférieurs est dégradée à cause de profils trop verticaux dans les tranchées. Cela induit la formation de cavités dans l'oxyde et entraine des courts-circuits. Afin de pallier ce problème, une nouvelle stratégie de remplissage en trois étapes est proposée pour la technologie CMOS 14 nm. Dans la première étape, un film mince d'oxyde est déposé dans les tranchées. Puis, dans la deuxième étape, les flancs du film sont gravés à l'aide d'un procédé de gravure innovant, basé sur un plasma délocalisé de NF3/NH3, permettant de créer une pente favorable au remplissage final réalisé au cours de la troisième étape. Le développement de cette nouvelle stratégie de remplissage s'est déroulé selon plusieurs axes. Tout d'abord, le procédé de dépôt a été caractérisé afin de sélectionner les conditions optimales pour la première étape de la stratégie. Puis, le procédé de gravure innovant a été caractérisé en détail. L'influence des paramètres de gravure a été étudiée sur pleine plaque et sur plaques avec motifs afin de comprendre les mécanismes de gravure et de changement de pente dans les tranchées. Enfin, dans un troisième temps, la stratégie de remplissage a été développée et intégrée pour la technologie CMOS 14 nm. Nous montrons ainsi qu'il est possible de contrôler le changement de pente avec les conditions de gravure et que cette stratégie permet un remplissage des tranchées d'isolation sans cavités.
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Rivers, Norman. "An Investigation of BGA Electronic Packaging Moiré Interferometry". Scholar Commons, 2003. https://scholarcommons.usf.edu/etd/1459.
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As technology progresses towards smaller electronic packages, thermo-mechanical considerations pose a challenge to package designers. One area of difficulty is the ability to predict the fatigue life of the solder connections. To do this one must be able to accurately model the thermo-mechanical performance of the electronic package. As the solder ball size decreases, it becomes difficult to determine the performance of the package with traditional methods such as the use of strain gages. This is due to the fact that strain gages become limited in size and resolution and lack the ability to measure discreet strain fields as the solder ball size decreases.
A solution to the limitations exhibited in strain gages is the use of Moiré interferometry. Moiré interferometry utilizes optical interferometry to measure small, in-plane relative displacements and strains with high sensitivity. Moiré interferometry is a full field technique over the application area, whereas a strain gage gives an average strain for the area encompassed by the gage. This ability to measure full field strains is useful in the analysis of electronic package interconnections; especially when used to measure strains in the solder ball corners, where failure is known to originate.
While the improved resolution of the data yielded by the method of Moiré interferometry results in the ability to develop more accurate models, that is not to say the process is simple and without difficulties of it's own. Moiré interferometry is inherently susceptible to error due to experimental and environmental effects; therefore, it is vital to generate a reliable experimental procedure that provides repeatable results. This was achieved in this study by emulating and modifying established procedures to meet our specific application. The developed procedure includes the preparation of the specimen, the replication and transfer of the grids, the use of the PEMI, interpretation of results, and validation of data by finite element analysis using ANSYS software. The data obtained maintained uniformity to the extent required by the scope of this study, and potential sources of error have been identified and should be the subject of further research.
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Tunuguntla, Sri Priyanka. "Numerical Study of Thermal Performance of Two-Layered Microchannel Heat Sink with Nanofluids For Cooling of Microelectronics". University of Cincinnati / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1307442807.
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Baudry, Ingwild. "Caractérisation des process de fabrication microélectroniques pour l'éco-conception des futures technologies". Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00957329.
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L'industrie microélectronique est engagée depuis longtemps dans des mesures visant à réduire ses impacts sur l'environnement, et ce sur toutes les phases du cycle de vie de ses produits. Sur les sites de fabrication, la suite logique à la mise en place de système de traitement des pollutions est l'anticipation de ces dernières. L'éco-conception des technologies microélectroniques, c'est-à-dire l'intégration de paramètres environnementaux dans leur processus de développement, permet de répondre à cet objectif. Notre travail de recherche a pour but de caractériser environnementalement les procédés de fabrication microélectronique afin de proposer des outils et méthodes pour leurs concepteurs. Nous avons donc modélisé une technologie microélectronique, et associé des impacts environnementaux aux flux entrants et sortants. Cela nous a permis de proposer des indicateurs environnementaux destinés à la R&D et adaptés à un site de développement et de production microélectronique.
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Hartzell, Brittany M. "DNA manipulation and characterization for nanoscale electronics". Ohio : Ohio University, 2004. http://www.ohiolink.edu/etd/view.cgi?ohiou1108051644.
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Pye, Nathan. "Microfluidic control systems in deep etch optical lithography". Thesis, De Montfort University, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.391693.
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Thornell, Mark E. "Sample fabrication and experimental design for studying interfacial creep at thin film/silicon interfaces". Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2004. http://library.nps.navy.mil/uhtbin/hyperion/04Mar%5FThornell.pdf.
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Song, Ingu. "Role of carbon dioxide in gas expanded liquids for removal of photoresist and etch residue". Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/26473.
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Thesis (Ph.D)--Chemical Engineering, Georgia Institute of Technology, 2008.Committee Chair: Hess, Dennis; Committee Member: Eckert, Charles; Committee Member: Frazier, Bruno; Committee Member: Henderson, Clifford; Committee Member: Liotta, Charles. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Peng, Der Liang, i 彭德亮. "Computer Aided Concurrent Engineering: Microelectronic Product Application". Thesis, 1995. http://ndltd.ncl.edu.tw/handle/96841123349977660570.
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碩士國立清華大學
工業工程研究所
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Concurrent product and process development is a fundamental determinant with which the technology-based companies bring the product successfully to market and gain the sustaining competitive advantages. The actual adaptation and regular practice of such a development process, however, has been sparse despite the wide recognition of the need. Since one of the key function of the tool is to provide the ability to recast the sequential process to a concurrent process in a life cycle framework, which enable the planning , managing, and controlling the impact of upstream and downstream constraints; the generative models need to have the following features: descriptive, prescriptive, and executable.
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Mohtar, Aaron. "A remote laboratory for testing microelectronic circuits on silicon wafers". 2009. http://arrow.unisa.edu.au/vital/access/manager/Repository/unisa:38670.
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This thesis explores the technical feasibilty of creating a remote laboratory in the field of microelectronics fabrication. It also includes the evaluation of the developed laboratory as a teaching tool.PhDElectronicEngineering
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Lum, Ivan. "Effects of Ultrasound in Microelectronic Ultrasonic Wire Bonding". Thesis, 2007. http://hdl.handle.net/10012/3439.
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Ultrasonic wire bonding is the most utilized technique in forming electrical interconnections in microelectronics. However, there is a lacking in the fundamental understanding of the process. In order for there to be improvements in the process a better understanding of the process is required.
The mechanism of the bond formation in ultrasonic wire bonding is not known. Although there have been theories proposed, inconsistencies have been shown to exist in them. One of the main inconsistencies is the contribution of ultrasound to the bonding process.
A series of experiments to investigate the mechanism of bond formation are performed on a semi automatic wire bonder at room temperature. 25 µm diameter Au wire is ball bonded and also 25 µm diameter Al wire is wedge-wedge bonded onto polished Cu sheets of thickness 2 mm. It is found that a modified microslip theory can describe the evolution of bonding. With increasing ultrasonic power the bond contact transitions from microslip into gross sliding. The reciprocating tangential relative motion at the bond interface results in wear of surface contaminants which leads to clean metal/metal contact and bonding.
The effect of superimposed ultrasound during deformation on the residual hardness of a bonded ball is systematically studied for the first time. An innovative bonding procedure with in-situ ball deformation and hardness measurement is developed using an ESEC WB3100 automatic ball bonder. 50 µm diameter Au wire is bonded at various ultrasound levels onto Au metallized PCB substrate at room temperature. It is found that sufficient ultrasound which is applied during the deformation leads to a bonded ball which is softer than a ball with a similar amount of deformation without ultrasound. No hardening of the 100 µm diameter Au ball is observed even with the maximum ultrasonic power capable of the equipment of 900 mW.
In summary, the fundamental effect of ultrasound in the wire bonding process is the reciprocating tangential displacement at the bond interface resulting in contaminant dispersal and bonding. A second effect of ultrasound is the softening of the bonded material when compared to a similarly non-ultrasound deformed ball.