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Al-Amin, Chowdhury G. "Advanced Graphene Microelectronic Devices". FIU Digital Commons, 2016. http://digitalcommons.fiu.edu/etd/2512.
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The outstanding electrical and material properties of Graphene have made it a promising material for several fields of analog applications, though its zero bandgap precludes its application in digital and logic devices. With its remarkably high electron mobility at room temperature, Graphene also has strong potential for terahertz (THz) plasmonic devices. However there still are challenges to be solved to realize Graphene’s full potential for practical applications.
In this dissertation, we investigate solutions for some of these challenges. First, to reduce the access resistances which significantly reduces the radio frequency (RF) performance of Graphene field effect transistors (GFETs), a novel device structure consisting of two additional contacts at the access region has been successfully modeled, designed, microfabicated/integrated, and characterized. The additional contacts of the proposed device are capacitively coupled to the device channel and independently biased, that induce more carriers and effectively reduce access resistance.
In addition to that, in this dissertation, bandgap has been experimentally introduced to semi-metallic Graphene, by decorating with randomly distributed gold nano-particles and zinc oxide (ZnO) nano-seeds, where their interaction breaks its sublattice symmetry and opens up bandgap. The engineered bandgap was extracted from its temperature dependent conductivity characteristics and compared with reported theoretical estimation. The proposed method of device engineering combined with material bandgap engineering, on a single device, introduces a gateway towards high speed Graphene logic devices.
Finally, THz plasmon generation and propagation in Graphene grating gate field effect transistors and Graphene plasmonic ring resonators have been investigated analytically and numerically to explore their potential use for compact, solid state tunable THz detectors.
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Burrows, Susan Elizabeth. "Silicone encapsulants for microelectronic devices". Thesis, University of Warwick, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.319702.
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Ramon, i. Garcia Eloi. "Inkjet printed microelectronic devices and circuits". Doctoral thesis, Universitat Autònoma de Barcelona, 2014. http://hdl.handle.net/10803/285078.
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En els darrers anys ha anat creixent l’interès per la fabricació de sistemes de baix cost, flexibles i sobre gran àrea com, per exemple, les etiquetes RFID per a identificació de productes, les pantalles flexibles o les etiquetes intel•ligents entre d’altres. La tecnologia d’impressió electrònica (Printed Electronics) s’ha posicionat com una de les tecnologies alternatives de fabricació més prometedores pel fet de no utilitzar tècniques fotolitogràfiques i de buit. Alhora, la millora en materials orgànics i inorgànics ha provocat un increment en les prestacions dels dispositius impresos. Tot i això, la fabricació de transistors orgànics, element clau per a construir circuits electrònics d’adquisició o processament, es veu afectada per la poca resolució i registre entre capes de les tecnologies d’impressió actuals com inkjet o gravat. Per compensar-ho, els transistors implementats utilitzant aquestes tecnologies tenen llargades de canal molt grans i grans solapaments entre porta i font/drenador. Aquestes grans dimensions limiten les prestacions dels transistors impresos, tot i les millores obtingudes en els materials.
Aquesta tesi està enfocada en contrarestar els problemes provocats per la poca resolució en impressió utilitzant tècniques de compensació i noves geometries de dispositius mantenint el procés completament inkjet. Aquest treball s’enfoca en el desenvolupament de dispositius microelectrònics passius i actius implementats amb maquinària inkjet de baix cost. He enfocat el meu esforç en el disseny, la fabricació i la caracterització (elèctrica i morfològica) amb l’objectiu de fer possible la fabricació de circuits integrats orgànics.
En el marc de la tesi, s’han fabricat varis milers de transistors, capacitats i resistències exclusivament amb tecnologia inkjet. Tots els dispositius s’han caracteritzat tant elèctrica com morfològicament. S’ha dut a terme un gran número d’experiments per assegurar una fabricació eficient, estudiar la variabilitat dels paràmetres i obtenir dades estadísticament significatives. La variació en els processos de fabricació de transistors porta a una important variabilitat en els paràmetres dels dispositius impresos fins ara poc estudiada. Escalabilitat, variabilitat i rendiment s’han analitzat utilitzant diferents estratègies.
S’han obtingut circuits digitals amb un comportament adient, demostrant l’estat actual de la tecnologia inkjet per a integrar dispositius impresos en circuits. Aquest és un primer pas en el camí per fabricar circuits més complexes amb tecnologia d’impressió inkjet.
La quantitat de mostres fabricades amb tecnologia inkjet es pot considerar com un assoliment important i contribueix a millorar el coneixement del comportament i els orígens de fallades dels dispositius orgànics i impresos.In the last years there has been a growing interest in the realization of low-cost, flexible and large area electronic systems such as item-level RFID tags, flexible displays or smart labels, among others. Printed Electronics has emerged as one of the most promising alternative manufacturing technologies due to its lithography- and vacuum-free processing. Related to this, organic and inorganic solution processed materials advanced rapidly improving the performance of printed devices. However, the fabrication of organic transistors, key element to build circuits for acquisition and processing, suffers from the poor resolution and layer-to-layer registration of current printing techniques such as inkjet and gravure printing. To compensate that transistors implemented in those technologies have large channel lengths and large gate to source/drain overlaps. These large dimensions limit the performance of the printed transistors, despite the improvements in materials. This thesis focuses on circumventing the printing resolution challenges using compensation techniques and new layout geometries while keeping an all-inkjet purely printing process. The dissertation deals with the development of microelectronic passive and active devices implemented using low-cost inkjet printing machinery. I focussed my effort in the design, manufacturing & characterization (electrical and morphological) points of view in order to allow the fabrication of organic integrated circuits. Several thousands of resistors, capacitors and transistors were fabricated, all of them fully inkjet-printed. All devices were morphologically and electrically characterized. A high number of experiments were developed to ensure efficient manufacturing and report on parameter variation, thus obtaining statistically significant data. Process variations present in transistor fabrication lead to a certain variability on the resulting transistor parameters that need to be taken in account. Scalability, variability and yield were analysed by using different strategies. Fabricated inverters show a clear inversion behaviour demonstrating the state of the inkjet fabrication process to integrate printed devices in circuits. This is a first step in the way to fabricate all-inkjet complex circuits. The amount of samples manufactured by the fully inkjet printing approach can be considered an outstanding achievement and contributes to a better knowledge of the behaviour and failure origins of organic and printed devices.
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Solis, Adrian (Adrian Orbita). "MIT Device Simulation WebLab : an online simulator for microelectronic devices". Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/33364.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2005.Includes bibliographical references (p. 149-157).
In the field of microelectronics, a device simulator is an important engineering tool with tremendous educational value. With a device simulator, a student can examine the characteristics of a microelectronic device described by a particular model. This makes it easier to develop an intuition for the general behavior of that device and examine the impact of particular device parameters on device characteristics. In this thesis, we designed and implemented the MIT Device Simulation WebLab ("WeblabSim"), an online simulator for exploring the behavior of microelectronic devices. WeblabSim makes a device simulator readily available to users on the web anywhere, and at any time. Through a Java applet interface, a user connected to the Internet specifies and submits a simulation to the system. A program performs the simulation on a computer that can be located anywhere else on the Internet. The results are then sent back to the user's applet for graphing and further analysis. The WeblabSim system uses a three-tier design based on the iLab Batched Experiment Architecture. It consists of a client applet that lets users configure simulations, a laboratory server that runs them, and a generic service broker that mediates between the two through SOAP-based web services. We have implemented a graphical client applet, based on the client used by the MIT Microelectronics WebLab.
(cont.) Our laboratory server has a distributed, modular design consisting of a data store, several worker servers that run simulations, and a master server that acts as a coordinator. On this system, we have successfully deployed WinSpice, a circuit simulator based on Berkeley Spice3F4. Our initial experiences with WeblabSim indicate that it is feature-complete, reliable and efficient. We are satisfied that it is ready for beta deployment in a classroom setting, which we hope to do in Fall 2004.
by Adrian Solis.
M.Eng.
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Reska, Anna. "Interfacing insect neuronal neutworks with microelectronic devices". Jülich Forschungszentrum, Zentralbibliothek, 2009. http://d-nb.info/1000321983/34.
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Sanderson, Lisa. "Nanoscale strain characterisation of modern microelectronic devices". Thesis, University of Newcastle upon Tyne, 2012. http://hdl.handle.net/10443/1541.
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Sources of stress and strain in modern microelectronics can be either beneficial to the electrical performance or detrimental to the mechanical integrity and ultimately lifetime of the device. Strain engineering is commonplace in state-of-the-art device fabrication as a means to boost performance in the face of device scaling limitation. The strain present in the device is directly related to the improvement factor and as such precise measurements and good understanding are of utmost importance due to the many thermal processing steps that can induce or cause relaxation of the strain. Front-end-of-line (FEOL) strain characterisation is becoming increasingly challenging due to the small volumes of material and nanoscale feature sizes being analysed. In this work, an extensive survey of strain characterisation techniques was undertaken. Narrow sSOI stripes were profiled using conventional Raman spectroscopy. Unlike with previous studies, it was shown that it is possible to achieve nanoscale measurements using current techniques. This study was supported by ANSYS FE simulation. The review of the literature briefly investigates the possibility of EBSD as a strain measurement tool. It is possible to calculate not just an absolute strain value as achievable with Raman spectroscopy, but the strain tensor. However, this is a difficult and complex process and not necessary for use in industry. This study proposes the possibility of a more simple method that would provide a good calibration technique to confirm Raman measurements. SERS and TERS are explored in detail as the most promising techniques when dealing with device scaling. Currently, SERS is a destructive technique not suitable for use in a highly cost driven industry such as semiconductor manufacturing. While it theoretically gives improved surface selectivity over conventional Raman spectroscopy, there is no improvement to the xy spatial resolution. With Si and SiGe samples, this study concludes there is also often no surface selectivity with either technique and the mechanisms behind the enhancement are not understood to the point of being able to implement the techniques in a process line. However, where a non-destructive technique is desired, outlined in this study is a method of achieving the SERS effect without sacrificing the sample. Aggressive scaling has forced the dimensions of the interconnecting wires that give the devices functionality to the deep submicron range. Copper, Cu has been introduced as a replacement to the traditionally used aluminium, Al because of its superior electrical and mechanical properties and scalability. However, as these wires begin to approach the dimensions of thin foils, the microtexture of the wires becomes significantly different from their bulk counterparts. This can affect the mechanical integrity of the interconnects and this has an impact on the reliability of the device. Failure mechanisms such as blistering, cracking and peeling caused by stress and strain are not uncommon and traditional methods of characterising residual stress in the thin films is no longer applicable to these narrow wires. The mechanical properties and microtexture of thin copper films annealed at temperatures comparative to those found in device manufacturing were characterised in some detail. EBSD was used to determine the grain size and structure of the films before nanoindentation confirmed properties such as hardness and elastic modulus. These results pave the way for investigation of strain applied along deep-submicron interconnects to lead to further understanding of what causes failure mechanisms from interconnecting wires.
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Limpaphayom, Koranan. "Microelectronic circuits for noninvasive ear type assistive devices". College Park, Md.: University of Maryland, 2009. http://hdl.handle.net/1903/9887.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2009.Thesis research directed by: Reliability Engineering Program. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Clarke, Warrick Robin Physics Faculty of Science UNSW. "Quantum interaction phenomena in p-GaAs microelectronic devices". Awarded by:University of New South Wales. School of Physics, 2006. http://handle.unsw.edu.au/1959.4/32259.
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In this dissertation, we study properties of quantum interaction phenomena in two-dimensional (2D) and one-dimensional (1D) electronic systems in p-GaAs micro- and nano-scale devices. We present low-temperature magneto-transport data from three forms of low-dimensional systems 1) 2D hole systems: in order to study interaction contributions to the metallic behavior of 2D systems 2) Bilayer hole systems: in order to study the many body, bilayer quantum Hall state at nu = 1 3) 1D hole systems: for the study of the anomalous conductance plateau G = 0.7 ???? 2e2/h The work is divided into five experimental studies aimed at either directly exploring the properties of the above three interaction phenomena or the development of novel device structures that exploit the strong particle-particle interactions found in p-GaAs for the study of many body phenomena. Firstly, we demonstrate a novel semiconductor-insulator-semiconductor field effect transistor (SISFET), designed specifically to induced 2D hole systems at a ????normal???? AlGaAs-on-GaAs heterojunction. The novel SISFETs feature in our studies of the metallic behavior in 2D systems in which we examine temperature corrections to ????xx(T) and ????xy(T) in short- and long-range disorder potentials. Next, we shift focus to bilayer hole systems and the many body quantum Hall states that form a nu = 1 in the presence of strong interlayer interactions. We explore the evolution of this quantum Hall state as the relative densities in the layers is imbalanced while the total density is kept constant. Finally, we demonstrate a novel p-type quantum point contact device that produce the most stable and robust current quantization in a p-type 1D systems to date, allowing us to observed for the first time the 0.7 structure in a p-type device.
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Heng, Stephen Fook-Geow. "Experimental and theoretical thermal analysis of microelectronic devices". Diss., Georgia Institute of Technology, 1988. http://hdl.handle.net/1853/16694.
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Thongpang, Sanitta. "Vacuum field emission microelectronic devices based on silicon nanowhiskers". Thesis, University of Canterbury. Electrical and Computer Engineering, 2007. http://hdl.handle.net/10092/1141.
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Vacuum field emission devices have become a promising candidate for emerging display technology due to their interesting properties compared to conventional thermionic emission devices that require high temperature and power to operate. Unlike thermionic emission, field emission devices can induce the electrons to emit at low temperature; sharp and thin emitters on the cathode are desired in order to increase the field emission. Many candidates from other research groups, such as Carbon Nanotubes (CNTs), SiC and ZnO, appear to have high field emission, but their complicated fabrication processes are the drawback. The silicon nanowhiskers produced by Geological & Nuclear Sciences (GNS) using Electron-Beam Rapid Thermal Annealing (EB-RTA) are an alternative material that is fast, inexpensive and uncomplicated to produce. They are based on the thermal desorption of silicon oxide, which forms silicon nanowhiskers on the silicon wafer in a short duration. Field emission diode structures on Silicon on Insulator (SOI) wafers were fabricated in order to investigate the field emission due to these GNS silicon nanowhiskers. An uncomplicated fabrication process using photolithography and etching process was developed. Electron beam lithography (EBL) was also used to create the different feature sizes directly onto the SOI wafer. The silicon nanowhiskers grown on these structures are as high as 35 nm with density distribution up to 30 µm⁻¹. The electrical characteristics of these devices are diode-like when the voltage range from -40 V to 40 V is applied. The best samples produced an emitted current as high as 2 mA, which is suitable for many applications, such as flat panel displays, x-ray sources and high frequency devices. However, in some cases, the diode structures failed to show the diode-like characteristics, perhaps as a result of bad contact connections or the emitters have been worn out after applying high voltage for some time. Device life time and stability were also considered and investigated via a number of electrical measurements for a period of time as long as one hour in this study. Even though these nanowhiskers have shown promising results, there are still many aspects to be considered to improve the experiments, such as the vacuum system and better contacts.
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León, Cerro Javier. "Advanced analysis of microelectronic devices and systems by lock-in IR thermography". Doctoral thesis, Universitat Autònoma de Barcelona, 2016. http://hdl.handle.net/10803/392687.
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Desde los inicios de la revolución microelectrónica, su evolución tecnológica siempre se ha visto marcada por la búsqueda constante de dispositivos y sistemas electrónicos monolíticos más compactos, fiables y robustos, ofreciendo mejores prestaciones y funcionalidades a un coste razonable. Ello no sólo ha permitido su uso para complementar o sustituir en muchas aplicaciones a otros sistemas basados en elementos mecánicos, electromecánicos, hidráulicos, y neumáticos (sistemas de comunicación, more electric aircrafts o tracción ferroviaria), sino que también ha dado lugar a nuevos conceptos o campos de aplicación (internet of things o vehiculos autónomos) afrontando retos sociales. Todo ello ha conllevado ciertos contratiempos relacionados con los procesos de fabricación, fiabilidad, y caracterización de dispositivos y sistemas electrònicos monolíticos, superados gracias al acceso al xip ofrecido por los pads de interconexión. No obstante, la accesibilidad local a todo el chip no es posible externamente, y esta situación se ha visto agravada por la alta capacidad de integración monolítica actual. En este escenario, la caracterización externa no invasiva local mediante técnicas de imagen se ha convertido en una solución muy prometedora.
Esta tesis doctoral propone estudiar térmicamente la superficie de dispositivos o sistemas microelectrónicos mediante un sistema de termografía infrarroja (TIR) por imagen aplicando estrategias de detección lock-in. Cuando se modulan fuentes de calor en frecuencia, la detección lock-in mejora ostensiblemente la sensibilidad del sistema (por debajo de los niveles de ruido de la cámara infrarroja) y, en función del tipo de modulación y su frecuencia, sin influencia alguna de las condiciones de contorno ni de los efectos de “desenfoque” (blurring effects) debidos a la propagación de calor (heat spreading effect). En consecuencia, la monitorización local de fuentes débiles de calor es factible a nivel chip, no tan sólo para realizar análisis de fallos (principal tendencia en el estado del arte), sino que también para la caracterización local eléctrica en frecuencia, extracción de figuras de mérito, o determinación de parámetros físicos de un dispositivo o sistema integrado (novedad propuesta en esta tesis doctoral). Así, se proporciona una alternativa i un enfoque novedoso para la caracterización local a nivel chip.
Para llevar a cabo esta investigación, ha sido primordial la comprensión de la física de las medidas realizadas, el diseño e implementación de instrumentación adicional para polarizar eléctrica y térmicamente la muestra, y la puesta a punto de un sistema TIR, optimizando su proceso de adquisición. Para mostrar la potencialidad de la solución propuesta, se han analizado los siguientes casos de estudio:
i) caracterización de parásitos de interconexión y de acoplo por sustrato a nivel encapsulado y chip, respectivamente;
ii) mecanismos de fallo de diodos de potencia de gap ancho (WBG) bajo condiciones de sobrecarga,
iii) estudio local del comportamiento eléctrico anómalo en dispositivos de potencia WBG,
iv) caracterización local eléctrica y térmica de amplificadores de potencia para RF y microondas,
v) análisis funcional y de consumo sistemas sensores integrados RFID inalámbricos.
Las conclusiones de cada estudio han sido proporcionadas a los diseñadores del dispositivo o sistema inspeccionado para mejorar sus prestaciones o robustez. Se ha puesto de manifiesto que la solución propuesta es una herramienta potente e innovadora, no sólo para el análisis de fallos, sino que también para extraer los parámetros físicos locales en dispositivos y caracterizar eléctrica y funcionalmente sistemas microelectrónicos complejos. Además, las metodologías presentadas son extrapolables a otros equipos de medida de temperatura con mayor resolución espacial.Since the microelectronic revolution, its technological evolution has been aimed at searching for more compact, reliable, and rugged electronic devices or integrated systems, offering as much performances and functionalities as possible at a lower cost. This has not only allowed them to complement or replace in many applications other systems based on mechanic, electromechanic, hydraulic, and pneumatic principles (e.g., communication systems, more electric aircrafts or railway traction), but also has fostered innovating working scenarios (e.g., internet of things or autonomous vehicles) facing societal challenges. However, these targets entailed several consequences in terms of microelectronic devices and systems manufacturability (optimize fabrication process), reliability (virtual prototyping), and testability (system assessment and performance evaluation), in which local functional inspection is crucial and partially ensured by accessing pads. However, local accessibility to the whole die is not possible externally, and has been worsened by the current monolithical integration capabilities, posing new challenges in the reliability and performance assessment at die level. In this scenario, local off-chip characterization with non-invasive spatially-resolved imaging techniques has become one of the most promising solutions. As a solution to such problems in more-than-Moore domain, this work proposes to thermally study the surface of such Microelectronic devices and systems with an imaging infrared thermography (IRT) system by applying lock-in detection strategies. When modulating heat sources in frequency, lock-in detection improves the sensitivity of the IRT system, and depending on the modulation and frequency, allows sensing thermal variations below noise equivalent thermal difference (NETD) limit of the camera, without any influence of boundary conditions and blurring effects due to heat spreading. Consequently, acquired thermal maps make possible locally monitoring weak heat sources not only for failure analysis (mainstream use, state-of-the-art), but also for electrical testing in frequency domain, figures of merit extraction, or device physical parameters determination (novelty of this work). Facing these challenges have supposed understanding the Physics underlying the performed measurements, designing and implementing a thermal and electrical biasing system for the samples, and setting up an Infrared Lock-in Thermography (IR-LIT) system, optimizing the thermal image acquisition procedure. In order to access the potential in the current Microelectronic scenario, the following case studies have been addressed (going from less to more complex situations): i) intradie and packaging parasitic phenomena inspection (parasitics deembedding), ii) wide bandgap (WBG) power devices failure analysis under overload conditions, iii) local abnormal electrical behavior study in WBG power devices , iv) thermal and electrical local testing of microwaves and RF power amplifiers, v) functional and consumption analysis of RFID wireless pad-free sensor systems. When required, the main conclusions of each study have been feedback to design engineers to improve or make more rugged the inspected device or system. As a result, the proposed approach has been assessed and demonstrated as a powerful and innovative tool, not only for failure analysis and electrical parameters extraction in power electronics, but also to perform a deeper behavioral study on more complex microelectronic systems to determine their possible electrical misbehaviors and propose design improvements. Besides, the presented approaches do not reduce to infrared acquisition systems, but also allow being implemented with any thermal monitoring equipment with higher spatial resolution.
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Reska, Anna [Verfasser]. "Interfacing insect neuronal neutworks with microelectronic devices / vorgelegt von Anna Magdalena Reska". Jülich : Forschungszentrum, Zentralbibliothek, 2009. http://d-nb.info/1000321983/34.
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Liu, Liyu. "Design and fabrication of microfluidic/microelectronic devices from nano particle based composites /". View abstract or full-text, 2008. http://library.ust.hk/cgi/db/thesis.pl?NSNT%202008%20LIU.
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Blanco, Agnes M. Padovani. "Low dielectric constant porous spin-on glass for microelectronic applications". Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/11840.
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Köck, Helmut [Verfasser]. "Experimental and numerical study on heat transfer problems in microelectronic devices / Helmut Köck". Aachen : Shaker, 2013. http://d-nb.info/1049382048/34.
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Monadgemi, Pezhman. "Polymer-Based Wafer-Level Packaging of Micromachined HARPSS Devices". Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11473.
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This thesis reports on a new low-cost wafer-level packaging technology for microelectromechanical systems (MEMS). The MEMS process is based on a revised version of High Aspect Ratio Polysilicon and Single Crystal Silicon (HARPSS) technology. The packaging technique is based on thermal decomposition of a sacrificial polymer through a polymer overcoat followed by metal coating to create resizable MEMS packages. The sacrificial polymer is created on top of the active component including beams, seismic mass, and electrodes by photodefining, dispensing, etching, or molding. The low loss polymer overcoat is patterned by photodefinition to provide access to the bond pads. The sacrificial polymer decomposes at temperatures around 200-280aC and the volatile products permeate through the overcoat polymer leaving an embedded air-cavity. For MEMS devices that do not need hermetic packaging, the encapsulated device can then be handled and packaged like an integrated circuit. For devices that are sensitive to humidity or need vacuum environment, hermiticity is obtained by deposition and patterning thin-film metals such as aluminum, chromium, copper, or gold.
To demonstrate the potential of this technology, different types of capacitive MEMS devices have been designed, fabricated, packaged, and characterized. These includes beam resonators, RF tunable capacitors, accelerometers, and gyroscopes. The MEMS design includes mechanical, thermal, and electromagnetic analysis. The device performance, before and after packaging is compared and the correlation to the model is presented.
The following is a summary of the main contributions of this work to the extensive research focused on MEMS and their packaging:
1)A new low-cost wafer-level packaging method for bulk or surface micromachined devices including resonators, RF passives and mechanical sensors is reported. This technique utilizes thermal decomposition of a sacrificial polymer through an overcoat polymer to create buried channels on top of the resonant/movable parts of the micromachined device. It provides small interconnections together with resizable package dimensions. We report MEMS package thicknesses in the range of 10 mm to 1 mm, and package size from 0.0001 mm to 1 mm.
2)A revised version of the HARPSS technology is presented to implement high aspect ratio silicon capacitors, resonators and inertial sensors in the smallest area.
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Kohl, Michael. "An experimental investigation of microchannel flow with internal pressure measurements". Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-06072004-131239/unrestricted/kohl%5Fmichael%5F200405%5Fphd.pdf.
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Weigel, Stefan. "Primary neuronal culture of Locusta migratoria for construction of networks on microelectronic recording devices". [S.l.] : [s.n.], 2006. http://deposit.ddb.de/cgi-bin/dokserv?idn=98245774X.
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Varghese, J. (Jobin). "MoO₃, PZ29 and TiO₂ based ultra-low fabrication temperature glass-ceramics for future microelectronic devices". Doctoral thesis, Oulun yliopisto, 2019. http://urn.fi/urn:isbn:9789526222172.
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Abstract This thesis describes a detailed investigation of new glass 10Li₂O−10Na₂O−20K₂O−60MoO₃ (LNKM), ceramic (α-MoO₃) and ceramic-commercial glass (PZ29-GO17, rutile TiO₂-GO17) composites to satisfy the future requirements for ultra-low fabrication temperature materials and their associated processes. The initial part of the thesis is devoted to the development of the LNKM glass by a glass-melting and quenching process, followed by an investigation into its structural, microstructural and microwave dielectric properties. The prepared glass had ultra-low glass transition and melting temperatures of 198 and 350 °C, respectively. The glass pellet heat-treated at 300 °C had a relative permittivity (εr) of 4.85 and a dielectric loss (tan δ) of 0.0009 at 9.9 GHz. The temperature dependence of the relative permittivity was (τε) 291 ppm/°C. Another part of the work concerns α-MoO₃ ceramic, its preparation by uniaxial pressing and sintering at 650 °C followed by an investigation of its structural, microstructural, thermal and microwave dielectric properties. It had an εr of 6.6, tan δ of 0.00013 (at 9.9 GHz) and τε of 140 ppm/°C. In addition to this, a functional ultra-low temperature co-fired composite was developed based on commercial PZ29 and 50 wt.% of GO17 glass followed by tape casting and co-firing with Ag at 450 °C. The average values of the piezoelectric (d₃₃) and voltage (g₃₃) coefficients were 17 pC/N and 30 mV/N, respectively. The sintered sample had an average CTE value of 6.9 ppm/°C measured in the temperature range of 100–300 °C. The εr and tan δ of the sintered substrates were 57.8 and 0.05 at 2.4 GHz, respectively. Additionally, a new ceramic-glass composite was developed using rutile TiO₂-GO17, and co-fired with Ag at 400 °C. It had an average CTE value of 8.3 ppm/°C measured in the temperature range of 100–300 °C. This composite substrate showed εr of 15.5 and tan δ 0.003, at 9.9 GHz. Moreover, it also had τε of -400 ppm/°C at 9.9 GHz measured in the temperature range of −40 to 80 °C. The findings of the thesis reveal the feasibility of the ultra-low temperature co-fired ceramic (ULTCC) technology for high-frequency telecommunication devices as well as for electronics packages. Additionally, a first step to develop functional ULTCC has been takenTiivistelmä Tässä väitöskirjassa kuvataan uuden lasin 10Li₂O−10Na₂O−20K₂O−60MoO₃ (LNKM), keraamin (α-MoO₃) sekä keraami-lasi (PZ29-GO17, rutiili TiO₂-GO17) komposiittien tutkimustulokset, jotka mahdollistavat tulevaisuuden sähkökeraamisten materiaalien ja komponenttien valmistuksen ultra-matalissa valmistuslämpötiloissa. Väitöskirjan alkuosa keskittyy LNKM lasin kehitykseen lasin sulatus- ja karkaisuprosessilla, sekä tämän materiaalin mikrorakenteen sekä mikroaaltoalueen dielektristen ominaisuuksien tarkasteluun. Valmistetulla lasilla oli ultra-matala lasittumislämpötila 198 °C sekä sulamislämpötila 350 °C. Lasipelletin, joka lämpökäsiteltiin 300 °C:ssa, suhteellinen permittiivisyys (εr) oli 4,85 ja dielektriset häviöt (tan δ) 0,0009 9,9 GHz taajuudella. Suhteellisen permittiivisyyden lämpötilariippuvuus (τε) oli 291 ppm/°C. Toinen osa työtä käsittelee α-MoO₃ keraamia, josta valmistettiin näytteet mikrorakenne ja mikroaaltoalueen dielektristen ominaisuuksien tutkimuksiin aksiaalisella puristuksella ja sintraamalla 650 °C:ssa. Valmistetun materiaalin suhteellinen permittiivisyys oli 6,6, häviöt 0,00013 (9,9 GHz:ssa) ja permittiivisyyden lämpötilariippuvuus 140 ppm/°C. Näiden lisäksi kehitettiin toiminnallinen ultra-matalan lämpötilan yhteissintrattu komposiitti perustuen kaupalliseen pietsosähköiseen keraamiin (PZ29) ja lasiin (GO17). Komposiitista valmistetiin monikerrosrakenne nauhavalulla ja yhteissintraamalla hopeaelektrodien kanssa 450 °C:ssa. Keskimääräiset arvot pietsosähköiselle varausvakiolle (d₃₃) sekä jännitevakiolle (g₃₃) olivat 17 pC/N ja 30 mV/N. Sintratun näytteen keskimääräinen lämpölaajenemiskerroin oli 8,3 ppm/°C lämpötila-alueella 100–300 °C. Tämän komposiittisubstraatin suhteellinen permittiivisyys oli 15,5 ja häviötangentti 0,003 9,9 GHz:n taajuudella. Lisäksi suhteellisen permittiivisyyden lämpötilariippuvuus oli -400 ppm/°C samalla 9,9 GHz:n taajuudella, kun lämpötilan mittausalue oli −40–80 °C. Tämän väitöstyön tulokset osoittavat ultra-matalan lämpötilan yhteissintrattavan keraamiteknologian (ULTCC) soveltuvuuden korkean taajuuden tietoliikennesovelluksiin ja elektroniikan pakkausteknologiaan. Lisäksi työssä on otettu ensimmäiset askeleet funktionaalisten ULTCC materiaalien kehittämiseksi
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Loik, V. B., V. Havrysh i L. Kolyasa. "Non-linear mathematical 3D model of determination of temperature field in elements of microelectronic devices (Scopus)". Thesis, XIІI International Scientific and Technical Conference “Computer Sciences and Information Technologies” CSIT 2018, 2018. http://hdl.handle.net/123456789/5324.
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Krundel, Ludovic. "On microelectronic self-learning cognitive chip systems". Thesis, Loughborough University, 2016. https://dspace.lboro.ac.uk/2134/21804.
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After a brief review of machine learning techniques and applications, this Ph.D. thesis examines several approaches for implementing machine learning architectures and algorithms into hardware within our laboratory. From this interdisciplinary background support, we have motivations for novel approaches that we intend to follow as an objective of innovative hardware implementations of dynamically self-reconfigurable logic for enhanced self-adaptive, self-(re)organizing and eventually self-assembling machine learning systems, while developing this new particular area of research. And after reviewing some relevant background of robotic control methods followed by most recent advanced cognitive controllers, this Ph.D. thesis suggests that amongst many well-known ways of designing operational technologies, the design methodologies of those leading-edge high-tech devices such as cognitive chips that may well lead to intelligent machines exhibiting conscious phenomena should crucially be restricted to extremely well defined constraints. Roboticists also need those as specifications to help decide upfront on otherwise infinitely free hardware/software design details. In addition and most importantly, we propose these specifications as methodological guidelines tightly related to ethics and the nowadays well-identified workings of the human body and of its psyche.
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Valdes, Abel. "Development of laser ultrasonic and interferometric inspection system for high-volume on-line inspection of microelectronic devices". Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29685.
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Thesis (M. S.)--Mechanical Engineering, Georgia Institute of Technology, 2009.Committee Chair: Ume, I. Charles; Committee Member: Kalaitzidou, Kyriaki; Committee Member: Mayor, J. Rhett. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Liang, Hongwei. "Development of microwave and millimeter-wave pin grid array and ball grid array packages". Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14867.
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Liu, Yi Johnson R. Wayne. "Packaging of silicon carbide high temperature, high power devices processes and materials /". Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Spring/doctoral/LIU_YI_31.pdf.
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Reading, Michael Alexander. "The application of MEIS for the physical characterisation of high-k ultra thin dielectric layers in microelectronic devices". Thesis, University of Salford, 2010. http://usir.salford.ac.uk/26876/.
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During the last decade the use of 8162 as gate dielectric layers in complementary metal oxide semiconductor (CMOS) microelectronic devices has become increasingly problematic due to leakage resulting from the electron tunnelling with gate oxide thickness approaching 1 nm. Approaches to deal with these problems have focused on increasing the dielectric constant (k) of the material, initially though nitridation of the oxide layer and more recently the application of high-A: materials such as Hf based dielectrics. The work described in this thesis concerns the physical characterisation of thin high-A: multilayered samples using medium energy ion scattering (MEIS). A MEIS computer simulation model was applied and adapted to enable the interpretation of depth profiles from MEIS energy spectra. Forming part of an EU collaborative project, results obtained were compared to those of X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM), and X-ray fluoresence (XRF) to provide a better overall understanding of the characteristics of the layers. Nanometre thin SiC>2 layers nitrided using a novel plasma nitridation technique were investigated, demonstrated the nitridation of, and yielded the N distributions in the SiC>2 samples as well as demonstrating plasma damage. An improved k value was found, leading to an increased equivalent oxide (EOT) thickness. Studies of HfO2 and HfSiOx nanolayers, both with and without subjection to a decoupled plasma nitridation (DPN) process were carried out, characterising the layer structures with an accuracy of 0.1 nm in excellent agreement with the additional techniques. Crystallisation of the HfO2 layers, but not of the HfSiOx layers, after DPN was demonstrated. A high-A; metal gate Si/SiO2/HfO2/Al2O3/TiN stack was also investigated and Hf/Al interdiffusion demonstrated upon annealing. Finally Si/TiN/STO layers grown using different stoichiometric recipes, with and without a rapid thermal anneal at 650°C for 15s, were analysed. Layer structures were again determined with sub-nm resolution and diffusion between the Sr and Ti layers was observed after annealing. The high level of agreement between the depth profiles derived from the MEIS energy spectra, the growth parameters and the results from additional techniques has demonstrated the capability of MEIS in combination with spectrum simulation for the accurate analysis of these demanding ultra thin layer structures.
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Dalmia, Sidharth. "Design and implementation of high-Q passive devices for wireless applications using System-On-Package (SOP) based organic technologies". Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15689.
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Ma, Wei. "Low temperature metal-based micro fabrication and packaging technology /". View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?MECH%202005%20MA.
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Howard, Turner A. "Design of an advanced system for inspection of microelectronic devices and their solder connections using laser-induced virbration techniques". Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/16645.
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Othman, Maslina. "Spectroscopic ellipsometry analysis of nanoporous low dielectric constant films processed via supercritical carbon dioxide for next-generation microelectronic devices". Diss., Columbia, Mo. : University of Missouri-Columbia, 2007. http://hdl.handle.net/10355/4879.
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Thesis (Ph.D.)--University of Missouri-Columbia, 2007.The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on March 24, 2009) Vita. Includes bibliographical references.
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Wächtler, Thomas. "Thin Films of Copper Oxide and Copper Grown by Atomic Layer Deposition for Applications in Metallization Systems of Microelectronic Devices". Doctoral thesis, Universitätsbibliothek Chemnitz, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-201000725.
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Copper-based multi-level metallization systems in today’s ultralarge-scale integrated electronic circuits require the fabrication of diffusion barriers and conductive seed layers for the electrochemical metal deposition. Such films of only several nanometers in thickness have to be deposited void-free and conformal in patterned dielectrics. The envisaged further reduction of the geometric dimensions of the interconnect system calls for coating techniques that circumvent the drawbacks of the well-established physical vapor deposition. The atomic layer deposition method (ALD) allows depositing films on the nanometer scale conformally both on three-dimensional objects as well as on large-area substrates. The present work therefore is concerned with the development of an ALD process to grow copper oxide films based on the metal-organic precursor bis(tri-n-butylphosphane)copper(I)acetylacetonate [(nBu3P)2Cu(acac)]. This liquid, non-fluorinated β-diketonate is brought to react with a mixture of water vapor and oxygen at temperatures from 100 to 160°C. Typical ALD-like growth behavior arises between 100 and 130°C, depending on the respective substrate used. On tantalum nitride and silicon dioxide substrates, smooth films and self-saturating film growth, typical for ALD, are obtained. On ruthenium substrates, positive deposition results are obtained as well. However, a considerable intermixing of the ALD copper oxide with the underlying films takes place. Tantalum substrates lead to a fast self-decomposition of the copper precursor. As a consequence, isolated nuclei or larger particles are always obtained together with continuous films. The copper oxide films grown by ALD can be reduced to copper by vapor-phase processes. If formic acid is used as the reducing agent, these processes can already be carried out at similar temperatures as the ALD, so that agglomeration of the films is largely avoided. Also for an integration with subsequent electrochemical copper deposition, the combination of ALD copper and ruthenium proves advantageous, especially with respect to the quality of the electroplated films and their filling behavior in interconnect structures. Furthermore, the ALD process developed also bears potential for an integration with carbon nanotubesKupferbasierte Mehrlagenmetallisierungssysteme in heutigen hochintegrierten elektronischen Schaltkreisen erfordern die Herstellung von Diffusionsbarrieren und leitfähigen Keimschichten für die galvanische Metallabscheidung. Diese Schichten von nur wenigen Nanometern Dicke müssen konform und fehlerfrei in strukturierten Dielektrika abgeschieden werden. Die sich abzeichnende weitere Verkleinerung der geometrischen Dimensionen des Leitbahnsystems erfordert Beschichtungstechnologien, die vorhandene Nachteile der bisher etablierten Physikalischen Dampfphasenabscheidung beheben. Die Methode der Atomlagenabscheidung (ALD) ermöglicht es, Schichten im Nanometerbereich sowohl auf dreidimensional strukturierten Objekten als auch auf großflächigen Substraten gleichmäßig herzustellen. Die vorliegende Arbeit befasst sich daher mit der Entwicklung eines ALD-Prozesses zur Abscheidung von Kupferoxidschichten, ausgehend von der metallorganischen Vorstufe Bis(tri-n-butylphosphan)kupfer(I)acetylacetonat [(nBu3P)2Cu(acac)]. Dieses flüssige, nichtfluorierte β-Diketonat wird bei Temperaturen zwischen 100 und 160°C mit einer Mischung aus Wasserdampf und Sauerstoff zur Reaktion gebracht. ALD-typisches Schichtwachstum stellt sich in Abhängigkeit des gewählten Substrats zwischen 100 und 130°C ein. Auf Tantalnitrid- und Siliziumdioxidsubstraten werden dabei sehr glatte Schichten bei gesättigtem Wachstumsverhalten erhalten. Auch auf Rutheniumsubstraten werden gute Abscheideergebnisse erzielt, jedoch kommt es hier zu einer merklichen Durchmischung des ALD-Kupferoxids mit dem Untergrund. Tantalsubstrate führen zu einer schnellen Selbstzersetzung des Kupferprecursors, in dessen Folge neben geschlossenen Schichten während der ALD auch immer isolierte Keime oder größere Partikel erhalten werden. Die mittels ALD gewachsenen Kupferoxidschichten können in Gasphasenprozessen zu Kupfer reduziert werden. Wird Ameisensäure als Reduktionsmittel genutzt, können diese Prozesse bereits bei ähnlichen Temperaturen wie die ALD durchgeführt werden, so dass Agglomeration der Schichten weitgehend verhindert wird. Als besonders vorteilhaft für die Ameisensäure-Reduktion erweisen sich Rutheniumsubstrate. Auch für eine Integration mit nachfolgenden Galvanikprozessen zur Abscheidung von Kupfer zeigen sich Vorteile der Kombination ALD-Kupfer/Ruthenium, insbesondere hinsichtlich der Qualität der erhaltenen galvanischen Schichten und deren Füllverhalten in Leitbahnstrukturen. Der entwickelte ALD-Prozess besitzt darüber hinaus Potential zur Integration mit Kohlenstoffnanoröhren
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Wächtler, Thomas. "Thin Films of Copper Oxide and Copper Grown by Atomic Layer Deposition for Applications in Metallization Systems of Microelectronic Devices". Doctoral thesis, Universitätsverlag der Technischen Universität Chemnitz, 2009. https://monarch.qucosa.de/id/qucosa%3A19323.
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Copper-based multi-level metallization systems in today’s ultralarge-scale integrated electronic circuits require the fabrication of diffusion barriers and conductive seed layers for the electrochemical metal deposition. Such films of only several nanometers in thickness have to be deposited void-free and conformal in patterned dielectrics.
The envisaged further reduction of the geometric dimensions of the interconnect system calls for coating techniques that circumvent the drawbacks of the well-established physical vapor deposition.
The atomic layer deposition method (ALD) allows depositing films on the nanometer scale conformally both on three-dimensional objects as well as on large-area substrates. The present work therefore is concerned with the development of an ALD process to grow copper oxide films based on the metal-organic precursor bis(tri-n-butylphosphane)copper(I)acetylacetonate [(nBu3P)2Cu(acac)]. This liquid, non-fluorinated β-diketonate is brought to react with a mixture of water vapor and oxygen at temperatures from 100 to 160°C. Typical ALD-like growth behavior arises between 100 and 130°C, depending on the respective substrate used. On tantalum nitride and silicon dioxide substrates, smooth films and self-saturating film growth, typical for ALD, are obtained. On ruthenium substrates, positive deposition results are obtained as well. However, a considerable intermixing of the ALD copper oxide with the underlying films takes place. Tantalum substrates lead to a fast self-decomposition of the copper precursor. As a consequence, isolated nuclei or larger particles are always obtained together with continuous films. The copper oxide films grown by ALD can be reduced to copper by vapor-phase processes. If formic acid is used as the reducing agent, these processes can already be carried out at similar temperatures as the ALD, so that agglomeration of the films is largely avoided.
Also for an integration with subsequent electrochemical copper deposition, the combination of ALD copper and ruthenium proves advantageous, especially with respect to the quality of the electroplated films and their filling behavior in interconnect structures. Furthermore, the ALD process developed also bears potential for an integration with carbon nanotubes.Kupferbasierte Mehrlagenmetallisierungssysteme in heutigen hochintegrierten elektronischen Schaltkreisen erfordern die Herstellung von Diffusionsbarrieren und leitfähigen Keimschichten für die galvanische Metallabscheidung. Diese Schichten von nur wenigen Nanometern Dicke müssen konform und fehlerfrei in strukturierten Dielektrika abgeschieden werden. Die sich abzeichnende weitere Verkleinerung der geometrischen Dimensionen des Leitbahnsystems erfordert Beschichtungstechnologien, die vorhandene Nachteile der bisher etablierten Physikalischen Dampfphasenabscheidung beheben. Die Methode der Atomlagenabscheidung (ALD) ermöglicht es, Schichten im Nanometerbereich sowohl auf dreidimensional strukturierten Objekten als auch auf großflächigen Substraten gleichmäßig herzustellen. Die vorliegende Arbeit befasst sich daher mit der Entwicklung eines ALD-Prozesses zur Abscheidung von Kupferoxidschichten, ausgehend von der metallorganischen Vorstufe Bis(tri-n-butylphosphan)kupfer(I)acetylacetonat [(nBu3P)2Cu(acac)]. Dieses flüssige, nichtfluorierte β-Diketonat wird bei Temperaturen zwischen 100 und 160°C mit einer Mischung aus Wasserdampf und Sauerstoff zur Reaktion gebracht. ALD-typisches Schichtwachstum stellt sich in Abhängigkeit des gewählten Substrats zwischen 100 und 130°C ein. Auf Tantalnitrid- und Siliziumdioxidsubstraten werden dabei sehr glatte Schichten bei gesättigtem Wachstumsverhalten erhalten. Auch auf Rutheniumsubstraten werden gute Abscheideergebnisse erzielt, jedoch kommt es hier zu einer merklichen Durchmischung des ALD-Kupferoxids mit dem Untergrund. Tantalsubstrate führen zu einer schnellen Selbstzersetzung des Kupferprecursors, in dessen Folge neben geschlossenen Schichten während der ALD auch immer isolierte Keime oder größere Partikel erhalten werden. Die mittels ALD gewachsenen Kupferoxidschichten können in Gasphasenprozessen zu Kupfer reduziert werden. Wird Ameisensäure als Reduktionsmittel genutzt, können diese Prozesse bereits bei ähnlichen Temperaturen wie die ALD durchgeführt werden, so dass Agglomeration der Schichten weitgehend verhindert wird. Als besonders vorteilhaft für die Ameisensäure-Reduktion erweisen sich Rutheniumsubstrate. Auch für eine Integration mit nachfolgenden Galvanikprozessen zur Abscheidung von Kupfer zeigen sich Vorteile der Kombination ALD-Kupfer/Ruthenium, insbesondere hinsichtlich der Qualität der erhaltenen galvanischen Schichten und deren Füllverhalten in Leitbahnstrukturen. Der entwickelte ALD-Prozess besitzt darüber hinaus Potential zur Integration mit Kohlenstoffnanoröhren.
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Alsaleem, Fadi M. "An investigation into the effect of the PCB motion on the dynamic response of MEMS devices under mechanical shock loads". Diss., Online access via UMI:, 2007.
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Ohta, Ricardo Luís. "Construção e caracterização de fotodetetores metal-semicondutor-metal (MSM)". Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-22072007-172649/.
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Este trabalho teve como objetivo principal a fabricação de fotodetetores do tipo Metal-Semicondutor-Metal (MSM) com corrente de escuro da ordem de 1 nA, responsividade da ordem de 0,1 A/W e razão fotocorrente/corrente de escuro de pelo menos 10. Estes valores asseguram que os fotodetetores obtidos tenham sensibilidade suficiente para serem utilizados em sensores ópticos integrados. Todos os materiais utilizados na construção dos fotodetetores MSM são compatíveis com processos convencionais de fabricação em microeletrônica, facilitando a integração com outros dispositivos em estado sólido. O semicondutor utilizado nos fotodetetores foi o silício, na forma monocristalina ou policristalina. Como material de eletrodo, foi utilizado o alumínio, o titânio ou o níquel. No processo de fabricação básico, foram utilizados apenas três etapas: deposição do filme metálico, fotolitografia e corrosão, confirmando a simplicidade de fabricação desse fotodetetor. Através da construção de dispositivos com diferentes geometrias e diferentes combinações dos materiais citados acima, foi possível verificar a influência que a estrutura cristalina do semicondutor, tipo de dopagem do semicondutor, geometria e material de eletrodo tem sobre o desempenho e o comportamento dos MSMs. O comprimento de onda de 632,8 nm foi utilizado na caracterização dos dispositivos, devido a sua disponibilidade e o desenvolvimento de guias ópticos utilizando esse comprimento de onda em trabalhos anteriores do nosso grupo de pesquisa. Os melhores resultados obtidos foram com as amostras de Si monocristalino tipo-p com eletrodos de titânio. Na amostra sinterizada à 250°C foi obtido um valor da corrente de escuro de 4,8 nA e, na amostra de referência, foi obtido um valor de responsividade de 0,28 A/W.The goal of this work was the fabrication of Metal-Semiconductor-Metal (MSM) photodetectors with the following characteristics: dark current of about 1 nA, responsivity of about 0.1 A/W and dark/photocurrent ratio of at least 10. These values ensure that the photodetectors have enough sensitivity to be used in integrated optic sensors. All materials used in the fabrication of the MSM are compatible with conventional microelectronic manufacture process, so that the photodetectors can be more easily integrated with other solid-state devices. The semiconductor used in the photodetectors was silicon, in single crystal and polycrystalline form. As material of electrodes, aluminum, titanium or nickel had been used. The basic fabrication process consists of only three steps: metal film deposition, photolithography and etching, which confirm the simplicity of the fabrication of this device. Building MSMs with different geometries and making combinations with the materials cited above, gave the possibility to verify the influence that crystalline structure of the semiconductor, doping type of the semiconductor, geometry and electrode material have on the behavior of the photodetectors. The wavelength of 632.8 nm was used in the characterization of the devices, due to its availability and the development of optic waveguides using this wavelength in previous works of our research group. The best results were obtained with the samples fabricated using single crystal Si p-type with titanium electrodes. The sample annealed at 250°C had dark current value of 4.8 nA and, the reference sample had responsivity of 0.28 A/W.
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Terranova, Brandon. "Design and optimization of VCSEL-based optical interconnects on package". Diss., Online access via UMI:, 2009.
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Yang, Jin. "Quality inspection and reliability study of solder bumps in packaged electronic devices [electronic resource] : using laser ultrasound and finite element methods". Diss., Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26593.
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Consumer demands are driving the current trend in the microelectronics industry to make electronic products that are miniature, fast, compact, high-density, reliable and low-cost. The use of surface mount devices (SMDs) has helped to decrease the size of electronic packages through the use of solder bump interconnections between the devices and the substrates/printed wiring boards (PWBs). Solder bumps act as not only mechanical, but also electrical interconnections between the device and the substrate/PWB. Common manufacturing defects ¨C such as open, cracked, missing, and misaligned solder bumps ¨C are difficult to detect because solder bumps are hidden between the device and the substrate/PWB after assembly. The reliability of packaged electronic devices in storage and usage is a major concern in the microelectronics industry. Therefore, quality inspection of solder bumps has become a critical process in the microelectronics industry to help ensure product quality and reliability.
In this thesis, a methodology for quality evaluation and reliability study of solder bumps in electronic packages has been developed using the non-destructive and non-contact laser ultrasound-interferometric technique, finite element and statistical methods in this research work. This methodology includes the following aspects: 1) inspection pattern ¨C specific inspection patterns are created according to inspection purpose and package formats, 2) laser pulse energy density calibration ¨C specific laser pulse power and excitation laser spot size are selected in terms of package formats, 3) processing and analysis methods, including integrated analytical, finite element and experimental modal analyses approach, advanced signal processing methods and statistical analysis method, 4) approach combining modal analysis and advanced signal processing to improve measurement sensitivity of laser ultrasound-interferometric inspection technique, and 5) calibration curve using energy based simulation method and laser ultrasound inspection technique to predict thermomechanical reliability of solder bumps in electronic packages.
Because of the successful completion of the research objectives, the system has been used to evaluate a broad range of solder bump defects in a variety of packaged electronic devices. The development of this system will help tremendously to improve the quality and reliability of electronic packages.
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Osborn, Tyler Nathaniel. "All-copper chip-to-substrate interconnects for high performance integrated circuit devices". Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28211.
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Thesis (M. S.)--Chemical Engineering, Georgia Institute of Technology, 2009.Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, James.
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Ткач, Олена Петрівна, Елена Петровна Ткач, Olena Petrivna Tkach, Є. І. Сухін, Катерина Сергіївна Однодворець, Екатерина Сергеевна Однодворец i Kateryna Serhiivna Odnodvorets. "Акустоелектронний сенсор фізичних величин на поверхневих акустичних хвилях". Thesis, Сумський державний університет, 2018. http://essuir.sumdu.edu.ua/handle/123456789/67906.
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Розроблення сенсорних пристроїв на вітчизняному та світовому ринках є прогресивним напрямом в подальшому розвитку наноелектроніки. На основі поверхневих хвиль розроблена велика кількість сенсорів з високими показниками точності, що дозволяють вимірювати вагу, тиск, прискорення та ін. До переваг даних пристроїв можна віднести те, що вони створюються на основі елементів інтегральної електроніки, оптики та різноманітних мікроелектронних технологій і при цьому забезпечують контроль декількох фізичних величин. Проте актуальними залишаються питання пошуку нових матеріалів для підкладки та топології її виготовлення.
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Thomas, Stuart R. "Solution processed metal oxide microelectronics : from materials to devices". Thesis, Imperial College London, 2013. http://hdl.handle.net/10044/1/22162.
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Owing to their many interesting characteristics, the application of metal oxide based electronics has been growing at a considerable rate for the past ten years. High performance, optical transparency, chemical stability and suitability toward low cost deposition methods make them well suited to a number of new and interesting application areas which conventional materials such as silicon, or more recently organic materials, are unable to satisfy. The work presented in this thesis is focussed on the optimisation of high performance metal oxide based electronics combined with use of spray pyrolysis, as a low cost deposition method. The findings presented here are split into three main areas, starting with an initial discussion on the physical and electronic properties of films deposited by spray pyrolysis. The results demonstrate a number of deposition criteria that aid in the optimisation and fabrication of high performance zinc oxide (ZnO) based thin-film transistors (TFTs) with charge carrier mobilities as high a 20 cm2/Vs. Solution processed gallium oxide TFTs with charge carrier mobilities of ~0.5 cm2/Vs are also demonstrated, highlighting the flexibility of the deposition method. The second part of the work explores the use of facile chemical doping methods suitable for spray pyrolysed ZnO based TFTs. By blending different precursor materials in solution prior to deposition, it has been possible to adjust certain material characteristics, and in turn device performance. Through the addition of lithium it has been possible alter the films grain structure, leading to significantly improved charge carrier mobilities as high as ~54 cm2/Vs. Additionally the inclusion of beryllium during film deposition has been demonstrated to control TFT threshold voltages, leading to improved integrated circuit performance. The final segment of work demonstrates the flexibility of spray pyrolysis through the deposition of a number of high-k dielectric materials. These high performance dielectrics are integrated into the fabrication of TFTs already benefiting from the findings of the previously discussed work, leading to highly optimised low-voltage TFTs. The performance of these devices represent some of best currently available from solution processed ZnO TFTs with charge carrier mobilities as high as 85 cm2/Vs operating at 3.5 V.
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Hou, Chih-Sheng Johnson. "An integrated microelectronic device for biomolecular amplification and detection". Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/38676.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 133-154).
The extraordinarily high sensitivity, large dynamic range and reproducibility of polymerase chain reaction (PCR) have made it one of the most widely used techniques for analyzing nucleic acids. As a result, considerable effort has been directed towards developing miniaturized systems for PCR, but most rely on off-chip optical detection modules that are difficult to miniaturize into a compact analytical system and fluorescent product markers that can require extensive effort to optimize. This thesis presents a robust and simple method for direct label-free PCR product quantification using a microelectronic sensor. The thesis covers the design, fabrication, and characterization of the sensing technique and its integration with PCR microfluidics into a monolithic detection platform. The sensor used in this thesis study is an electrolyte-insulator-silicon (EIS) device fabricated on planar silicon substrates. Based on electronic detection of layer-by-layer assembly of polyelectrolytes, the sensing technique can specifically quantify double-stranded DNA product in unprocessed samples and monitor the product concentration at various stages of PCR to generate readout analogous to that of a real-time fluorescent measurement.
(cont.) Amplification is achieved with integrated metal resistive heaters, temperature sensors, and microfluidic valves. Direct electronic quantification of the product on-chip yields analog surface potential signals that can be converted to a digital true/false readout. A silicon field-effect sensor for direct detection of heparin by its intrinsic negative charge has also been developed. Detection of heparin and heparin-based drugs in buffer and serum has been studied, and a study demonstrating strong correlation between electronic heparin sensing measurements and those from a colorimetric assay for heparin-mediated anti-Xa activity has been performed.
by Chih-Sheng Johnson Hou.
Ph.D.
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Cukalovic, Boris. "MIT integrated microelectronics device experimentation and simulation iLab". Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/36776.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 57-58).
We developed the MIT Integrated Microelectronics Device Experimentation and Simulation iLab, a new online laboratory that combines and significantly upgrades the capabilities of two existing online microelectronics labs: WebLab, a device characterization lab, and WebLabSim, a device simulation lab. The new integrated tool allows users to simultaneously run experiments on actual devices and simulations on the virtual ones, as well as to compare the results of the two. In order to achieve this, we considerably extended the capabilities of the original clients. We added the ability to graph the results of multiple experiments and simulations simultaneously, on top of each other, which allows for much easier comparison. We also added the ability to load, view and graph the results of experiments and simulations that were ran at any point in the past, even when the corresponding lab configurations are no longer available. Our hope is that this new integrated iLab will enrich microelectronics teaching and learning by allowing students to compare real life device behavior with theoretical expectations.
by Boris Cukalovic.
M.Eng.
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Wei, Xiaojin. "Stacked Microchannel Heat Sinks for Liquid Cooling of Microelectronics Devices". Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4873.
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A stacked microchannel heat sink was developed to provide efficient cooling for microelectronics devices at a relatively low pressure drop while maintaining chip temperature uniformity. Microfabrication techniques were employed to fabricate the stacked microchannel structure, and experiments were conducted to study its thermal performance. A total thermal resistance of less than 0.1 K/W was demonstrated for both counter flow and parallel flow configurations. The effects of flow direction and interlayer flow rate ratio were investigated. It was found that for the low flow rate range the parallel flow arrangement results in a better overall thermal performance than the counter flow arrangement; whereas, for the large flow rate range, the total thermal resistances for both the counter flow and parallel flow configurations are indistinguishable. On the other hand, the counter flow arrangement provides better temperature uniformity for the entire flow rate range tested. The effects of localized heating on the overall thermal performance were examined by selectively applying electrical power to the heaters. Numerical simulations were conducted to study the conjugate heat transfer inside the stacked microchannels. Negative heat flux conditions were found near the outlets of the microchannels for the counter flow arrangement. This is particularly evident for small flow rates. The numerical results clearly explain why the total thermal resistance for counter flow arrangement is larger than that for the parallel flow at low flow rates.
In addition, laminar flow inside the microchannels were characterized using Micro-PIV techniques. Microchannels of different width were fabricated in silicon, the smallest channel measuring 34 mm in width. Measurements were conducted at various channel depths. Measured velocity profiles at these depths were found to be in reasonable agreement with laminar flow theory. Micro-PIV measurement found that the maximum velocity is shifted significantly towards the top of the microchannels due to the sidewall slope, a common issue faced with DRIE etching. Numerical simulations were conducted to investigate the effects of the sidewall slope on the flow and heat transfer. The results show that the effects of large sidewall slope on heat transfer are significant; whereas, the effects on pressure drop are not as pronounced.
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Foong, Andrew Jun Li. "Heat transfer and fluid flow characteristics of microchannels with internal longitudinal fins". Thesis, Curtin University, 2009. http://hdl.handle.net/20.500.11937/360.
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Electronic components generate large amount of heat during their operation, which requires to be dissipated. Over the past decade, internal heat generation levels have exponentially increased due to the compact packaging of high-powered microelectronic circuitry in modern devices. The efficient removal of this internally generated heat from microelectronic components is a critical design consideration for enabling optimum performance, and improving the operational reliability of modern high-performance electronic devices. Traditional cooling techniques such as fan-cooled heat sinks are grossly inadequate, and impose severe limits on product design, and hence cannot be used for cooling modern electronic components. Microchannel based cooling systems are highly popular due to its high surface area to volume ratio, and are identified as a highly viable practical alternative for meeting the current and future cooling needs of advanced electronic components. There are several methods to enhance the heat transfer performance of a microchannel. One of the single-phase heat transfer enhancement methods is to provide internal fins in a microchannel. The internal fins provide an increase in the surface area for heat transfer, and under certain conditions, alter the internal flow to provide an enhancement in heat transfer as compared to a microchannel without internal fins.In this thesis, a numerical study is performed to investigate the heat transfer and fluid flow characteristics of microchannels with four longitudinal internal fins. The simulations are carried out in the presence of a hydrodynamically fully developed, thermally developing laminar flow. Constant heat flux boundary conditions are assumed on the external walls of the microchannel. A range of channel aspect ratios covering square and rectangular cross-sectioned microchannels, with four internal longitudinal fins of various heights and thicknesses are considered in the modeling. Results of the velocity and temperature distribution are analysed in detail, to examine the effects of fin height and thickness on the heat transfer and fluid flow characteristics of the microchannels. Based on the range of parameters analysed, an optimum fin geometry that provides the maximum heat transfer rate is obtained from the analysis. The result of the optimum fin geometry is also obtained using the thermal resistance method of analysis. A thermodynamic analysis based on the entropy generation minimization method is carried out by estimating the irreversibility due to both heat transfer and fluid friction, in order to obtain the an optimum fin geometry. The optimum fin geometry obtained from the above methods are further compared, and is found to be similar. The comprehensive study carried out in this thesis provide more physical insight, and useful results on the heat and fluid flow characteristics of this potential single-phase passive heat transfer enhancement technique.
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Wan, Kris Pui Yu. "Fabrication of protein and DNA-mediated devices : a potential application in microelectronics /". View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?CENG%202003%20WAN.
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Garst, Sebastian. "Design and production of polymer based miniaturised bio-analytical devices". Australasian Digital Thesis Program, 2007. http://adt.lib.swin.edu.au/public/adt-VSWT20071003.082618/index.html.
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Thesis (MEng) - Swinburne University of Technology, Industrial Research Institute Swinburne - 2007.A thesis submitted for fulfillment of the requirement for the degree of Master of Engineering, Industrial Research Institute, Swinburne University of Technology - 2007. Typescript. Includes bibliographical references (p. 148-155).
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Sidek, Roslina. "Applications of Si/SiGe heterostructures to CMOS devices". Thesis, University of Southampton, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.286957.
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Madathil, Sankara Narayanan Ekkanath. "CMOS compatible lateral MOS controlled power devices for High Voltage Integrated Circuits". Thesis, University of Cambridge, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.240223.
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Wong, Terence Kin Shun. "Fabrication and characterization of ultrasmall tunnelling devices". Thesis, University of Cambridge, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.241122.
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Hoole, Andrew Charles Frederick. "Nanolithography and its application to the fabrication of electron devices". Thesis, University of Cambridge, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.308358.
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Qin, Zuxin. "Novel lateral MOS controlled power devices and technologies for power integrated circuits". Thesis, De Montfort University, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.391477.
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Chang, Won Jae. "Design and fabrication of a novel electrostatic micromirror with high speed and large rotation angle". [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0009060.
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