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Wang, Xin. "Power Efficient Embedded Memory Design for Mobile Video Applications". Thesis, North Dakota State University, 2015. https://hdl.handle.net/10365/27621.
Pełny tekst źródłaSELMO, SIMONE. "Functional analysis of In-based nanowires for low power phase change memory applications". Doctoral thesis, Università degli Studi di Milano-Bicocca, 2017. http://hdl.handle.net/10281/153247.
Pełny tekst źródłaPhase change memories (PCMs), based on chalcogenide alloys (mainly Ge2Sb2Te5), are the most promising candidate for the realization of “Storage Class Memories”, which would fill the gap between ‘‘operation’’ and ‘‘storage’’ memories. PCMs are also one of the few currently available technologies for the implementation of nanoeletronic synapses in high density neuromorphic systems. The main improvements needed in order to exploit the full potential of PCMs in these innovative applications are the reduction of the programming currents and power consumption, and further cell downscaling. Thanks to their nano-sized active volume to be programmed and self-heating behavior, phase change nanowires (NWs) are expected to exhibit improved memory performances with respected to commonly used thin-film/heater-based structures. The Ph. D. Thesis of the candidate reports the study of the phase change properties of ultra-thin In-based NWs for low power consuming PCMs, exploring the more promising features of this class of materials with respect to the commonly considered Ge-Sb-Te alloys. In particular, the self-assembly of In-Sb-Te, In-doped Sb and In-Ge-Te NWs was successfully achieved by Metal Organic Chemical Vapour Deposition (MOCVD), coupled to vapour-liquid-solid mechanism, catalysed by catalyst nanoparticles. The parameters influencing the NW self-assembly were studied and the compositional, morphological and structural analysis of the grown structures was performed. In all cases, NWs of several μm in length and with diameters as small as 15 nm were obtained. The experimental contribution of the Ph. D. candidate to the NWs growth study was mainly related to the substrates preparation, catalyst deposition and, morphological and elemental analysis of the grown samples. Moreover, the Ph. D. candidate has performed the functional analysis of In3Sb1Te2 and In-doped Sb NW-based PCM devices. To conduct that analysis, a suitable fabrication procedure of the devices and an appropriate electrical measuring set-up have been identified. Reversible and well reproducible phase change memory switching was demonstrated for In3Sb1Te2 and In-doped Sb NW devices, showing low working parameters, such as “RESET” voltage, current and power. The obtained results support the conclusion that In-based ultra-thin NWs are potential building blocks for the realization of ultra-scaled, high performance PCM devices.
Morrison, Matthew Arthur. "Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits For Security Applications". Scholar Commons, 2013. https://scholarcommons.usf.edu/etd/5082.
Pełny tekst źródłaRamclam, Kenneth M. "Low-Power and Robust Level-Shifter with Contention Mitigation for Memory and Standalone Applications". Scholar Commons, 2015. https://scholarcommons.usf.edu/etd/5555.
Pełny tekst źródłaLai, Farley. "Stream processing optimizations for mobile sensing applications". Diss., University of Iowa, 2017. https://ir.uiowa.edu/etd/5797.
Pełny tekst źródłaMandlekar, Anup Shrikant. "An Application Framework for a Power-Aware Processor Architecture". Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/34484.
Pełny tekst źródłaMaster of Science
Cortes, Christoffer, i Adam Krauser. "Android : Resource Consumption in Native and Web Applications". Thesis, Blekinge Tekniska Högskola, Sektionen för datavetenskap och kommunikation, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-4681.
Pełny tekst źródłaMugisha, Dieudonne Manzi. "Exploiting Application Behaviors for Resilient Static Random Access Memory Arrays in the Near-Threshold Computing Regime". DigitalCommons@USU, 2015. https://digitalcommons.usu.edu/etd/4550.
Pełny tekst źródłaMahato, Prabir. "Study and development of resistive memories for flexible electronic applications". Thesis, Lyon, 2020. http://www.theses.fr/2020LYSEI134.
Pełny tekst źródłaThe advent of flexible electronics has brought about rapid research towards sensors, bio implantable and wearable devices for assessment of diseases such as epilepsy, Parkinson’s and heart attacks. Memory devices are major component in any electronic circuits, only secondary to transistors, therefore many research efforts are devoted to the development of flexible memory devices. Conductive Bridge Random Access Memories (CBRAMs) based on creation/dissolution of a metallic filament within a solid electrolyte are of great research interest because of their simple Metal Insulator Metal architecture, low-voltage capabilities, and compatibility with flexible substrates. In this work, instead of a conventional metallic oxide or a chalcogenide layer, a biocompatible polymer - Polyethylene Oxide (PEO) – is employed as the solid electrolyte layer using water as solvent. Memory devices, consisting in Ag/PEO/Pt tri-layer stacks, were fabricated on both silicon and flexible substrates using a heterogeneous process combining physical vapour deposition and spin coating. To aim this, a systematic study on the effect of solution concentration and deposition speed on the PEO thickness is presented. SEM/EDX and AFM measurements were then conducted on devoted “nano-gap” planar structures and have revealed the formation of metallic Ag precipitates together with morphological changes of the polymer layer after resistance switching. The performance of the resistive memory devices is then assessed on silicon and flexible substrates. In particular programming voltage statistics, OFF/ON resistance ratio, endurance cycles and retention tests are performed and the effect of current compliance is analysed. The conduction mechanism in the HRS/LRS is studied on the Ag/PEO/Pt and Pt/PEO/Pt reference devices. Finally, the electrical characterization of devices on flexible substrate is performed under mechanical stress, showing promising results. Polymer-based CBRAM devices are therefore suggested as potential candidates for sustainable development of flexible memory devices
Ly, Aliou. "Développement d’un oscillateur paramétrique optique continu intense et à faible bruit pour des applications aux communications quantiques". Thesis, Université Paris-Saclay (ComUE), 2017. http://www.theses.fr/2017SACLS528/document.
Pełny tekst źródłaLong distance quantum communications are limited to few tens of km due to the attenuation of light in telecom fibres. Quantum repeaters (quantum relays synchronized by photonic quantum memories) were introduced in order to increase distances. Or, currently, the most efficient memories do not operate at wavelengths in the telecom C band. In order to take advantage of these memories, the use of quantum interfaces (second order nonlinear medium) was proposed as an alternative. Thus, by adding by sum frequency generation a pump photon at an appropriate wavelength to the telecom photon carrying the information, one transfers the information to a wavelength compatible with these memories, and this with a preservation of the information initially carried by the telecom photon. Our aim is thus to build a continuous-wave singly resonant optical parametric oscillator (cw SRO) which will provide a wave at 1648 nm that will be frequency summed to telecom photons at 1536 nm to transfer the information to a photon storable into alkali atoms based memory. To efficiently transfer the information, the cw SRO has to fulfill some requirements: a high spectral purity (linewidth ~kHz), a high output power (~1 W) and a wavelength longer than that of the telecom photon to be converted. To this aim, we use the non-resonant wave of a cw SRO. The first work done during this thesis was to experimentally prove the possibility to have both high output power and high spectral purity from a cw SRO. By reusing a cw SRO already built during our previous works, we were able to stabilize at the kHz level the frequency of the non-resonant wave at 947 nm (signal wave) of this SRO, with an output power of more than one watt. Then, we built the cw SRO of which non-resonant wave at 1648 nm (idler wave) has been frequency stabilized below the kHz level along with an output power of the order of one watt. We next studied the long term stability of the idler wavelength at 1648 nm. We have measured frequency drifts of the order of 10 MHz/mn. These drifts originating mainly from the reference cavity to which the SRO is locked, can be reduced by, firstly, an active control of the cavity and by, secondly, the use of robust frequency stabilization techniques
Mbaye, Amadou. "Linéarisation des amplificateurs de puissance large-bande pour des applications de communications tactiques et de diffusion audio ou vidéo numérique". Thesis, Paris Est, 2015. http://www.theses.fr/2015PEST1021/document.
Pełny tekst źródłaPower amplifier is one of the most critical element within radiocommunications systems. The PA is their main source of nonlinearities and it has a great contribution on the emitter's power consumption. Running the PA with highest power efficiency is thus as crucial as having it linear for a good communication quality. However these two specifications of the PA are antagonistic and PA manifacturers need to find a compromise between linearity and power efficiency. Digital Predistortion (DPD) and Crest factor Reduction techniques are intended to improve power efficiency while preserving linearity or inversely. Linearization of wideband RF power amplifiers using Digital Predistortion is the focus of this thesis. Three DPD issues are investigated in these works. The first issue deals with multiband linearization where signals with various waveforms located at different frequency bands are amplified. The second objective of this thesis is to study a concurrent DPD/CFR systems based on an automatic estimation of the necessary CFR gain. The last part of this dissertation deals with PA linearization under antenna load variations. Indeed, the impedance of antenna may vary because of electromagnetic objects that are present in its vicinity. Those impedance variations may instigate signal reflections toward the PA, that modify some of its main specifications (linearity, delivered power and efficiency). Our goal in this field is to preserve DPD linearization performances under antenna load mismatch
Du, Nan. "Beyond "More than Moore": Novel applications of BiFeO3 (BFO)-based nonvolatile resistive switches". Doctoral thesis, Universitätsbibliothek Chemnitz, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-202508.
Pełny tekst źródłaIn den letzten Jahrzehnten war die Größenreduktion von Transistoren einer der Hauptgründe für die Leistungssteigerung von integrierten Halbleiterschaltungen. Aufgrund des physikalisch beschränkten Skalierungspotentials, werden alternative Technologien für Halbleiterschaltungen entwickelt. Dazu zählen neuartige Widerstandsschalter, sogenannte Memristoren, welche wegen ihrer schnellen Schaltgeschwindigkeit, langen Speicherzeit und stabilen Haltbarkeit in den Fokus der Forschung gerückt sind. Das nichtflüchtige analoge bipolare Schalten des Widerstandwertes mit einem On/Off Verhältnis größer als 100 wurde in BiFeO 3 (BFO)-basierten Widerstands-schaltern beobachtet. Bisher wurden Widerstandsschalter hauptsächlich als Speicher oder in rekonfigurierbaren Logikschaltungen verwendet. Aufgrund der ausgezeichneten Eigenschaften von BFO-basierten Memristoren, ist die Untersuchung weiterer neuer Funktionalitäten vielversprechend. Als neuer Ansatz für ein Hardware-basiertes Kryptosystem wird in der vorliegenden Arbeit die Ausnutzung des Leistungsübertragungskoeffizienten in BFO Memristoren vorgeschlagen. Mit Hilfe der unterschiedlichen Oberschwingungen, welche von einem BFO Memristor im ON und OFF Zustand generiert werden, wurde ein Kryptosystem zum Kodieren binärer Daten entwickelt. Ein Test des Hardware-basierten Kryptosystems an Biodaten ergab, dass die kodierten Biodaten keine vorhersagbare Korrelation mehr enthielten. In der vorliegenden Arbeit wurden darüberhinaus BFO-basierte künstliche Synapsen mit einer Aktionspotentials-Intervall abhängigen Plastizität (STDP) für Einzelpulse entwickelt. Diese Einzelpuls-STDP legt den Grundstein für energieffiziente und schnelle neuromorphe Netzwerke mit künstlichen Synapsen. Im Vergleich zu biologischen Synapsen mit einer 60-80-Puls-STDP und einem Lernfenster auf der ms-Zeitskale, konnte das Lernfenster von BFO-basierten künstlichen Synapsen von 25 ms auf 125 μs reduziert werden. Solch ein schnelles Lernen ermöglicht auch die extreme Reduzierung des Leistungsverbrauchs in neuromorphen Netzwerken
Hitchcock, Yvonne Roslyn. "Elliptic curve cryptography for lightweight applications". Thesis, Queensland University of Technology, 2003. https://eprints.qut.edu.au/15838/1/Yvonne_Hitchcock_Thesis.pdf.
Pełny tekst źródłaHitchcock, Yvonne Roslyn. "Elliptic Curve Cryptography for Lightweight Applications". Queensland University of Technology, 2003. http://eprints.qut.edu.au/15838/.
Pełny tekst źródłaKatrue, Srikanth. "Power reduction techniques for memory elements /". Online version of thesis, 2007. http://hdl.handle.net/1850/5720.
Pełny tekst źródłaFeki, Anis. "Conception d’une mémoire SRAM en tension sous le seuil pour des applications biomédicales et les nœuds de capteurs sans fils en technologies CMOS avancées". Thesis, Lyon, INSA, 2015. http://www.theses.fr/2015ISAL0018/document.
Pełny tekst źródłaEmergence of large Systems-On-Chip introduces the challenge of power management. Of the various embedded blocks, static random access memories (SRAM) constitute the angrier contributors to power consumption. Scaling down the power supply is one way to act positively on power consumption. One aggressive target is to enable the operation of SRAMs at Ultra-Low-Voltage, i.e. as low as 300 mV (lower than the threshold voltage of standard CMOS transistors). The present work concerned the proposal of SRAM bitcells able to operate at ULV and for advanced technology nodes (either CMOS bulk 28 nm or FDSOI 28 nm). The benchmarking of published architectures as state-of-the-art has led to propose two flavors of 10-transitor bitcells, solving the limitations due to leakage current and parasitic power consumption. Segmented read-ports have been used along with the required synchronous peripheral circuitry including original replica assistance, a dedicated unbalanced sense amplifier for ULV operation and dynamic forward back-biasing of SOI boxes. Experimental test chips are provided in previously mentioned technologies. A complete memory cut of 32 kbits (1024x32) has been designed with an embedded BIST block, able to operate at ULV. After a general introduction, the manuscript proposes the state-of-the-art in chapter two. The new 10T bitcells are presented in chapter 3. The sense amplifier along with the replica assistance is the core of chapter 4. The memory cut in FDSOI 28 nm is detailed in chapter 5. Results of the PhD have been disseminated with 4 patent proposals, 2 papers in international conferences, a first paper accepted in an international journal and a second but only submitted paper in an international journal
Dancy, Abram P. (Abram Paul). "Power supplies for ultra low power applications". Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/10069.
Pełny tekst źródłaIncludes bibliographical references (p. 101-103).
by Abram P. Dancy.
M.Eng.
Nizamuddin, Muhammad Ali. "Predistortion for Nonlinear Power Amplifiers with Memory". Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/36184.
Pełny tekst źródłaThe fusion of voice and data applications, along with the demand for high data-rate applications such as video-on-demand, is making radio frequency (RF) spectrum an increasingly expensive commodity for current and future communications. Although bandwidth-efficient digital modulation alleviates part of the problem by requiring a minimal use of spectral resources, they put an extra design burden on RF engineers. RF transmitters and power amplifiers account for more than half the total maintenance cost of a base-station, while occupying nearly the same portion of space. Therefore, power amplifiers become a bottleneck for digital systems in terms of space and power consumption. However, power-efficient use of the amplifiers, although desirable, is extremely detrimental to end-to-end performance due to the very high peak-to-average power ratios of modulations that are used today. In order to reduce distortion while maintaining high power conversion efficiency in a power amplifier, linearization schemes are needed. In addition, significant frequency-dependent Memory Effects result in high power amplifiers operating on wideband signals. Therefore, these effects need to be considered during any attempt to minimize amplifier distortion.
In this thesis, we present two schemes to cancel nonlinear distortion of a power amplifier, along with its memory effects and results for one of the schemes. The results highlight the fact that in the presence of significant memory effects, cancellation of these effects is necessary to achieve reasonable improvement in performance through linearization. We focus on predistortive schemes due to their digital- friendly structure and simple implementation. The operating environment consists of a multi-carrier W-CDMA signal. All of the studies are performed using numerical simulation on MATLAB and Agilent's Advanced Design System (ADS).
Master of Science
Zhu, Zhichun. "Power considerations for memory-related microarchitecture designs". W&M ScholarWorks, 2003. https://scholarworks.wm.edu/etd/1539623427.
Pełny tekst źródłaHanai, Ryo. "Memory management for real-time applications". 京都大学 (Kyoto University), 2007. http://hdl.handle.net/2433/135980.
Pełny tekst źródłaDulloor, Subramanya R. "Systems and applications for persistent memory". Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/54396.
Pełny tekst źródłaChoi, David Suho. "Integration of non-volatile memory with volatile memory for embedded memory architectures and signal processing applications". Diss., Restricted to subscribing institutions, 2008. http://proquest.umi.com/pqdweb?did=1692120591&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.
Pełny tekst źródłaNeagu, Mădălin. "Self-healing and secure low-power memory systems". Doctoral thesis, Universitat Politècnica de Catalunya, 2017. http://hdl.handle.net/10803/460893.
Pełny tekst źródłaRuppert, Eric. "The consensus power of shared-memory distributed systems". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape3/PQDD_0028/NQ49848.pdf.
Pełny tekst źródłaHettiaratchi, Sambuddhi Sinha Bandara. "Power optimized memory access in high-level synthesis". Thesis, Imperial College London, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.407906.
Pełny tekst źródłaTolentino, Matthew Edward. "Managing Memory for Power, Performance, and Thermal Efficiency". Diss., Virginia Tech, 2009. http://hdl.handle.net/10919/26301.
Pełny tekst źródłaPh. D.
Harel, Nissim. "Memory Optimizations for Distributed Stream-based Applications". Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/13988.
Pełny tekst źródłaHernandez, Allison 1979. "Analysis of magnetic random access memory applications". Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/8461.
Pełny tekst źródłaIncludes bibliographical references (p. 45-47).
Magnetic Random Access Memory (MRAM) is considered to be the most viable option for nonvolatile memory in the computer industry. This need for nonvolatile computer memory has resulted in the dramatic evolution of MRAM technology in the past ten years. Currently in the latter stages of development, emphasis is being put on experiments concerning optimization of density and reduction of the switching fields of the magnetic elements. Applications of MRAM technology are currently being explored by companies who seek to obtain relevant intellectual property in those areas. Once research is completed, companies must create a business plan that recognizes the initial, breakthrough markets and implement technology integration accordingly.
by Allison Hernandez.
M.Eng.
Guo, Weimin M. Eng Massachusetts Institute of Technology. "Orthopaedic applications of ferromagnetic shape memory alloys". Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/45957.
Pełny tekst źródłaIncludes bibliographical references (leaves 36-40).
Ferromagnetic shape memory alloys (FSMAs) are a new class of magnetic field-actuated active materials with no current commercial applications. By applying a magnetic field of around 0.4 T, they can exert a stress of approximately 1.5 MPa, exhibiting a strain of up to 6%. This thesis evaluates their technical and commercial feasibility in orthopaedic applications. Remote actuation is a key advantage FSMAs have over current implant materials. Also, the human body temperature is constant, providing a stable environment for FSMAs to operate. A number of potential orthopaedic applications are proposed and evaluated. Out of these, the most prominent application is the spinal traction device. It is a temporary implantable device, intended to perform internal spinal traction. A design has been proposed, with suggestions of suitable materials for its various components and appropriate device dimensions. Preliminary market and cost analyses have been conducted. This orthopaedic technology is currently in its infant stage. To commercialize this device, more trials are needed.
by Weimin Guo.
M.Eng.
Chou, Wu-chun. "Coding applications in volume holographic memory systems". Diss., The University of Arizona, 1999. http://hdl.handle.net/10150/283998.
Pełny tekst źródłaChitty, R., L. Capote, J. Kaschmitter i D. Tuckerman. "Compact Memory Module for High Performance Applications". International Foundation for Telemetering, 1989. http://hdl.handle.net/10150/614702.
Pełny tekst źródłaA common problem in many space applications is the need for a reliable large memory capacity in a light weight, low volume package. The Fairchild Space Company (FSC) is developing a high density static RAM based on VHSIC Hybrid Wafer Scale Integration (HWSI) technology for use in high reliability applications. Advances in interconnect technology and electronic packaging result in a bit density of 2.1 x 10⁷ bits per cu. in. Emphasis will be placed on the general benefits to the aerospace community of the device's high packing density and configurable 16, 32, and 64 bit word width. A specific application of the 64 Megabit SRAM module in the Fairchild Solid State Recorder is discussed to illustrate the performance advantage over conventional single chip and less conventional multi-chip package technologies.
Xu, Bin. "Shape memory polymeric nanocomposites for biological applications". Thesis, Heriot-Watt University, 2011. http://hdl.handle.net/10399/2489.
Pełny tekst źródłaHotton, Matthew. "The clinical applications of working memory training". Thesis, University of Oxford, 2016. https://ora.ox.ac.uk/objects/uuid:62a7a411-9624-4fc6-9330-3a279013db42.
Pełny tekst źródłaJosefson, Carl Elof. "Evaluation of ferroelectric materials for memory applications". Thesis, Monterey, California : Naval Postgraduate School, 1990. http://handle.dtic.mil/100.2/ADA232112.
Pełny tekst źródłaThesis Advisor(s): Panholzer, R. Second Reader: Neighbours, J.R. "June 1990." Description based on signature page. DTIC Identifiers(s): Nonvolitile memories, ferroelectric materials. Author(s) subject terms: Ferrorelectric, nonvolatile memory, radiation hard. Includes bibliographical references (p. 80-86). Also available online.
Salén, Filip. "Visualization of Dynamic Memory in C++ Applications". Thesis, Luleå tekniska universitet, Institutionen för system- och rymdteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-75286.
Pełny tekst źródłaOptimerad minneshantering är viktig för att uppnå hög prestanda i en krävande applikation. Men att upptäcka icke optimerade eller oönskade minnesbeteenden kan vara svårt utan en visuell översikt över hur minnet är strukturerat under programmets exekvering. Denna avhandling undersöker hur dynamisk minnesallokering kan visualiseras i realtid för applikationer som använder allokeringstekniken minnes\-pool. I avhandlingen beskrivs tekniska och grafiska utmaningar tillsammans med deras lösningar och de designval som gjordes. Slutresultatet är ett program som kan visualisera dynamisk minneshantering i realtid och som fokuserar på att visa en detaljerad och omfattande minnesöversikt som bevarar detaljeringsgraden över tiden.
Blomster, Katie Ann. "Schemes for reducing power and delay in SRAMs". Online access for everyone, 2006. http://www.dissertations.wsu.edu/Thesis/Summer2006/k%5Fblomster%5F071706.pdf.
Pełny tekst źródłaQi, Huan. "Memory, Movement, and MoodRetrieving the Power of Architecture as a Physical Container of Memory". University of Cincinnati / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1397734632.
Pełny tekst źródłaCheng, Yong. "Power electronics controller prototyping tool for power system applications". Master's thesis, Mississippi State : Mississippi State University, 2006. http://sun.library.msstate.edu/ETD-db/ETD-browse/browse.
Pełny tekst źródłaDas, Sauparna 1979. "Magnetic machines and power electronics for power MEMS applications". Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/34465.
Pełny tekst źródłaIncludes bibliographical references (p. 321-323).
This thesis presents the modeling, design, and characterization of microfabricated, surface-wound, permanent-magnet (PM) generators, and their power electronics, for use in Watt-level Power MEMS applications such as a microscale gas turbine engine. The generators are three-phase, axial-flux, synchronous machines, comprising a rotor with an annular PM and ferromagnetic core, and a stator with multi-turn surface windings on a soft magnetic substrate. The fabrication of the PM generators, as well as the development of their high-speed spinning rotor test stand, was carried out by collaborators at the Georgia Institute of Technology. The machines are modeled by analytically solving 2D magneto-quasistatic Maxwell's Equations as a function of radius and then integrating the field solutions over the radial span of the machine to determine the open-circuit voltage, torque and losses in the stator core. The model provides a computationally fast method to determine power and efficiency of an axial-air-gap PM machine as a function of geometry, speed and material properties. Both passive and active power electronics have been built and tested. The passive power electronics consist of a three-phase transformer and diode bridge rectifier.
(cont.) The active power electronics consist of a switch-mode rectifier based on the boost semi-bridge topology which is used to convert the unregulated AC generator voltages to a regulated 12 V DC without the need for rotor position/speed or stator terminal current/voltage sensing. At the rotational speed of 300,000 rpm, one generator converts 16.2 W of mechanical power to electrical power. Coupled to the transformer and diode bridge rectifier, it delivers 8 W DC to a resistive load. This is the highest output power ever delivered by a microscale electric generator to date. The corresponding power and current densities of 57.8 MW/m3 and 6x 108 A/m2, respectively, are much higher than those of a macroscale electric generator. At the rotational speed of 300,000 rpm, the generator and switch-mode rectifier delivered 5.5 W DC to a resistive load at a power density three times that of the passive electronics. This Watt-scale electrical power generation demonstrates the viability of scaled PM machines and power electronics for practical Power MEMS applications.
by Sauparna Das.
Ph.D.
Balachandran, Ajith. "Novel power electronic device structures for power conditioning applications". Thesis, University of Sheffield, 2014. http://etheses.whiterose.ac.uk/9574/.
Pełny tekst źródłaKameswar, Rao Vaddina. "Evaluation of A Low-power Random Access Memory Generator". Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7823.
Pełny tekst źródłaIn this work, an existing RAM generator is analysed and evaluated. Some of the aspects that were considered in the evaluation are the optimization of the basic SRAM cell, how the RAM generator can be ported to newer technologys, automating the simulation process and the creation of the workflow for the energy model.
One of the main focus of this thesis work is to optimize the basic SRAM cell. The SRAM cell which is used in the RAM generator is not optimized for area nor power. A compact layout is suggested which saves a lot of area and power. The technology that is used to create the RAM generator is old and a suitable way to port it to newer technology has also been found.
To create an energy model one has to simulate a lot of memories with a lot of data. This cannot be done in the traditional way of simulating circuits using the GUI. Hence an automation procedure has been suggested which can be made to work to create energy models by simulating the memories comprehensively.
Finally, basic ground work has been initiated by creating a workflow for the creation of the energy model.
Mohan, Nitin. "Low-Power High-Performance Ternary Content Addressable Memory Circuits". Thesis, University of Waterloo, 2006. http://hdl.handle.net/10012/2873.
Pełny tekst źródłaZHOU, YUAN. "POWER VARIATIONS AND TEST SCHEDULING FOR EMBEDDED MEMORY ARRAYS". University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1140810178.
Pełny tekst źródłaRamamoorthy, Saravanan. "LOW-POWER ADDRESS POINTER DESIGN FOR FIFO MEMORY CIRCUITS". Available to subscribers only, 2009. http://proquest.umi.com/pqdweb?did=1796420511&sid=1&Fmt=2&clientId=1509&RQT=309&VName=PQD.
Pełny tekst źródłaAlghanim, Abdulrahman A. "High power waveform measurement system enabling characterisation of high power devices including memory effects". Thesis, Cardiff University, 2008. http://orca.cf.ac.uk/54653/.
Pełny tekst źródłaMou, Duan. "Complex oxide films for memory and detector applications". Doctoral thesis, KTH, Electronic Systems Design, 1998. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-2715.
Pełny tekst źródłaAnsari, Mohammad M. "Efficient execution of concurrent applications using transactional memory". Thesis, University of Manchester, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.496238.
Pełny tekst źródłaZaffaroni, Paolo. "Nonlinear long memory models with applications in finance". Thesis, London School of Economics and Political Science (University of London), 1997. http://etheses.lse.ac.uk/1468/.
Pełny tekst źródłaTsung, Chih-qu, i 鄭智聰. "Design and Applications of Low-Power Memory Generators". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/6g3e4k.
Pełny tekst źródła國立中山大學
資訊工程學系研究所
96
Memory unit has become a major core component in most SoC designs, and thus reusable memory IP is crucial in speeding up the design process. In this thesis, we develop a low-power SRAM generator to reduce the design efforts by producing all the files required in traditional cell-based design flow. Several methods are used to reduce power consumption in the memory circuits, including hierarchical word-line architecture and block amplifiers. The SRAM generator can be extended to generate cache memory with mixed hard IP and soft IP where cache memory cells are hard IP while the cache controller is soft IP. Based on the SRAM generator, we can also generate some popular memory units such as register files, FIFO, LIFO, and delay elements used in many applications.
Panda, Soumya Ranjan. "Junctionless Nanowire : Towards Logic Circuits and Memory Applications". Thesis, 2017. http://ethesis.nitrkl.ac.in/8924/1/2017_MT_SRPanda.pdf.
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