Gotowe bibliografie tematyczne / Low Power ESD Protection

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Gotowa bibliografia na temat „Low Power ESD Protection”

Autor: Grafiati

Data publikacji: 6 września 2023

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Artykuły w czasopismach na temat "Low Power ESD Protection"

Kwon, Sang-Wook, Seung-Gu Jeong, Jeong-Min Lee i Yong-Seo Koo. "Design of Destruction Protection and Sustainability Low-Dropout Regulator Using an Electrostatic Discharge Protection Circuit". Sustainability 15, nr 13 (26.06.2023): 10126. http://dx.doi.org/10.3390/su151310126.

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In terms of sustainable power semiconductors, the embedding of an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) is an important aspect. In order for the semiconductor circuit to operate continuously or stably, a sufficient protection circuit against external surges must be configured. The purpose of this thesis is not only to effectively operate the low-dropout (LDO) regulator according to the load current, but to also secure high reliability against ESD situations by embedding an ESD protection circuit at the IC level. Moreover, the existence and nonexistence of an ESD protection circuit at the IC level is directly related to reliability. The proposed LDO regulator has high reliability against ESD situations using an embedded silicon controlled rectifier (SCR)-based ESD protection circuit in the I/O clamp and power clamp. The results revealed that the LDO regulator can not only effectively control the output voltage according to the load current, but it can also stably maintain the output voltage against the ESD surge. Moreover, the proposed LDO regulator with an embedded ESD protection circuit implemented in a 0.13 μm BCD process maintained an undershoot voltage of 21 mV and overshoot voltage of 19 mV for a load current of 300 mA.

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Song, BoBae, i YongSeo Koo. "Low Ron and high robustness ESD protection design for low‐voltage power clamp application". Electronics Letters 52, nr 18 (wrzesień 2016): 1554–55. http://dx.doi.org/10.1049/el.2016.2391.

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Hadzi-Vukovic, J., M. Jevtic, M. Glavanovics i H. Rothleitner. "The study of ESD induced defects in smart power ESD protection circuits using low frequency noise measurements". physica status solidi (a) 205, nr 11 (22.09.2008): 2544–47. http://dx.doi.org/10.1002/pssa.200780115.

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Jiang, yibo, Hui Bi, Zhihao Xu, Wei Zhao, Yuanyuan Zhang i Xiaolei Wang. "Polysilicon devices as a highly compatible ESD protection with modulable voltage and low capacitance". International Journal of Modern Physics B 35, nr 04 (2.02.2021): 2150052. http://dx.doi.org/10.1142/s0217979221500521.

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The electronic circuits fabricated in a variety of technologies for different applications are all vulnerable to the electrostatic discharge (ESD) event. In this paper, polysilicon devices are investigated as ESD protection because of the noticeable advantages such as compatibility with several technologies, low parasitical capacitance, and little noise coupling. By forming the p-i-n diode in the polysilicon layer and stacking them together, the single polysilicon diode (SPD) and cascaded polysilicon diode (CasPD) are implemented in the 0.35 [Formula: see text] high voltage diffusion process. Through DC IV/CV, transmission line pulse (TLP), and zipping test, the CasPD presents as ESD protection for an S-band RF power amplifier, with high process-compatibility, modulable voltage, low leakage current and parasitic capacitance.

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Tian, Zhuo, i Bai Cheng Li. "Conduction Uniformity Improvement of ESD Protection Device in 0.35 μm Partially-Depleted SOI Salicided CMOS Technology". Applied Mechanics and Materials 687-691 (listopad 2014): 3251–54. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.3251.

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ComparedtobulkCMOStechnology,Silicon-on-Insulator (SOI) CMOS technology has many advantages, such as low power consumption, low leakage current, low parasitic capacitance and a low soft error rate from both alpha particles and cosmic rays. However,electrostatic discharge (ESD) protection in SOI technology is still a major substantial barrier to overcome for the poor thermal conductivity of isolation oxide and the absence of vertical diode and silicon controlled rectifier (SCR).

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Chen, Shen Li, i Tzung Shian Wu. "Influence of a Deep NBL Structure on ESD/Latch-Up Immunities in the Power Device nLDMOS". Advanced Materials Research 732-733 (sierpień 2013): 1207–11. http://dx.doi.org/10.4028/www.scientific.net/amr.732-733.1207.

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In this paper, we propose a novel high-voltage (HV) nLDMOS transistor with a small Ron resistance, low trigger voltage (Vt1) and high holding voltage (Vh) characteristics. Here, we introduce a deep N+-buried-layer (NBL) into this HV nLDMOS to evaluate the ESD/latch-up (LU) parameters variation. These electric snapback parameters affect the reliability of proposed device and its performance. Eventually, we expect this proposed HV stucture processed better characteristic behaviors, which can be applied to the power electronics and ESD protection application of HV ICs.

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Berenguer, Roc, Gui Liu i Yang Xu. "A Low Power 77 GHz Low Noise Amplifier With an Area Efficient RF-ESD Protection in 65 nm CMOS". IEEE Microwave and Wireless Components Letters 20, nr 12 (grudzień 2010): 678–80. http://dx.doi.org/10.1109/lmwc.2010.2087015.

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Chang, Rong-Kun, i Ming-Dou Ker. "Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes". IEEE Transactions on Electron Devices 67, nr 1 (styczeń 2020): 40–46. http://dx.doi.org/10.1109/ted.2019.2954754.

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Zhang, Wei Qiang, Li Su, Jun Wang, Bin Bin Liu i Jian Ping Hu. "Design and Manufacture of Energy-Recycling Pads for Low-Power Chips". Key Engineering Materials 460-461 (styczeń 2011): 467–72. http://dx.doi.org/10.4028/www.scientific.net/kem.460-461.467.

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Energy-recycling output pad cells for driving adiabatic chips are designed, which have been fabricated with Chartered 0.35um process and tested. The proposed energy-recycling output pad cells include mainly bonding pads, electrostatic discharge (ESD) protection circuits, and two stage energy-recycling buffers that are used to drive the large load capacitances on chip pads. The two stage energy-recycling buffers are realized using CPAL (Complementary Pass-transistor Adiabatic Logic) and PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration), respectively. For comparison, a conventional output pad cell is also embedded in the test chip. The function verifications and energy loss tests for the three output pad cells are carried out. The energy consumption of the proposed two energy-recycling output pad cells has large savings over a wide range of frequencies, as compared with the conventional CMOS counterparts, since the energy on large load capacitances in the chip pads can be well recycled.

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Cheng, Guoxiao, Zhiqun Li, Pengfei Yue, Lei Luo, Xiaodong He i Boyong He. "A 6.5-kV HBM ESD-protected high-gain LNA using cascaded L-match input network". Modern Physics Letters B 33, nr 23 (16.08.2019): 1950280. http://dx.doi.org/10.1142/s0217984919502804.

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A wideband (2–3 GHz) three-stage low noise amplifier (LNA) with electrostatic discharge (ESD) protection circuits using 0.18 [Formula: see text]m CMOS technology is presented in this paper. Low-parasitic silicon-controlled rectifier (SCR) devices are co-designed with the LNA in the form of [Formula: see text]-parameters, and a new cascaded L-match input network is proposed to reduce the parasitic effects of them on the input matching. To improve linearity performance, an optimized multiple-gated transistors method (MGTR) is proposed and applied to the third stage, which takes both transconductance [Formula: see text] and third-order nonlinear coefficient [Formula: see text] into consideration. The measured results show a wide input matching across 2–8 GHz and a high third-order input intercept point (IIP3) of −12.8 dBm. The peak power gain can achieve 29.1 dB, and the noise figure (NF) is in a range of 3.1–3.6 dB within the 3-dB bandwidth. Using SCR devices with low parasitic capacitance of [Formula: see text]80 fF and robust gate-driven power clamps, a 6.5-kV human body mode (HBM) ESD performance is obtained.

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Rozprawy doktorskie na temat "Low Power ESD Protection"

Moghadasiriseh, Amirhasan. "Analysis and Modeling of Advanced Power Control and Protection Requirements for Integrating Renewable Energy Sources in Smart Grid". FIU Digital Commons, 2016. http://digitalcommons.fiu.edu/etd/2469.

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Attempts to reduce greenhouse gas emissions are promising with the recent dramatic increase of installed renewable energy sources (RES) capacity. Integration of large intermittent renewable resources affects smart grid systems in several significant ways, such as transient and voltage stability, existing protection scheme, and power leveling and energy balancing. To protect the grid from threats related to these issues, utilities impose rigorous technical requirements, more importantly, focusing on fault ride through requirements and active/reactive power responses following disturbances. This dissertation is aimed at developing and verifying the advanced and algorithmic methods for specification of protection schemes, reactive power capability and power control requirements for interconnection of the RESs to the smart grid systems. The first findings of this dissertation verified that the integration of large RESs become more promising from the energy-saving, and downsizing perspective by introducing a resistive superconducting fault current limiter (SFCL) as a self-healing equipment. The proposed SFCL decreased the activation of the conventional control scheme for the wind power plant (WPP), such as dc braking chopper and fast pitch angle control systems, thereby increased the reliability of the system. A static synchronous compensator (STATCOM) has been proposed to assist with the uninterrupted operation of the doubly-fed induction generators (DFIGs)-based WTs during grid disturbances. The key motivation of this study was to design a new computational intelligence technique based on a multi-objective optimization problem (MOP), for the online coordinated reactive power control between the DFIG and the STATCOM in order to improve the low voltage ride-through (LVRT) capability of the WT during the fault, and to smooth low-frequency oscillations of the active power during the recovery. Furthermore, the application of a three-phase single-stage module-integrated converter (MIC) incorporated into a grid-tied photovoltaic (PV) system was investigated in this dissertation. A new current control scheme based on multivariable PI controller, with a faster dynamic and superior axis decoupling capability compared with the conventional PI control method, was developed and experimentally evaluated for three-phase PV MIC system. Finally, a study was conducted based on the framework of stochastic game theory to enable a power system to dynamically survive concurrent severe multi-failure events, before such failures turn into a full blown cascading failure. This effort provides reliable strategies in the form of insightful guidelines on how to deploy limited budgets for protecting critical components of the smart grid systems.

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Latzo, Curtis Thomas. "Approaches to Arc Flash Hazard Mitigation in 600 Volt Power Systems". Scholar Commons, 2011. http://scholarcommons.usf.edu/etd/3198.

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ABSTRACT Federal regulations have recognized that arc flash hazards are a critical source of potential injury. As a consequence, in order to work on some electrical equipment, the energy source must be completely shut-down. However, power distribution systems in mission critical facilities such as hospitals and data centers must sometimes remain energized while being maintained. In recent years the Arc Flash Hazard Analysis has emerged as a power system tool that informs the qualified technician of the incident energy at the equipment to be maintained and recommends the proper protective equipment to wear. Due to codes, standards and historically acceptable design methods, the Arc Flash Hazard is often higher and more dangerous than necessary. This dissertation presents detailed methodology and proposes alternative strategies to be implemented at the design stage of 600 volt facility power distribution systems which will decrease the Arc Flash Hazard Exposure when compared to widely used code acceptable design strategies. Software models have been developed for different locations throughout a power system. These software model simulations will analyze the Arc Flash Hazard in a system designed with typical mainstream code acceptable methods. The model will be changed to show implementation of arc flash mitigation techniques at the system design level. The computer simulations after the mitigation techniques will show significant lowering of the Arc Flash Hazard Exposure.

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Li, You. "Design of low-capacitance and high-speed electrostatic discharge (ESD) devices for low-voltage protection applications". Doctoral diss., University of Central Florida, 2010. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4551.

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Electrostatic discharge (ESD) is defined as the transfer of charge between bodies at different potentials. The electrostatic discharge induced integrated circuit damages occur throughout the whole life of a product from the manufacturing, testing, shipping, handing, to end user operating stages. This is particularly true as microelectronics technology continues shrink to nano-metric dimensions. The ESD related failures is a major IC reliability concern and results in a loss of millions dollars to the semiconductor industry each year. Several ESD stress models and test methods have been developed to reproduce the real world ESD discharge events and quantify the sensitivity of ESD protection structures. The basic ESD models are: Human body model (HBM), Machine model (MM), and Charged device model (CDM). To avoid or reduce the IC failure due to ESD, the on-chip ESD protection structures and schemes have been implemented to discharge ESD current and clamp overstress voltage under different ESD stress events. Because of its simple structure and good performance, the junction diode is widely used in on-chip ESD protection applications. This is particularly true for ESD protection of low-voltage ICs where a relatively low trigger voltage for the ESD protection device is required. However, when the diode operates under the ESD stress, its current density and temperature are far beyond the normal conditions and the device is in danger of being damaged. For the design of effective ESD protection solution, the ESD robustness and low parasitic capacitance are two major concerns. The ESD robustness is usually defined after the failure current It2 and on-state resistance Ron. The transmission line pulsing (TLP) measurement is a very effective tool for evaluating the ESD robustness of a circuit or single element. This is particularly helpful in characterizing the effect of HBM stress where the ESD-induced damages are more likely due to thermal failures.; The recent industry data indicates the charged device model (CDM) ESD event becomes increasingly important in today's manufacturing environment and packaging technology. This event generates highly destructive pulses with a very short rise time and very small duration. TLP has been modified to probe CDM ESD protection effectiveness. The pulse width was reduced to the range of 1-10 ns to mimic the very fast transient of the CDM pulses. Such a very fast TLP (VFTLP) testing has been used frequently for CDM ESD characterization. The overshoot voltage and turn-on time are two key considerations for designing the CDM ESD protection devices. A relatively high overshoot voltage can cause failure of the protection devices as well as the protected devices, and a relatively long turn-on time may not switch on the protection device fast enough to effectively protect the core circuit against the CDM stress. The overshoot voltage and turn-on time of an ESD protection device can be observed and extracted from the voltage versus time waveforms measured from the VFTLP testing. Transient behaviors of polysilicon-bound diodes subject to pulses generated by the VFTLP tester are characterized for fast ESD events such as the charged device model. The effects of changing devices' dimension parameters on the transient behaviors and on the overshoot voltage and turn-on time are studied. The correlation between the diode failure and poly-gate configuration under the VFTLP stress is also investigated. Silicon-controlled rectifier (SCR) is another widely used ESD device for protecting the I/O pins and power supply rails of integrated circuits. Multiple fingers are often needed to achieve optimal ESD protection performance, but the uniformity of finger triggering and current flow is always a concern for multi-finger SCR devices operating under the post-snapback region.; Two types of diodes with different anode/cathode isolation technologies will be investigated for their ESD performance: one with a LOCOS (Local Oxidation of Silicon) oxide isolation called the LOCOS-bound diode, the other with a polysilicon gate isolation called the polysilicon-bound diode. We first examine the ESD performance of the LOCOS-bound diode. The effects of different diode geometries, metal connection patterns, dimensions and junction configurations on the ESD robustness and parasitic capacitance are investigated experimentally. The devices considered are N+/P-well junction LOCOS-bound diodes having different device widths, lengths and finger numbers, but the approach applies generally to the P+/N-well junction diode as well. The results provide useful insights into optimizing the diode for robust HBM ESD protection applications. Then, the current carrying and voltage clamping capabilities of LOCOS- and polysilicon-bound diodes are compared and investigated based on both TCAD simulation and experimental results. Comparison of these capabilities leads to the conclusion that the polysilicon-bound diode is more suited for ESD protection applications due to its higher performance. The effects of polysilicon-bound diode's design parameters, including the device width, anode/cathode length, finger number, poly-gate length, terminal connection and metal topology, on the ESD robustness are studied. Two figures of merits, FOM_It2 and FOM_Ron, are developed to better assess the effects of different parameters on polysilicon-bound diode's overall ESD performance. As latest generation package styles such as mBGAs, SOTs, SC70s, and CSPs are going to the millimeter-range dimensions, they are often effectively too small for people to handle with fingers.; Without a proper understanding of the finger turn-on mechanism, design and realization of robust SCRs for ESD protection applications are not possible. Two two-finger SCRs with different combinations of anode/cathode regions are considered, and their finger turn-on uniformities are analyzed based on the I-V characteristics obtained from the transmission line pulsing (TLP) tester. The dV/dt effect of pulses with different rise times on the finger turn-on behavior of the SCRs are also investigated experimentally. In this work, unless noted otherwise, all the measurements are conducted using the Barth 4002 transmission line pulsing (TLP) and Barth 4012 very-fast transmission line pulsing (VFTLP) testers.
ID: 029050342; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2010.; Includes bibliographical references (p. 92-100).
Ph.D.
Doctorate
Department of Electrical Engineering and Computer Science
Engineering and Computer Science

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Cao, Yiqun [Verfasser], Stephan [Akademischer Betreuer] Frei i Bernd [Gutachter] Deutschmann. "High-voltage ESD structures and ESD protection concepts in smart power technologies / Yiqun Cao ; Gutachter: Bernd Deutschmann ; Betreuer: Stephan Frei". Dortmund : Universitätsbibliothek Dortmund, 2019. http://d-nb.info/1200209605/34.

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Baum, Keith Warren 1959. "ESD effects on the radiation response of low power vertical DMOS N-channel transistors". Thesis, The University of Arizona, 1991. http://hdl.handle.net/10150/277850.

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The effect of non-catastrophic human body model positive electrostatic discharge pulses on the radiation response of low power VDMOS N-channel transistors is explored. The effect of multiple pulses of HBM ESD is to cause a change in threshold-voltage shifts between stressed and non-stressed devices when exposed to Co₆₀ gamma radiation. This difference is due to the build-up of a space charge region next to the Si/SiO₂ interface. This space charge region reduces the net electric field across the gate oxide when biased with a positive voltage and thus reduces the formation of holes and interface traps. Therefore, the ESD stressed devices appear to be less sensitive to radiation.

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Salomonsson, Daniel. "Modeling, Control and Protection of Low-Voltage DC Microgrids". Doctoral thesis, Stockholm : Elektriska energisystem, Electric Power Systems, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4666.

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袁綺珊 i Yee-shan Cherry Yuen. "High impedance fault detection and overvoltage protection in low voltage power systems". Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1998. http://hub.hku.hk/bib/B31222146.

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Yuen, Yee-shan Cherry. "High impedance fault detection and overvoltage protection in low voltage power systems /". Hong Kong : University of Hong Kong, 1998. http://sunzi.lib.hku.hk/hkuto/record.jsp?B20735297.

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Gammon, Tammy Lea. "Improved arcing-fault current models for low-voltage power systems (<1kV)". Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15675.

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Muhammad, Wasim. "CMOS LNA Design for Multi-Standard Applications". Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7841.

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This thesis discusses design of narrowband low noise amplifiers for multi¬standard applications. The target of this work is to design a low noise ampli¬fier(LNA) for DCS1800 and Bluetooth standard frequency bands. Various designs for narrowband multi-standard LNAs have been studied and a new design for tunable multi-standard LNA has been presented and designed using accumulation mode MOS varactors.

As this design includes on-chip spiral inductors, the design, modelling and layout of on-chip inductors have been discussed briefly. The tool used for this purpose is ASITIC.

Also ESD protection techniques for RF circuits and their effect on LNA per¬formance has been discussed.

Finally fully differential LNA has been designed in O.35um AMS thick metal CMOS process using Cadence SpectreRF. The design also includes ESD pro¬tection at the input of LNA.

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Książki na temat "Low Power ESD Protection"

Hasse, Peter. Overvoltage protection of low voltage systems. London: P. Peregrinus on behalf of the Institution of Electrical Engineers, 1992.

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National Institute of Standards and Technology (U.S.), red. Surge protection in low-voltage AC power circuits-- an anthology. Gaithersburg, MD: U.S. Dept. of Commerce, Technology Administration, National Institute of Standards and Technology, 2001.

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Martzloff, François D. Surge protection in low-voltage AC power circuits, an 8-part anthology. Gaithersburg, MD]: U.S. Dept. of Commerce, Technology Administration, National Institute of Standards and Technology, 2001.

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IEEE Power Engineering Society. Surge Protective Devices Committee., Institute of Electrical and Electronics Engineers. i IEEE-SA Standards Board, red. IEEE standard test specifications for surge-protective devices for low-voltage AC power circuits. New York, N.Y., USA: Institute of Electrical and Electronics Engineers, 2000.

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Institute Of Electrical and Electronics Engineers. IEEE recommended practice on surge voltages in low-voltage AC power circuits. New York: IEEE, 1991.

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IEEE Power Engineering Society. Surge Protective Devices Committee. i National Electrical Manufacturers Association, red. IEEE guide on surge testing for equipment connected to low-voltage AC power circuits. New York, NY: Institute of Electrical and Electronics Engineers, 1987.

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Keuneke, Robin. Total breast health: The power food solution for protection and wellness. New York, NY: Kensington Pub., 1998.

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Części książek na temat "Low Power ESD Protection"

Mikhalev, Vasily, Laurent Gomez, Frederik Armknecht i José Márquez. "Towards End-to-End Data Protection in Low-Power Networks". W Computer Security, 3–18. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-72817-9_1.

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Vashchenko, Vladislav A., i Andrei Shibkov. "Power Management Circuits’ ESD Protection". W ESD Design for Analog Circuits, 317–93. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6565-3_7.

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Lu, Guangyi, Yuan Wang, Xuelin Zhang, Song Jia i Xing Zhang. "A Novel Multi-RC-Triggered Power Clamp Circuit for On-Chip ESD Protection". W Lecture Notes in Electrical Engineering, 1839–46. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-4981-2_201.

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Liu, Jizhi, Zhiwei Liu, Fei Hou, Hui Cheng, Liu Zhao i Rui Tian. "Low Trigger Voltage and High Turn-On Speed SCR for ESD Protection in Nanometer Technology". W Outlook and Challenges of Nano Devices, Sensors, and MEMS, 151–81. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-50824-5_6.

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Zhang, Xuelin, Yuan Wang, Guangyi Lu, Song Jia i Xing Zhang. "A Low Leakage Power-Rail ESD Clamp Circuit with Adjustable Holding Voltage in Nanoscale Process". W Lecture Notes in Electrical Engineering, 1715–23. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-4981-2_188.

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Magdy, Gaber, Gaber Shabib, Adel A. Elbaset i Yasunori Mitani. "A Comprehensive Digital Protection Scheme for Low-inertia Microgrids Considering High Penetration of Renewables". W Renewable Power Systems Dynamic Security, 39–57. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-33455-0_3.

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Zhu, Zhengwei, i Zongwen Chen. "Application of Fuzzy Control in Low-Temperature Wind Power Generator Protection System". W Advances in Intelligent and Soft Computing, 1–7. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-25188-7_1.

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Dong, Aihua, Qiongfang Yu, Yangmei Dong i Liang Li. "The Summary of Low-Voltage Power Distribution Switch Fault Arc Detection and Protection Technology". W Lecture Notes in Electrical Engineering, 711–18. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-21697-8_90.

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Liu, Huiping, Xiaoqing Zhang i Kejie Huang. "Analysis of the Protection of a Simplified Surge Protective Device for Low-Voltage AC Power System". W Lecture Notes in Electrical Engineering, 1147–54. Berlin, Heidelberg: Springer Berlin Heidelberg, 2016. http://dx.doi.org/10.1007/978-3-662-48768-6_128.

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Zhang, Xiaoyue, Jin Wang, Ting Liu, Shuhao Zhao, Bing Gao i Huajian Wu. "Low Carbon Economic Operation of Integrated Energy Systems Considering Power-to-Gas Thermal Recovery and Demand Response". W Proceedings of the 7th PURPLE MOUNTAIN FORUM on Smart Grid Protection and Control (PMF2022), 92–105. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0063-3_7.

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Streszczenia konferencji na temat "Low Power ESD Protection"

Hossain, E., S. S. Chowdhury, M. Matin, A. M. Ahmed i M. M. A. Hakim. "Investigation on short channel GGNMOS ESD protection device for low power IC". W 2020 IEEE Region 10 Symposium (TENSYMP). IEEE, 2020. http://dx.doi.org/10.1109/tensymp50017.2020.9230678.

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Cao, Jian, Zhenxu Ye, Yuan Wang, Guangyi Lu i Xing Zhang. "A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network". W 2015 IEEE 11th International Conference on ASIC (ASICON ). IEEE, 2015. http://dx.doi.org/10.1109/asicon.2015.7516982.

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Kearney, Ian, i Hank Sung. "Integrated ESD Robustness through Device Analysis of Ultra-Small Low Voltage Power MOSFETs". W ISTFA 2014. ASM International, 2014. http://dx.doi.org/10.31399/asm.cp.istfa2014p0350.

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Abstract Low voltage power MOSFETs often integrate voltage spike protection and gate oxide ESD protection. The basic concept of complete-static protection for the power MOSFETs is the prevention of static build-up where possible and the quick, reliable removal of existing charges. The power MOSFET gate is equivalent to a low voltage low leakage capacitor. The capacitor plates are formed primarily by the silicon gate and source metallization. The capacitor dielectric is the silicon oxide gate insulation. Smaller devices have less capacitance and require less charge per volt and are therefore more susceptible to ESD than larger MOSFETs. A FemtoFETTM is an ultra-small, low on-resistance MOSFET transistor for space-constrained handheld applications, such as smartphones and tablets. An ESD event, for example, between a fingertip and the communication-port connectors of a cell phone or tablet may cause permanent system damage. Through electrical characterization and global isolation by active photon emission, the authors identify and distinguish ESD failures. Thermographic analysis provided additional insight enabling further separation of ESD failmodes. This paper emphasizes the role of failure analysis in new product development from the create phase through to product ramp. Coupled with device electrical simulation, the analysis observations led to further design enhancement.

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Machado, Wilson J. Bortoletto, i Calvin Plett. "Impact of ESD Protection and Power Supply Decoupling on 10 GHz Low Noise Amplifier". W the 27th Symposium. New York, New York, USA: ACM Press, 2014. http://dx.doi.org/10.1145/2660540.2660551.

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Ostman, Kim B., Erlend Strandvik, Phil Corbishley, Tor Oyvind Vedal i Mika Salmi. "Analysis and Design of ESD Protection for Robust Low-Power Pierce Crystal Oscillator Startup". W 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE, 2018. http://dx.doi.org/10.1109/norchip.2018.8573499.

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Lai, Wen-Cheng, Wei-Te Liu, Yan-Cu Lin i Sheng-Lyang Jang. "Low Power Device Phase Locked Loop with Gm-Boosted Charge Pump and ESD Protection". W 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2019. http://dx.doi.org/10.1109/edssc.2019.8754354.

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Yu, Bo, Yang Wang, Yuye Zhang, Wenjie Guan, Zhiqin Deng i Hongjiao Yang. "Low Trigger-Voltage Design of SCR Structure with Power-Rail ESD Clamp Circuit Network for On-Chip ESD Protection". W 2022 10th International Symposium on Next-Generation Electronics (ISNE). IEEE, 2023. http://dx.doi.org/10.1109/isne56211.2023.10221629.

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Ta-Lee Yu, Li-Hsien Fan, Huijuan Cheng, Jing Liu, Xianmin Chen, Jingjing Wang, Ying Ma i in. "A novel ESD protection circuit for ultra-deep-submicron low power mixed-signal IC designs". W 2007 7th International Conference on ASIC. IEEE, 2007. http://dx.doi.org/10.1109/icasic.2007.4415648.

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Tsai, Ming-Hsien, Shawn S. H. Hsu, Fu-Lung Hsueh, Chewn-Pu Jou, Tzu-Jin Yeh, Ming-Hsiang Song i Jen-Chou Tseng. "An ultra-low power K-band low-noise amplifier co-designed with ESD protection in 40-nm CMOS". W Technology (ICICDT). IEEE, 2011. http://dx.doi.org/10.1109/icicdt.2011.5783220.

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Qi, Zhao, Ming Qiao, Fei Zhao, Zhaoji Li i Bo Zhang. "Novel Integrated Low Capacitance Transient Voltage Suppressor Array with Capacitance Equalization Technique for System-Level EOS/ESD Protection". W 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD). IEEE, 2021. http://dx.doi.org/10.23919/ispsd50666.2021.9452195.

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Raporty organizacyjne na temat "Low Power ESD Protection"

Martzloff, Francois D. Surge protection in low-voltage AC power circuits - an anthology, part 1 - annotated bibliography. Gaithersburg, MD: National Institute of Standards and Technology, 2001. http://dx.doi.org/10.6028/nist.ir.6714-1.

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Martzloff, Francois D. Surge protection in low-voltage AC power circuits - an anthology, part 2 - development of standards reality checks. Gaithersburg, MD: National Institute of Standards and Technology, 2002. http://dx.doi.org/10.6028/nist.ir.6714-2.

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Martzloff, Francois D. Surge protection in low-voltage AC power circuits - an anthology, part 4 - propagation and coupling of surges. Gaithersburg, MD: National Institute of Standards and Technology, 2002. http://dx.doi.org/10.6028/nist.ir.6714-4.

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Martzloff, Francois D. Surge protection in low-voltage AC power circuits - an anthology, part 8 - Coordination of cascaded surge-protective devices. Gaithersburg, MD: National Institute of Standards and Technology, 2002. http://dx.doi.org/10.6028/nist.ir.6714-8.

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Martzloff, Francois D. Surge protection in low-voltage AC power circuits - an anthology, part 3 - recorded surge occurrences, surveys and staged tests. Gaithersburg, MD: National Institute of Standards and Technology, 2002. http://dx.doi.org/10.6028/nist.ir.6714-3.

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Macdonald. L51750 New Technique to Assess Level of Cathodic Protection in Underground Pipe Systems (Phases I and II). Chantilly, Virginia: Pipeline Research Council International, Inc. (PRCI), luty 1996. http://dx.doi.org/10.55274/r0010611.

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This report introduces the Variable Frequency Impedance Tomography (VFIT) method for assessing the effectiveness of non-interruptible power supplies (sacrificial anodes) for protecting coated buried pipe. This method imposes a low-amplitude alternating voltage between the pipe and a reference electrode placed on the surface. A potentiostat/galvanostat controls the electric potential by modulating the current between the pipe and a surface counter electrode. The principle interpretive tool used in this study was an Artificial Neural Network (ANN) that had been \trained\" on simulated pipe with a defective coating and on field data from a test pipe.

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Olwande, John, Miltone Ayieko, John Mukundi i Nicholas Odhiambo. A Multi-Phase Assessment of the Effects of COVID-19 on Food Systems and Rural Livelihoods in Kenya. Institute of Development Studies (IDS), grudzień 2021. http://dx.doi.org/10.19088/apra.2021.037.

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Kenya confirmed its first case of COVID-19 on 12 March 2020. Like many governments across the world, the Kenyan government implemented various measures aimed at slowing down local spread of the virus and cushioning the population against the negative economic effects of the pandemic and the associated policy restrictions. International organisations and researchers postulated that the measures would negatively affect economic activities and livelihoods, with undesirable implications for poverty and food insecurity. Particularly vulnerable would be populations in developing countries such as Kenya, where many people depend on food systems for their livelihoods, and the majority of those are smallholder farmers who often have low economic power. The objective of this rapid assessment was to investigate the impact of COVID-19 on the food system and the sub-set of the population largely dependent on agriculture in Kenya to inform actions that can assure protection of rural livelihoods and continued access to adequate and affordable food of acceptable quality to the population. This report presents results of that rapid assessment.

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Page, Martin, Bruce MacAllister, Marissa Campobasso, Angela Urban, Catherine Thomas, Clinton Cender, Clint Arnett i in. Optimizing the Harmful Algal Bloom Interception, Treatment, and Transformation System (HABITATS). Engineer Research and Development Center (U.S.), październik 2021. http://dx.doi.org/10.21079/11681/42223.

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Harmful algal blooms (HABs) continue to affect lakes and waterways across the nation, often resulting in environmental and economic damage at regional scales. The US Army Engineer Research and Development Center (ERDC) and collaborators have continued research on the Harmful Algal Bloom Interception, Treatment, and Transformation System (HABITATS) project to develop a rapidly deployable and scalable system for mitigating large HABs. The second year of the project focused on optimization research, including (1) development of a new organic flocculant formulation for neutralization and flotation of algal cells; (2) testing and initial optimization of a new, high-throughput biomass dewatering system with low power requirements; (3) development, design, assembly, and initial testing of the first shipboard HABITATS prototype; (4) execution of two field pilot studies of interception and treatment systems in coordination with the Florida Department of Environmental Protection and New York State Department of Environmental Conservation; (5) conversion of algal biomass into biocrude fuel at pilot scale with a 33% increase in yield compared to the previous bench scale continuous-flow reactor studies; and (6) refinement of a scalability analysis and optimization model to guide the future development of full-scale prototypes.

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Kiefner, Maxey i Eiber. L51607 Pipeline Coating Impedance Effect on Powerline Fault Current Coupling. Chantilly, Virginia: Pipeline Research Council International, Inc. (PRCI), styczeń 1989. http://dx.doi.org/10.55274/r0010294.

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Prior research leading to the development of predictive electromagnetic coupling computer codes has shown that the coating conductance is the principal factor in determining the response of a pipeline to magnetic induction transmission line. Under power line fault conditions, a high voltage may stress the coating causing a significant change in its conductance, and hence, the coupling response. Based upon laboratory experimentation and analysis, a model has been developed which allows prediction of the modified coating characteristics when subjected to high voltages during fault situations. The program objective was the investigation of a method to determine the high voltage behavior of an existing coating from low voltage in-situ field measurements. Such a method appeared conceptually feasible for non-porous coatings whose conductance is primarily a result of current leakage through existing holidays. However, limited testing has shown that difficulties in determining the steel-electrolyte capacitance limit the application of the method. Methods for field measurement of the pipeline coating conductance were studied for both DC and AC signal excitation. AC techniques offer the advantage that cathodic protection current interruption is not required, thus eliminating depolarization effects. However, ac field measurement techniques need additional refinement before these methods can be generally applied.

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