Artykuły w czasopismach: „LOW NOISE ADC”

1

McCartney, Damien, Adrian Sherry, John O'Dowd, and Pat Hickey. "Low-noise low-drift transducer ADC." Computer Standards & Interfaces 21, no. 2 (1999): 102. http://dx.doi.org/10.1016/s0920-5489(99)91937-2.

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McCartney, D., A. Sherry, J. O'Dowd, and P. Hickey. "A low-noise low-drift transducer ADC." IEEE Journal of Solid-State Circuits 32, no. 7 (1997): 959–67. http://dx.doi.org/10.1109/4.597286.

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Ren, Si Kui, and Zhi Qun Li. "Design of Low Voltage Low Power ADC for WSN Node." Advanced Materials Research 760-762 (September 2013): 561–66. http://dx.doi.org/10.4028/www.scientific.net/amr.760-762.561.

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This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm2. It results in a figure-of-merit (FOM) of 0.11pJ/step.

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Choi, Gyuri, Hyunwoo Heo, Donggeun You, et al. "A Low-Power, Low-Noise, Resistive-Bridge Microsensor Readout Circuit with Chopper-Stabilized Recycling Folded Cascode Instrumentation Amplifier." Applied Sciences 11, no. 17 (2021): 7982. http://dx.doi.org/10.3390/app11177982.

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In this paper, a low-power and low-noise readout circuit for resistive-bridge microsensors is presented. The chopper-stabilized, recycling folded cascode current-feedback instrumentation amplifier (IA) is proposed to achieve the low-power, low-noise, and high-input impedance. The chopper-stabilized, recycling folded cascode topology (with a Monticelli-style, class-AB output stage) can enhance the overall noise characteristic, gain, and slew rate. The readout circuit consists of a chopper-stabilized, recycling folded cascode IA, low-pass filter (LPF), ADC driving buffer, and 12-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). The prototype readout circuit is implemented in a standard 0.18 µm CMOS process, with an active area of 12.5 mm2. The measured input-referred noise at 1 Hz is 86.6 nV/√Hz and the noise efficiency factor (NEF) is 4.94, respectively. The total current consumption is 2.23 μA, with a 1.8 V power supply.

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Li, Jiamin, Qian Lv, Jing Yang, Pengcheng Zhu, and Xiaohu You. "Spectral and Energy Efficiency of Distributed Massive MIMO with Low-Resolution ADC." Electronics 7, no. 12 (2018): 391. http://dx.doi.org/10.3390/electronics7120391.

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In this paper, considering a more realistic case where the low-resolution analog-to-digital convertors (ADCs) are employed at receiver antennas, we investigate the spectral and energy efficiency in multi-cell multi-user distributed massive multi-input multi-output (MIMO) systems with two linear receivers. An additive quantization noise model is provided first to study the effects of quantization noise. Using the model provided, the closed-form expressions for the uplink achievable rates with a zero-forcing (ZF) receiver and a maximum ratio combination (MRC) receiver under quantization noise and pilot contamination are derived. Furthermore, the asymptotic achievable rates are also given when the number of quantization bits, the per user transmit power, and the number of antennas per remote antenna unit (RAU) go to infinity, respectively. Numerical results prove that the theoretical analysis is accurate and show that quantization noise degrades the performance in spectral efficiency, but the growth in the number of antennas can compensate for the degradation. Furthermore, low-resolution ADCs with 3 or 4 bits outperform perfect ADCs in energy efficiency. Numerical results imply that it is preferable to use low-resolution ADCs in distributed massive MIMO systems.

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ZHU, ZHANGMING, HONGBING WU, GUANGWEN YU, YANHONG LI, LIANXI LIU, and YINTANG YANG. "A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC." Journal of Circuits, Systems and Computers 22, no. 04 (2013): 1350018. http://dx.doi.org/10.1142/s0218126613500187.

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A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

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Lee, Sang-Hun, and Won-Young Lee. "A 10-Bit 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparator for Input-Referred Noise Reduction." Sensors 22, no. 16 (2022): 6078. http://dx.doi.org/10.3390/s22166078.

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This paper presents a low noise 0.6-V 400-kS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for input-referred noise reduction. A dual-domain comparator is proposed to optimize the power, noise, and sampling rate of the ADC in the 10-bit conversion. In order to optimize the figure of merits (FoM) of the ADC, the 10-bit conversion consists of a 7-bit coarse conversion with the double-tail dynamic comparator and a 3-bit fine conversion with the VCDL-based time-domain comparator. An asynchronous timing controller is also proposed to improve the ADC sampling rate and optimize the power consumption of the dual-domain comparator. The proposed SAR ADC is fabricated in 180-nm CMOS technology with an area of 0.836 mm2. At a 0.6-V supply voltage and a 400-kS/s sampling rate, the implemented SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 56.59 dB and an effective number of bits (ENOB) of 9.16 bits. The peak values of DNL and INL are +0.47/−0.53 LSB and +0.92/−0.64 LSB, respectively. The FoM is 10.31 fJ/conversion step with a power consumption of 2.36 μW.

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Xu, Daiguo, Kaikai Xu, Shiliu Xu, Lu Liu, and Tao Liu. "A System-Level Correction SAR ADC with Noise-Tolerant Technique." Journal of Circuits, Systems and Computers 27, no. 13 (2018): 1850202. http://dx.doi.org/10.1142/s021812661850202x.

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A system-level correction successive approximation register analog-to-digital converter (SAR ADC) with regulated comparator of noise-tolerant technique is proposed. First, a substrate voltage boost technique is provided to improve the linearity and speed of sampling switch. Secondly, the proposed SAR ADC provides a comparator of noise regulation without redundant comparison cycle. The proposed comparator would be regulated in high-speed large noise state in large input differential signals. In the condition of small input differential signals, the comparator would be adjusted to low-speed small noise state. Furthermore, a high-speed low-power technique is proposed to optimize the performance of dynamic comparator. Additionally, a fast SAR logic structure is provided to increase the conversion speed of SAR ADC. To demonstrate the proposed techniques, a design example of SAR ADC is fabricated in 65[Formula: see text]nm CMOS technology. The SAR ADC is able to tolerate about 1.1 LSB noise errors in post-simulation with the operation state regulated automatically. The core occupies an active area of only 0.025[Formula: see text]mm2 and consumes 1.5[Formula: see text]mW. Measurement results achieve SFDR [Formula: see text][Formula: see text]dB and SNDR [Formula: see text][Formula: see text]dB, resulting in the FOM of 21.6[Formula: see text]fJ per conversion step.

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Ding, Wei, Heng Liu, and Tao Wu. "Optimizing for High Resolution ADC Model With Combined Architecture." International Journal of Cognitive Informatics and Natural Intelligence 14, no. 3 (2020): 118–32. http://dx.doi.org/10.4018/ijcini.2020070106.

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High resolution analog-digital conversion (ADC) is a key instrument to convert analog signals to digital signals, which is deployed in data acquisition system to match high resolution analog signals from seismometers systems. To achieve high resolution, architecture of Σ-△ oversampling or pipeline ADC architecture have following disadvantages: high power consumption, low linearity of modulators, and complex structure. This work presents a novel model architecture, which design principle is validated by mathematical formulations which combined advantages of both pipeline and Σ-△oversampling ADC architecture. By discussing the adverse effects of the whole ADC architecture with an external noise theoretically, an amended theoretical model is proposed according to the assessment result of a noise simulation algorithm. The simulation results represent that the whole performance of combined architecture is determined by the noise level of integrator and subtractor. Using these two components with a noise index no more than 10-7 V/√Hz, the resolution of the prototype can achieve a reservation of 144.5 dB.

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Sheng, Shuran, Peng Chen, Yuxuan Yao, Lenan Wu, and Zhimin Chen. "Atomic Network-Based DOA Estimation Using Low-Bit ADC." Electronics 10, no. 6 (2021): 738. http://dx.doi.org/10.3390/electronics10060738.

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In the direction of arrival (DOA) estimation problem, when a low-bit analog to digital converter (ADC) is used, the estimation performance severely deteriorates. In this paper, the DOA estimation problem is considered in a low-cost direction finding system with low-bit ADC. To eliminate quantization noise, we propose a novel network ADCnet, which is a composition of fully connected layers and exponential linear unit (ELU) layers, and the input signals are the received signals using low-bit ADC. After the ADCnet, an AtomicNet is also proposed to estimate the DOA from the denoised signals, where atomic vectors are corresponding to the steer vectors. A loss function considering both the reconstruction performance and the sparsity is proposed in the AtomicNet. Different from the exiting atomic norm-based methods, the proposed method can avoid an optimization problem and estimate the DOA with lower computational complexity. Simulation results show that the proposed method outperforms the existing methods in the DOA estimation performance using low-bit ADC.

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Zhuang, Haoyu, Jiaxin Liu, He Tang, Xizhu Peng, and Nan Sun. "A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC." IEEE Journal of Solid-State Circuits 56, no. 9 (2021): 2680–90. http://dx.doi.org/10.1109/jssc.2021.3072034.

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Rajaee, Omid, Seiji Takeuchi, Mitsuru Aniya, Koichi Hamashita, and Un-Ku Moon. "Low-OSR Over-Ranging Hybrid ADC Incorporating Noise-Shaped Two-Step Quantizer." IEEE Journal of Solid-State Circuits 46, no. 11 (2011): 2458–68. http://dx.doi.org/10.1109/jssc.2011.2164293.

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Vera, Pablo, Andreas Wiesbauer та Susana Paton. "An Analysis of Noise in Multi-Bit ΣΔ Modulators with Low-Frequency Input Signals". Sensors 22, № 19 (2022): 7458. http://dx.doi.org/10.3390/s22197458.

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Digital and smart sensors are commonly implemented using multi-bit ΣΔ Modulators. Undesired signals can be present at the ADC input, such as low-frequency signals with medium or high amplitude, as a consequence of mechanical artifacts in the MEMS and/or temporary signal overload. Simulations and measurements of those sensors with such signals show temporary increments of in-band noise power. This paper investigates the factors that produce this transient performance loss. Interestingly, noise increments happen when the modulator is forced to toggle between three adjacent levels and is not correlated with the typical tonal behavior of ΣΔ Modulators. Hence, the sensor performance is sensitive to some specific input patterns even if tonal behavior is decreased by dithering the input of the ADC. Different error sources, such as the mismatch between DAC cells, loop filter linearity error, and quantization error, contribute to the observed noise increments. Our aim is to analyze each of these error sources to understand and quantify in-band noise power increments, and to desensitize the ADC from the undesired input patterns. Some estimation equations are proposed and verified through extensive simulations, by means of deterministic and stochastic methods. These equations are influenced by some modulator parameters and can be used to optimize them in order to reduce such in-band noise power increments.

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Lin, Shengmin, Cheng Lin, and Qunchao Chen. "A Low-power Level-Crossing ADC for Biosignal Acquisition." Journal of Physics: Conference Series 2524, no. 1 (2023): 012022. http://dx.doi.org/10.1088/1742-6596/2524/1/012022.

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Abstract A large number of redundant signals will be generated when the traditional Nyquist sampling method is used to acquire a biological signal, leading to a system’s energy loss. A new level-crossing analog-to-digital converter (LC-ADC) with non-uniform sampling and fixed window structure is presented, with fewer data and low power consumption features. The circuit uses a 6-bit capacitive DAC to quantize the input signal, avoiding the error accumulation of the 1-bit capacitive DAC structure, and a nanoamp CMOS current bias circuit to provide a very low quiescent current for the comparator, further reducing power consumption. The structure was verified in a 0.18μm CMOS technology. The results indicate that the total power dissipation is 0.26uw@500Hz, the signal-to-noise distortion ratio (SNDR) is 59dB@500Hz, and ENOB reached 9.51bit, which is suitable for the acquisition of low-frequency biological signals.

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Lee, Juyong, Younggyun Oh, Sein Oh, and Hyungil Chae. "Low Power CMOS-Based Hall Sensor with Simple Structure Using Double-Sampling Delta-Sigma ADC." Sensors 20, no. 18 (2020): 5285. http://dx.doi.org/10.3390/s20185285.

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A CMOS (Complementary metal-oxide-semiconductor) Hall sensor with low power consumption and simple structure is introduced. The tiny magnetic signal from Hall device could be detected by a high-resolution delta-sigma ADC in presence of offset and flickering noise. Also, the offset as well as the flickering noise are effectively suppressed by the current spinning technique combined with double sampling switches of the ADC. The double sampling scheme of the ADC reduces the operating frequency and helps to reduce the power consumption. The prototype Hall sensor is fabricated in a 0.18-µm CMOS process, and the measurement shows detection range of ±150 mT and sensitivity of 110 µV/mT. The size of active area is 0.7 mm2, and the total power consumption is 4.9 mW. The proposed system is advantageous not only for low power consumption, but also for small sensor size due to its simplicity.

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Zhang, Wence, Jing Xia, and Xu Bao. "Massive MIMO Systems with Low-Resolution ADCs: Achievable Rates and Allocation of Quantization Bits." Wireless Communications and Mobile Computing 2023 (February 17, 2023): 1–12. http://dx.doi.org/10.1155/2023/4012841.

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In massive multiple-input multiple-output (MIMO) systems, the large number of high-resolution analog-to-digital converters (ADCs) lead to high hardware cost and power consumption. In this work, the uplink achievable rates of massive MIMO systems with low-resolution ADCs are studied with consideration of both “Uniform-ADC” that uses ADCs with the same number of quantization bits and “Mixed-ADC” that allows the use of ADCs with different resolutions. By leveraging an additive quantization noise model (AQNM), the asymptotic achievable rates are obtained for maximum ratio combining (MRC), zero-forcing (ZF), and linear minimum mean squared error (LMMSE) receivers in very simple forms. Taking advantages of the theoretical results, we propose two criteria for allocation of quantization bits. It is found that the optimal quantization bits allocation for LMMSE is Mixed-ADCs with number of quantization bits that are polarized, while Uniform-ADC is optimal for MRC and ZF. When there is a constraint on the total ADC power consumption, the proposed quantization-bit allocation scheme for LMMSE becomes Uniform-ADC when the transmit signal-to-noise ratio (SNR) is below a threshold, which is related to the system scale and the ADC power consumption. The theoretical results are verified by Monte-Carlo simulations.

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Lee, Juyong, Seungjun Lee, Kihyun Kim, and Hyungil Chae. "A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier." Electronics 10, no. 16 (2021): 1968. http://dx.doi.org/10.3390/electronics10161968.

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In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design requirements. The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed. The ring amplifier was designed to improve power efficiency and be tolerant to process–voltage–temperature (PVT) variation, and uses a single loop common-mode feedback (CMFB) circuit. By processing residual signals with a single ring amplifier, power efficiency can be maximized, and a low-power system with 30% lower power consumption than that of a conventional PLNS-SAR ADC is implemented. With a high-gain ring amplifier, noise leakage is greatly suppressed, and a structure can be implemented that is tolerant of mismatches between the analog loop and digital correction filters. The measured signal to noise distortion ratio (SNDR) is 70 dB for a 5.15 MHz bandwidth (BW) at a 72 MS/s sampling rate (Fs) with an oversampling ratio (OSR) of 7, and the power consumption is 2.4 mW. The FoMS,SNDR (= SNDR + 10log10BW/Power) is 163.5 dB. The proposed structure in this study can achieve high resolution and wide BW with good power efficiency, without a filter calibration process, through the use of a ring amplifier in the PLNS-SAR ADC.

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Bhargava, Bhanupriya, Pradeep Kumar Sharma, and Shyam Akashe. "High Performance Analysis of CDS Delta-Sigma ADC in 45-Nanometer Regime." International Journal of Nanoscience 13, no. 01 (2014): 1450003. http://dx.doi.org/10.1142/s0219581x14500033.

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In this paper, a correlated double sampling (CDS) technique is proposed in the design of a delta sigma analog-to-digital converter (ADC). These CDS techniques are very effective for the compensation of the nonidealities in switched-capacitor (SC) circuits, such as charge injection, clock feed-through, operational amplifier (op-amp) input-referred offset and finite op-amp gain. An improved compensation scheme is proposed to attain continuous compensation of clock feed-through and offset in SC integrators. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. Also this CDS delta sigma ADC is the most promising circuit for analog to digital converter because this circuit reduces noise due to drift and low frequency noise such as flicker noise and offset voltage and also boosts the gain performance of the amplifier. Further, the simulation results of this circuit are verified on using a "cadence virtuoso tool" using spectre at 45 nm technology with supply voltage 0.7 V.

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Xu, Ming Yuan, Shui Qin Yao, Liang Li, Xing Fa Huang, Xiao Feng Shen, and Xi Chen. "A Low Power Reference Buffer Used in High-Speed High-Precision Pipelined ADC." Applied Mechanics and Materials 667 (October 2014): 379–82. http://dx.doi.org/10.4028/www.scientific.net/amm.667.379.

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An analysis of the output impedance of the reference buffer for pipelined ADC is presented is this paper. To achieve high performance of the reference buffer, damping network has added in. The output impedance of buffer amplifier is made equal to the resistance of the damping network. As a result, the effective impedance is made independent of frequency. Spectre simulation with 14-bit 250MSPS pipelined ADC loads, the results show the settling time can be achieved 1.2 ns with 0.0023% precision, and the noise floor per bin is-114dB with the power consumption is 42.3mW. The reference buffer can meet the requirement of 14-bit up to 800MSPS pipelined ADC.

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Zhang, Guohe, Bo Wang, Feng Liang, and Zhibiao Shao. "A low-kickback-noise and low-voltage latched comparator for high-speed folding and interpolating ADC." IEICE Electronics Express 5, no. 22 (2008): 943–48. http://dx.doi.org/10.1587/elex.5.943.

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Hyun-Yong, Jung, Chu Myonglae, Seo Min-Woong, et al. "Design and analysis on low-power and low-noise single slope ADC for digital pixel sensors." Electronic Imaging 34, no. 7 (2022): 256–1. http://dx.doi.org/10.2352/ei.2022.34.7.iss-256.

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Liu, Maliang, Rui Ma, Shubin Liu, Zhen Ding, Pan Zhang, and Zhangming Zhu. "A 5-GHz Low-Power Low-Noise Integer-N Digital Subsampling PLL With SAR ADC PD." IEEE Transactions on Microwave Theory and Techniques 66, no. 9 (2018): 4078–87. http://dx.doi.org/10.1109/tmtt.2018.2840987.

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Axelsson, S. R. J. "Noise radar for range/doppler processing and digital beamforming using low-bit adc." IEEE Transactions on Geoscience and Remote Sensing 41, no. 12 (2003): 2703–20. http://dx.doi.org/10.1109/tgrs.2003.816665.

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Spivak, A., A. Belenky, and O. Yadid-Pecht. "Very Sensitive Low-Noise Active-Reset CMOS Image Sensor With In-Pixel ADC." IEEE Transactions on Circuits and Systems II: Express Briefs 63, no. 10 (2016): 939–43. http://dx.doi.org/10.1109/tcsii.2016.2539058.

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FOONG, HUEY CHIAN, MENG TONG TAN та YUANJIN ZHENG. "HIGH LINEARITY 8-BIT VCO-BASED CASCADED ΣΔADC FOR DIGITAL DC-DC CONVERTERS". Journal of Circuits, Systems and Computers 21, № 07 (2012): 1250062. http://dx.doi.org/10.1142/s0218126612500624.

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This paper presents the design and implementation of a high resolution voltage-controlled oscillator (VCO)-based ΣΔADC for digital DC-DC converters. The proposed ADC adopts a robust VCO and a sixth-order delta-sigma modulation to attenuate the phase noise and output ripples. The delta-sigma modulation is realized using a cascade of a second-order high-pass filter and a fourth-order band-stop noise shaping filter. Chopper modulation is further employed to reduce the effect of 1/f noise. These have significantly increased the signal-to-noise+distortion ratio (SNDR) and lead to high linearity. The proposed ADC was designed and fabricated using CMOS 0.18 μm process. From measurement, the differential and integral nonlinearities of the ADC are determined to be ±0.5 LSB and ±0.65 LSB, respectively. The SNDR of the ADC is 49 dB up to 500 kHz, which gives an ENOB of 8 bits and quantization step of 2 mV. The ADC also features a low power consumption of 120 μA and a small IC area of 0.18 mm2.

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Sosa, J., Juan A. Montiel-Nelson, R. Pulido, and Jose C. Garcia-Montesdeoca. "Design and Optimization of a Low Power Pressure Sensor for Wireless Biomedical Applications." Journal of Sensors 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/352036.

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A blood pressure sensor suitable for wireless biomedical applications is designed and optimized. State-of-the-art blood pressure sensors based on piezoresistive transducers in a full Wheatstone bridge configuration use low ohmic values because of relatively high sensitivity and low noise approach resulting in high power consumption. In this paper, the piezoresistance values are increased in order to reduce by one order of magnitude the power consumption in comparison with literature approaches. The microelectromechanical system (MEMS) pressure sensor, the mixed signal circuits signal conditioning circuitry, and the successive approximation register (SAR) analog-to-digital converter (ADC) are designed, optimized, and integrated in the same substrate using a commercial 1 μm CMOS technology. As result of the optimization, we obtained a digital sensor with high sensitivity, low noise (0.002 μV/Hz), and low power consumption (358 μW). Finally, the piezoresistance noise does not affect the pressure sensor application since its value is lower than half least significant bit (LSB) of the ADC.

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Baek, Jihyun, Juyong Lee, Jintae Kim, and Hyungil Chae. "2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure." Electronics 11, no. 19 (2022): 3072. http://dx.doi.org/10.3390/electronics11193072.

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This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency.

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Huang, Xiao Yang, Liu Lei Zhou, and Wen Shi Li. "A 1V 2.52-kS/s 367nW Rail-to-Rail 10-Bit Successive Approximation ADC." Advanced Materials Research 718-720 (July 2013): 1717–22. http://dx.doi.org/10.4028/www.scientific.net/amr.718-720.1717.

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A 10-bit successive approximation (SAR) analog-to-digital converter (ADC) in 90nm CMOS dedicated for sample rate limited applications is presented. The SAR ADC achieves an extra low energy by applying only one pre-opamp and without any low voltage techs in preserving the desired low power. HSPICE simulation results show that at a supply voltage of 1V and an output rate of 2.52kS/s, the SAR ADC performs a peak signal-to-noise-and-distortion ratio of 56.8dB. Our SAR ADC consumes 367nW in the simulation, corresponding to a figure of merits of 258.1fJ/conversion-step. And at lowest sample rate mode with an output rate of 126S/s, the ADC consumes only 21nW.

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Yuan, Meng, Mingchao Jian, Jiwei Zheng, and Chunbing Guo. "Behavioral Modeling and Circuit Design of High Precision Low Power Dynamic Zoom ADC." Journal of Physics: Conference Series 2477, no. 1 (2023): 012074. http://dx.doi.org/10.1088/1742-6596/2477/1/012074.

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Abstract In this paper, a high-precision, energy-saving dynamic zoom ADC consisting of a 6-bit SAR ADC and a second-level Σ − ∆ modulator (SDM) is proposed. Non-ideal factors, including slew rate (SR), limited bandwidth and DC gain of the op-amp, and kT/C noise, mismatch of DAC capacitors, are analyzed with a behavioral model in Simulink to guide actual circuit design more accurately. The ADC parameters are adjusted and optimized by model simulation. Because the DAC capacitors mismatch produces harmonic distortion, the DWA technique is used. A new digital combined circuit is proposed to minimize power consumption. To further improve its energy efficiency, a gain enhancement current mirror OTA is designed and the SAR ADC adopts upper plate sampling technique. The layout of zoom ADC occupies 0.856 mm2 in 65 nm techniques. It achieves 109.2 dB SNDR, 17.84 bits ENOB at 1 kHz signal bandwidth and consumes only 0.233 mW.

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Li, Shouping, Jianjun Chen, Bin Liang, and Yang Guo. "Low Power SAR ADC Design with Digital Background Calibration Algorithm." Symmetry 12, no. 11 (2020): 1757. http://dx.doi.org/10.3390/sym12111757.

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This paper proposed a digital background calibration algorithm with positive and negative symmetry error tolerance to remedy the capacitor mismatch for successive approximation register analog-to-digital converters (SAR ADCs). Compensate for the errors caused by capacitor mismatches and improve the ADC performance. Combination with a tri-level switching scheme based on the common-mode voltage Vcm to achieve capacitor reduction and high switching energy efficiency. The proposed calibration algorithm significantly improves capacitor mismatch without resorting to extensive computation or dedicated circuits. The active area is 0.046 mm2 in 40 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The post-simulation results show the effective number of bits (ENOB) improves from 8.23 bits to 11.36 bits, signal-to-noise-and distortion ratio (SNDR) improves from 51.33 dB to 70.15 dB, respectively, before and after calibration. This improves the spurious-free dynamic range (SFDR) by 24.13 dB, from 61.50 dB up to 85.63 dB. The whole ADC’s power consumption is only 0.3564 mW at sampling rate fs =2 MS/s and Nyquist input frequency, with a figure-of-merit (FOM) 67.8 fJ/conv.-step.

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31

Ngoc, Nguyen Dinh, and Kien Truong. "Phase Impairment Estimation for mmWave MIMO Systems with Low Resolutions ADC and Imperfect CSI." EAI Endorsed Transactions on Industrial Networks and Intelligent Systems 9, no. 4 (2022): e3. http://dx.doi.org/10.4108/eetinis.v9i4.2467.

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Multiple-Input Multiple-Output systems operating at millimeter wave band (mmWave MIMO) are a promising technology next generations of mobile networks. In practice, the non-ideal hardware is a challenge for commercially viable mmWave MIMO transceivers and come from non-linearities of the amplifier, phase noise, quantization errors, mutual coupling between antenna ports, and In-phase/Quadrature (I/Q) imbalance. As a result, the received signals are affected by non-ideal transceiver hardware components, thus reduce the performance of such systems, especially phase impairment caused by phase noise and carrier frequency offset (CFO). In this paper, we consider a mmWave MIMO system model that takes into account many practical hardware impairments and imperfect channel state information (CSI). Our main contributions are a problem formulation of phase impairments with imperfect CSI and a low-complexity estimation method to solve the problem. Numerical results are provided to evaluate the performance of the proposed algorithm.

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32

Kim, Kihyun, Sein Oh, and Hyungil Chae. "Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC." Electronics 10, no. 20 (2021): 2545. http://dx.doi.org/10.3390/electronics10202545.

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A 2-then-1-bit/cycle noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC) for high sampling rate and high resolution is presented. The conversion consists of two phases of a coarse 2-bit/cycle SAR conversion for high speed and a fine 1-bit/cycle noise-shaping SAR conversion for high accuracy. The coarse conversion is performed by both voltage and time comparison for low power consumption. A redundancy after the coarse conversion corrects the error caused by a jitter noise during the time comparison. Additionally, a mismatch error between signal and reference paths is eliminated with the help of a tail-current-sharing comparator. The proposed ADC was designed in a 28 nm CMOS process, and the simulation result shows a 68.2 dB signal-to-noise distortion (SNDR) for a sampling rate of 480 MS/s and a bandwidth of 60 MHz with good energy efficiency.

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Khan, Sadeque Reza, and M. S. Bhat. "Low Power Data Acquisition System for Bioimplantable Devices." Advances in Electronics 2014 (December 21, 2014): 1–13. http://dx.doi.org/10.1155/2014/394057.

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Signal acquisition represents the most important block in biomedical devices, because of its responsibilities to retrieve precise data from the biological tissues. In this paper an energy efficient data acquisition unit is presented which includes low power high bandwidth front-end amplifier and a 10-bit fully differential successive approximation ADC. The proposed system is designed with 0.18 µm CMOS technology and the simulation results show that the bioamplifier maintains a wide bandwidth versus low noise trade-off and the proposed SAR-ADC consumes 450 nW power under 1.8 V supply and retain the effective number of bit 9.55 in 100 KS/s sampling rate.

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Et.al, Yarlagadda Archana. "Design of 16-Bit SAR ADC Using DTMOS Technique." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 3046–54. http://dx.doi.org/10.17762/turcomat.v12i3.1339.

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This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The ADC is designed using Cadence virtuoso with CMOS 45nm technology. For SFDR, SNR, ENOB and power consumption, the converter utilizes 63.97dB, 51.06 dB, 15.15 and 528.8uw.

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35

Kakarla Hari Kishore, Yarlagadda Archana,. "Design of 16-Bit SAR ADC Using DTMOS Technique." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (2021): 144–52. http://dx.doi.org/10.17762/turcomat.v12i5.806.

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This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The ADC is designed using Cadence virtuoso with CMOS 45nm technology. For SFDR, SNR, ENOB and power consumption, the converter utilizes 63.97dB, 51.06 dB, 15.15 and 528.8uw.

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36

Zhou, Ye, Wengao Lu, Shanzhe Yu, Dunshan Yu, Yacong Zhang, and Zhongjian Chen. "A Low Power ROIC with Extended Counting ADC Based on Circuit Noise Analysis for Sensor Arrays in IoT System." Journal of Sensors 2022 (October 3, 2022): 1–12. http://dx.doi.org/10.1155/2022/5304613.

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As the Internet of Things (IoT) is rapidly integrated into our daily life, the demand for high performance readout integrated circuit (ROIC) design for sensor arrays is boosting. This paper presents a low power, low noise ROIC with 14-bit column-parallel extended counting (EC) ADCs for sensor arrays targeting the IoT applications. The proposed EC-ADC adopts a pseudodifferential architecture to cancel even-order nonlinearity. The analog front-end is a G m stage, which employs a current-reuse topology to boost the transconductance and reduce noise without increasing current consumption. The upper 9-bit conversion is implemented during integration, and the residual voltage is converted by a 5-bit single-slope (SS) ADC, where the comparator is reused. A ping-pong integrator is proposed to reduce the reset time and improve linearity, eliminating the power-hungry CTIA structure. The ROIC is designed in 0.18 μm 1P5M CMOS process for a 640 × 480 sensor array. Power consumption of the ROIC is 33 mW, and each column ADC consumes 40.1 μW. Simulation results show an input-referred noise of 0.89 LSB (1.74 μVrms), an integral nonlinearity of +0.92/-0.70 LSB, an ENOB of 12.87 bits, and a FoM of 131.1 fJ/step.

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Ma, Cheng, Yang Liu, Yang Li, Quan Zhou, Xinyang Wang, and Yuchun Chang. "A 4-M Pixel High Dynamic Range, Low-Noise CMOS Image Sensor With Low-Power Counting ADC." IEEE Transactions on Electron Devices 64, no. 8 (2017): 3199–205. http://dx.doi.org/10.1109/ted.2017.2702624.

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38

Gao, Bo, Xin Li, Jie Sun, and Jianhui Wu. "Modeling of High-Resolution Data Converter: Two-Step Pipelined-SAR ADC based on ISDM." Electronics 9, no. 1 (2020): 137. http://dx.doi.org/10.3390/electronics9010137.

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The features of high-resolution and high-bandwidth are in an increasing demand considering to the wide range application fields based on high performance data converters. In this paper, a modeling of high-resolution hybrid analog-to-digital converter (ADC) is proposed to meet those requirements, and a 16-bit two-step pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with first-order continuous-time incremental sigma-delta modulator (ISDM) assisted is presented to verify this modeling. The combination of high-bandwidth two-step pipelined-SAR ADC with low noise ISDM and background comparator offset calibration can achieve higher signal-to-noise ratio (SNR) without sacrificing the speed and plenty of hardware. The usage of a sub-ranging scheme consists of a coarse SAR ADC followed by an fine ISDM, can not only provide better suppression of the noise added in 2nd stage during conversion but also alleviate the demands of comparator’s resolution in both stages for a given power budget, compared with a conventional Pipelined-SAR ADC. At 1.2 V/1.8 V supply, 33.3 MS/s and 16 MHz input sinusoidal signal in the 40 nm complementary metal oxide semiconductor (CMOS) process, the post-layout simulation results show that the proposed hybrid ADC achieves a signal-to-noise distortion ratio (SNDR) and a spurious free dynamic range (SFDR) of 86.3 dB and 102.5 dBc respectively with a total power consumption of 19.2 mW.

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39

Buynosov, Alexander Petrovich, Vitaliy Albertovich Vasilyev, Alexey Viktorovich Erpalov, Anton Yuryevich Nitskiy, and Alexander Sergeevich Baitov. "Analysis of electric noise at vibration based diagnostics of motor-coach stock assemblies." Transport of the Urals, no. 2 (2020): 10–15. http://dx.doi.org/10.20291/1815-9400-2020-2-10-15.

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Wide dynamic and frequency ranges, low level of noise allow using piezoelectric accelerometers as general purpose sensors for monitoring and diagnostics of vibration condition of assemblies of prospective motivecoach stock. Electric noise of a vibration parameters measuring channel depends not only on noise from the detecting element, but also on the further processing of a signal, first of all on the operation of an analog-todigital converter (ADC). The paper considers a comparative analysis of electric noise level of the vibration parameters measuring channel for piezoelectric and MEMS-accelerometers with the consideration for the influence of the ADC. As a result, the best ADCs for measuring vibration parameters are 12-digit and 16-digit ones.

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40

Faghani, Maral, Hamidreza Rezaee-Dehsorkh, Nassim Ravanshad, and Hamed Aminzadeh. "Ultra-Low-Power Voice Activity Detection System Using Level-Crossing Sampling." Electronics 12, no. 4 (2023): 795. http://dx.doi.org/10.3390/electronics12040795.

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This paper presents an ultra-low-power voice activity detection (VAD) system to discriminate speech from non-speech parts of audio signals. The proposed VAD system uses level-crossing sampling for voice activity detection. The useless samples in the non-speech parts of the signal are eliminated due to the activity-dependent nature of this sampling scheme. A 40 ms moving window with a 30 ms overlap is exploited as a feature extraction block, within which the output samples of the level-crossing analog-to-digital converter (LC-ADC) are counted as the feature. The only variable used to distinguish speech and non-speech segments in the audio input signal is the number of LC-ADC output samples within a time window. The proposed system achieves an average of 91.02% speech hit rate and 82.64% non-speech hit rate over 12 noise types at −5, 0, 5, and 10 dB signal-to-noise ratios (SNR) over the TIMIT database. The proposed system including LC-ADC, feature extraction, and classification circuits was designed in 0.18 µm CMOS technology. Post-layout simulation results show a power consumption of 394.6 nW with a silicon area of 0.044 mm2, which makes it suitable as an always-on device in an automatic speech recognition system.

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41

SVILAINIS, LINAS, VYTAUTAS DUMBRAVA, and DARIUS KYBARTAS. "EVALUATION OF THE ULTRASONIC PREAMPLIFIER NOISE VOLTAGE DENSITY." Journal of Circuits, Systems and Computers 23, no. 01 (2014): 1450007. http://dx.doi.org/10.1142/s0218126614500078.

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Analysis of the noise voltage density evaluation procedures of the ultrasonic preamplifier is presented. Ultrasonic testing is demanding low noise reception channel. Techniques and equipment for ultrasonic preamplifier's noise performance evaluation are suggested. Equipment used and measurement technologies applied are described. One of the techniques suggested allows estimating the preamplifier noise with only impedance measurement results available. Sine wave correlation technique was used in the impedance measurement procedure. Another technique, not demanding the spectrum analyzer, was suggested, which uses the analog-to-digital converter (ADC) sampling and the Fourier transform to obtain the noise spectral density. Experimental results for the measured complex gain and the equivalent input noise of the preamplifier are presented. Comparison with traditional noise estimation procedure, using the spectrum analyzer is given. Both direct measurement techniques (ADC record Fourier analysis based and spectrum analyzer) indicated good match. Noise whiteness was estimated: in a region of operation frequencies, 5–7 MHz, noise can be considered as white.

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42

Xu, Zule, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa. "A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC." IEEE Journal of Solid-State Circuits 51, no. 10 (2016): 2345–56. http://dx.doi.org/10.1109/jssc.2016.2582854.

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43

Lee, Dongmyung, Kunhee Cho, Dongsoo Kim, and Gunhee Han. "Low-Noise In-Pixel Comparing Active Pixel Sensor Using Column-Level Single-Slope ADC." IEEE Transactions on Electron Devices 55, no. 12 (2008): 3383–88. http://dx.doi.org/10.1109/ted.2008.2006735.

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44

Sanjuán, J., A. Lobo, J. Ramos-Castro, N. Mateos, and M. Díaz-Aguiló. "ADC non-linear error corrections for low-noise temperature measurements in the LISA band." Journal of Physics: Conference Series 228 (May 1, 2010): 012041. http://dx.doi.org/10.1088/1742-6596/228/1/012041.

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45

Luo, Laifu, Zhongtao Shen, Hanlin Yu, Jianyong Zhang, and Shubin Liu. "A Low Noise Readout System for Diamond Microstrip Detectors." Journal of Physics: Conference Series 2374, no. 1 (2022): 012079. http://dx.doi.org/10.1088/1742-6596/2374/1/012079.

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Diamond is widely adopted in physics experiments owing to its good radiation hardness. In this paper, a low noise electronics system based on charge sensitive amplifier (CSA) is designed to read out diamond microstrip detectors. Up to 40 channels are implemented in the system, each containing a CSA, a CR — RC 2 shaper, an analog to digital convertor (ADC) and a discriminator used for trigger generation. After calibration and joint test with prototype detector with a size of 4×4×0.5 mm 3, a noise level of less than 845 electrons is realized in all 40 channels. Furthermore, the result with 90 Sr radiation source is consistent with the theory, and a position resolution of 13 um is obtained in laser test which indicates the readout system meets the demand of the future experiment.

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46

Abd, Hamam, and Andreas König. "Adaptive Spiking Sensor System Based on CMOS Memristors Emulating Long and Short-Term Plasticity of Biological Synapses for Industry 4.0 Applications." tm - Technisches Messen 88, s1 (2021): s114—s119. http://dx.doi.org/10.1515/teme-2021-0057.

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Abstract A conventional analog to digital converter (ADC) faces many issues with leading-edge technologies due to noise, manufacturing deviations, signal swings, etc. Thus, we pursue to design an adaptive spiking neural ADC (SN-ADC) with promising features, e.g., robust to noise, low-power, technology scaling issues, and low-voltage operation. Therefore, our approach promises to be technology agnostic, i.e., effectively translatable to aggressive new technologies. It supports machine learning and self-x (self-calibration, self-healing) that needs for industry 4.0 and the internet of things (IoTs). In this work, we design an adaptive spike-to-rank coding (ASRC), which is the main part of the spiking neural ADC. The ASRC is based on CMOS memristors emulating short-term plasticity (STP) and long-term plasticity (LTP) biological synapses. The proposed ASRC compensates deviations by adapting the weights of the synapses. Also, ASRC is designed using XFAB 0.35 μm CMOS technology and Cadence design tools. In addition, ASRC is simulated to test its performance in the temperature range (−40°C to 85°C).

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47

Zhang, Shuoyan, Qinghe Sun, Xiaolong Chen, Bocheng Wang, and Yifan Li. "ADC Clock Jitter Measurement Based on Simple Coherent Sampling Algorithm." Journal of Physics: Conference Series 2366, no. 1 (2022): 012045. http://dx.doi.org/10.1088/1742-6596/2366/1/012045.

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Abstract In a high-speed sampling system, the clock jitter of analog-to-digital converters (ADCs) will greatly affect its sampling accuracy, leading to the reduction of the signal-to-noise ratio (SNR) of the system output. Therefore, it is necessary to compensate the sampling results to reduce the sampling error caused by clock jitter by measuring the distribution sequence of jitter. In this paper, the influence of clock jitter on the ADC sampling process is analyzed, and an ADC clock jitter measurement scheme based on a simple coherent sampling algorithm is investigated. This scheme can accurately measure the distribution sequence of clock jitter, and has the characteristics of low computational complexity and high precision. The simulation results show that this algorithm can accurately measure the clock jitter sequence with root-mean-square (RMS) greater than 5ps when the amplitude noise of the input signal is greater than 35dB, and the relative error is less than 5%.

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48

Bontems, William, and Daniel Dzahini. "Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm." Chips 2, no. 1 (2023): 31–43. http://dx.doi.org/10.3390/chips2010003.

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This paper presents a design methodology for a low-power, low-chip-area, and high-resolution successive approximations register (SAR) analog-to-digital converter (ADC). The proposed method includes a segmented capacitive DAC (C-DAC) to reduce the power consumption and the total area. An embedded self-calibration algorithm based on a set of trimming capacitors was applied alongside a dynamic element matching (DEM) procedure to control the inherent linearity issues caused by the process mismatch. The SAR ADC and each additional algorithm were modeled in MATLAB to show their efficiency. Finally, a simple methodology was developed to allow for the fast estimation of signal-to-noise ratios (SNRs) without any FFT calculation.

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49

Yin, Y., H. Klar, and P. Wennekers. "A 8X Oversampling Ratio, 14bit, 5-MSamples/s Cascade 3-1 Sigma-delta Modulator." Advances in Radio Science 3 (May 12, 2005): 277–80. http://dx.doi.org/10.5194/ars-3-277-2005.

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Abstract. A 14-b, 5-MHz output-rate cascaded 3-1 sigma-delta analog-to-digital converters (ADC) has been developed for broadband communication applications, and a novel 4th-order noise-shaping is obtained by using the proposed architecture. At a low oversampling ratio (OSR) of 8, the ADC achieves 91.5dB signal-to-quantization ratio (SQNR), in contrast to 71.8dB of traditional 2-1-1 cascaded sigma-delta ADC in 2.5-MHz bandwidth and over 80dB signal-to-noise and distortion (SINAD) even under assumptions of awful circuit non-idealities and opamp non-linearity. The proposed architecture can potentially operates at much more high frequencies with scaled IC technology, to expand the analog-to-digital conversion rate for high-resolution applications.

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Vasudeva, G., and B. V. Uma. "Design and Implementation of High Speed and Low Power 12-bit SAR ADC using 22nm FinFET." WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL 17 (January 3, 2022): 1–15. http://dx.doi.org/10.37394/23203.2022.17.1.

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Successive Approximation Register (SAR) Analog to Digital Converter (ADC) architecture comprises of sub modules such as comparator, Digital to Analog Converter and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements and ADC metrics is presented in this work. Operational Transconductance Amplifier (OTA) based comparator, 12-bit two stage segmented resistive string DAC architecture and low power SAR logic is designed and integrated to form the ADC architecture with maximum sampling rate of 1 GS/s. Circuit schematic is captured in Cadence environment with optimum geometrical parameters and performance metrics of the proposed ADC is evaluated in MATLAB environment. Differential Non Linearity and Integral Non Linearity metrics for the 12-bit ADC is limited to +1.15/-1 LSB and +1.22/-0.69 LSB respectively. ENOB of 10.1663 with SNR of 62.9613 dB is achieved for the designed ADC measured for conversion of input signal of 100 MHz with 20dB noise. ADC with sampling frequency upto 1 GSps is designed in this work with low power dissipation less than 10 mW.

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