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Gotowa bibliografia na temat „LOW NOISE ADC”

Autor: Grafiati

Data publikacji: 11 września 2023

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Artykuły w czasopismach na temat "LOW NOISE ADC"

McCartney, Damien, Adrian Sherry, John O'Dowd i Pat Hickey. "Low-noise low-drift transducer ADC". Computer Standards & Interfaces 21, nr 2 (czerwiec 1999): 102. http://dx.doi.org/10.1016/s0920-5489(99)91937-2.

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McCartney, D., A. Sherry, J. O'Dowd i P. Hickey. "A low-noise low-drift transducer ADC". IEEE Journal of Solid-State Circuits 32, nr 7 (lipiec 1997): 959–67. http://dx.doi.org/10.1109/4.597286.

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Ren, Si Kui, i Zhi Qun Li. "Design of Low Voltage Low Power ADC for WSN Node". Advanced Materials Research 760-762 (wrzesień 2013): 561–66. http://dx.doi.org/10.4028/www.scientific.net/amr.760-762.561.

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This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm2. It results in a figure-of-merit (FOM) of 0.11pJ/step.

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Choi, Gyuri, Hyunwoo Heo, Donggeun You, Hyungseup Kim, Kyeongsik Nam, Mookyoung Yoo, Sangmin Lee i Hyoungho Ko. "A Low-Power, Low-Noise, Resistive-Bridge Microsensor Readout Circuit with Chopper-Stabilized Recycling Folded Cascode Instrumentation Amplifier". Applied Sciences 11, nr 17 (28.08.2021): 7982. http://dx.doi.org/10.3390/app11177982.

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In this paper, a low-power and low-noise readout circuit for resistive-bridge microsensors is presented. The chopper-stabilized, recycling folded cascode current-feedback instrumentation amplifier (IA) is proposed to achieve the low-power, low-noise, and high-input impedance. The chopper-stabilized, recycling folded cascode topology (with a Monticelli-style, class-AB output stage) can enhance the overall noise characteristic, gain, and slew rate. The readout circuit consists of a chopper-stabilized, recycling folded cascode IA, low-pass filter (LPF), ADC driving buffer, and 12-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). The prototype readout circuit is implemented in a standard 0.18 µm CMOS process, with an active area of 12.5 mm2. The measured input-referred noise at 1 Hz is 86.6 nV/√Hz and the noise efficiency factor (NEF) is 4.94, respectively. The total current consumption is 2.23 μA, with a 1.8 V power supply.

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Li, Jiamin, Qian Lv, Jing Yang, Pengcheng Zhu i Xiaohu You. "Spectral and Energy Efficiency of Distributed Massive MIMO with Low-Resolution ADC". Electronics 7, nr 12 (4.12.2018): 391. http://dx.doi.org/10.3390/electronics7120391.

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In this paper, considering a more realistic case where the low-resolution analog-to-digital convertors (ADCs) are employed at receiver antennas, we investigate the spectral and energy efficiency in multi-cell multi-user distributed massive multi-input multi-output (MIMO) systems with two linear receivers. An additive quantization noise model is provided first to study the effects of quantization noise. Using the model provided, the closed-form expressions for the uplink achievable rates with a zero-forcing (ZF) receiver and a maximum ratio combination (MRC) receiver under quantization noise and pilot contamination are derived. Furthermore, the asymptotic achievable rates are also given when the number of quantization bits, the per user transmit power, and the number of antennas per remote antenna unit (RAU) go to infinity, respectively. Numerical results prove that the theoretical analysis is accurate and show that quantization noise degrades the performance in spectral efficiency, but the growth in the number of antennas can compensate for the degradation. Furthermore, low-resolution ADCs with 3 or 4 bits outperform perfect ADCs in energy efficiency. Numerical results imply that it is preferable to use low-resolution ADCs in distributed massive MIMO systems.

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ZHU, ZHANGMING, HONGBING WU, GUANGWEN YU, YANHONG LI, LIANXI LIU i YINTANG YANG. "A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC". Journal of Circuits, Systems and Computers 22, nr 04 (kwiecień 2013): 1350018. http://dx.doi.org/10.1142/s0218126613500187.

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A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

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Lee, Sang-Hun, i Won-Young Lee. "A 10-Bit 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparator for Input-Referred Noise Reduction". Sensors 22, nr 16 (14.08.2022): 6078. http://dx.doi.org/10.3390/s22166078.

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This paper presents a low noise 0.6-V 400-kS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for input-referred noise reduction. A dual-domain comparator is proposed to optimize the power, noise, and sampling rate of the ADC in the 10-bit conversion. In order to optimize the figure of merits (FoM) of the ADC, the 10-bit conversion consists of a 7-bit coarse conversion with the double-tail dynamic comparator and a 3-bit fine conversion with the VCDL-based time-domain comparator. An asynchronous timing controller is also proposed to improve the ADC sampling rate and optimize the power consumption of the dual-domain comparator. The proposed SAR ADC is fabricated in 180-nm CMOS technology with an area of 0.836 mm2. At a 0.6-V supply voltage and a 400-kS/s sampling rate, the implemented SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 56.59 dB and an effective number of bits (ENOB) of 9.16 bits. The peak values of DNL and INL are +0.47/−0.53 LSB and +0.92/−0.64 LSB, respectively. The FoM is 10.31 fJ/conversion step with a power consumption of 2.36 μW.

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Xu, Daiguo, Kaikai Xu, Shiliu Xu, Lu Liu i Tao Liu. "A System-Level Correction SAR ADC with Noise-Tolerant Technique". Journal of Circuits, Systems and Computers 27, nr 13 (3.08.2018): 1850202. http://dx.doi.org/10.1142/s021812661850202x.

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A system-level correction successive approximation register analog-to-digital converter (SAR ADC) with regulated comparator of noise-tolerant technique is proposed. First, a substrate voltage boost technique is provided to improve the linearity and speed of sampling switch. Secondly, the proposed SAR ADC provides a comparator of noise regulation without redundant comparison cycle. The proposed comparator would be regulated in high-speed large noise state in large input differential signals. In the condition of small input differential signals, the comparator would be adjusted to low-speed small noise state. Furthermore, a high-speed low-power technique is proposed to optimize the performance of dynamic comparator. Additionally, a fast SAR logic structure is provided to increase the conversion speed of SAR ADC. To demonstrate the proposed techniques, a design example of SAR ADC is fabricated in 65[Formula: see text]nm CMOS technology. The SAR ADC is able to tolerate about 1.1 LSB noise errors in post-simulation with the operation state regulated automatically. The core occupies an active area of only 0.025[Formula: see text]mm2 and consumes 1.5[Formula: see text]mW. Measurement results achieve SFDR [Formula: see text][Formula: see text]dB and SNDR [Formula: see text][Formula: see text]dB, resulting in the FOM of 21.6[Formula: see text]fJ per conversion step.

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Ding, Wei, Heng Liu i Tao Wu. "Optimizing for High Resolution ADC Model With Combined Architecture". International Journal of Cognitive Informatics and Natural Intelligence 14, nr 3 (lipiec 2020): 118–32. http://dx.doi.org/10.4018/ijcini.2020070106.

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High resolution analog-digital conversion (ADC) is a key instrument to convert analog signals to digital signals, which is deployed in data acquisition system to match high resolution analog signals from seismometers systems. To achieve high resolution, architecture of Σ-△ oversampling or pipeline ADC architecture have following disadvantages: high power consumption, low linearity of modulators, and complex structure. This work presents a novel model architecture, which design principle is validated by mathematical formulations which combined advantages of both pipeline and Σ-△oversampling ADC architecture. By discussing the adverse effects of the whole ADC architecture with an external noise theoretically, an amended theoretical model is proposed according to the assessment result of a noise simulation algorithm. The simulation results represent that the whole performance of combined architecture is determined by the noise level of integrator and subtractor. Using these two components with a noise index no more than 10-7 V/√Hz, the resolution of the prototype can achieve a reservation of 144.5 dB.

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Sheng, Shuran, Peng Chen, Yuxuan Yao, Lenan Wu i Zhimin Chen. "Atomic Network-Based DOA Estimation Using Low-Bit ADC". Electronics 10, nr 6 (20.03.2021): 738. http://dx.doi.org/10.3390/electronics10060738.

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In the direction of arrival (DOA) estimation problem, when a low-bit analog to digital converter (ADC) is used, the estimation performance severely deteriorates. In this paper, the DOA estimation problem is considered in a low-cost direction finding system with low-bit ADC. To eliminate quantization noise, we propose a novel network ADCnet, which is a composition of fully connected layers and exponential linear unit (ELU) layers, and the input signals are the received signals using low-bit ADC. After the ADCnet, an AtomicNet is also proposed to estimate the DOA from the denoised signals, where atomic vectors are corresponding to the steer vectors. A loss function considering both the reconstruction performance and the sparsity is proposed in the AtomicNet. Different from the exiting atomic norm-based methods, the proposed method can avoid an optimization problem and estimate the DOA with lower computational complexity. Simulation results show that the proposed method outperforms the existing methods in the DOA estimation performance using low-bit ADC.

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Rozprawy doktorskie na temat "LOW NOISE ADC"

Carr, Richard D. "Analog preprocessing in a SNS 2 [mu] low-noise CMOS folding ADC". Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1994. http://handle.dtic.mil/100.2/ADA293356.

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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, December 1994.
"December 1994." Thesis advisor(s): Phillip E. Pace, Douglas J. Fouts. Bibliography: p. 103. Also available online.

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Schafer, Jeffrey L. "Decimation of encoding errors in an optimum SNS 2 [mu] low-noise CMOS ADC". Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1995. http://handle.dtic.mil/100.2/ADA293208.

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Tallhage, Jonas. "Construction of a Low-Noise Amplifier Chain With Programmable Gain and Offset". Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106143.

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A low-noise, variable gain amplier chain was constructed for interfa-cing a sensor to an ADC. During the course of the work two dierent methods -switched-capacitor circuits and chopping circuits - for dealing with 1/f noise wereinvestigated during the course of the work. The resulting circuit did not quitemeet the performance required by the specication, some possible improvementsare suggested.

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Jacmenovic, Dennis, i dennis_jacman@yahoo com au. "Optimisation of Active Microstrip Patch Antennas". RMIT University. Electrical and Computer Engineering, 2004. http://adt.lib.rmit.edu.au/adt/public/adt-VIT20060307.144507.

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This thesis presents a study of impedance optimisation of active microstrip patch antennas to multiple frequency points. A single layered aperture coupled microstrip patch antenna has been optimised to match the source reflection coefficient of a transistor in designing an active antenna. The active aperture coupled microstrip patch antenna was optimised to satisfy Global Positioning System (GPS) frequency specifications. A rudimentary aperture coupled microstrip patch antenna consists of a rectangular antenna element etched on the top surface of two dielectric substrates. The substrates are separated by a ground plane and a microstrip feed is etched on the bottom surface. A rectangular aperture in the ground plane provides coupling between the feed and the antenna element. This type of antenna, which conveniently isolates any circuit at the feed from the antenna element, is suitable for integrated circuit design and is simple to fabricate. An active antenna design directly couples an antenna to an active device, therefore saving real estate and power. This thesis focuses on designing an aperture coupled patch antenna directly coupled to a low noise amplifier as part of the front end of a GPS receiver. In this work an in-house software package, dubbed ACP by its creator Dr Rod Waterhouse, for calculating aperture coupled microstrip patch antenna performance parameters was linked to HP-EEsof, a microwave computer aided design and simulation package by Hewlett-Packard. An ANSI C module in HP-EEsof was written to bind the two packages. This process affords the client the benefit of powerful analysis tools offered in HP-EEsof and the fast analysis of ACP for seamless system design. Moreover, the optimisation algorithms in HP-EEsof were employed to investigate which algorithms are best suited for optimising patch antennas. The active antenna design presented in this study evades an input matching network, which is accomplished by designing the antenna to represent the desired source termination of a transistor. It has been demonstrated that a dual-band microstrip patch antenna can be successfully designed to match the source reflection coefficient, avoiding the need to insert a matching network. Maximum power transfer in electrical circuits is accomplished by matching the impedance between entities, which is generally acheived with the use of a matching network. Passive matching networks employed in amplifier design generally consist of discrete components up to the low GHz frequency range or distributed elements at greater frequencies. The source termination for a low noise amplifier will greatly influence its noise, gain and linearity which is controlled by designing a suitable input matching network. Ten diverse search methods offered in HP-EEsof were used to optimise an active aperture coupled microstrip patch antenna. This study has shown that the algorithms based on the randomised search techniques and the Genetic algorithm provide the most robust performance. The optimisation results were used to design an active dual-band antenna.

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Chiang, Wen-Nan, i 江文男. "Low Noise Dual Channel Pipelined ADC". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/d68jd9.

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碩士
國立臺北科技大學
電資碩士班
97
Due to the portable computer, communication, and consuming electronic grew up extensively. In the application of the display and wireless communication ,as to the low power, and high speed, that the interface circuit of analog to digit converter has indispensable demands. The pipelined analog to digital converter is a better choice at present which has high speed conversion ratio and high resolution for the analog to digital converter. The main structure used the 9 stages pipelined ADC. In this thesis the 10 bits pipelined ADC is composed of the first 8 stages which each stage 1.5 bit and the last stage that has 2 bit. In order to get low power, high speed, and high resolution , each stage used the dual channel 1.5bit Flash ADC. Because of the 1.5bit flash ADC have high-speed operation advantage and the dual channel structure can decrease the power consumption and reduce the noise when it work in positive and negative duty cycle respectively. We descript the basic principle of pipelined analog to digital converter and realize from designing to the circuit. We adopt the TSMC 0.18 μm CMOS technology to simulation the circuit of system and implement it. the core area is about 0.6 1.47 mm2, and the power consumption is about 21.6mW. If the bandwidth of the input signal is 44.1 kHz sine wave, we obtain the 41.5 dB peak signal to noise and distortion ratio, and simulation results ENOB=6.6 bits.

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DWIVEDI, MAHEEP. "DESIGN OF ULTRA LOW VOLTAGE LOW NOISE ANALOG FRONT END FOR BIO-POTENTIAL SIGNALS". Thesis, 2016. http://dspace.dtu.ac.in:8080/jspui/handle/repository/14946.

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The information extracted from the bio-potential signals such as ECG, EEG, ECoG, ERG and ENG is extensively used for health care and medical treatment purposes. The use of bio-potential acquisition systems is not only limited to the hospitals but also extended to the homes for ubiquitous health care. Therefor the demand of portable bio-signal measurement system is increasing. The key constituent to this kind of systems is the analog front-end (AFE). The analog readout front-end extracts the bio-signals directly from human body through electrodes and defines the extracted signal quality. The most critical block in an bio-potential acquisition system is the AFE as it is connected directly to the human body and the output this should be ready to feed the subsequent stages that are ADCs and DSPs. This block must operate under low power consumption with minimal added noise to ensure the better signal quality with enhanced battery life, when incorporated in portable bio-signal acquisition systems. In this dissertation a novel multi-function Analog Front-End is proposed. This analog readout front end is oriented to be employed in flexible and portable bio-potential signal acquisition systems. The essential contribution of this work is the new Forward Body Biased Current Mode Amplifier (FBBCMA) based on convention forward body biased technique for low-voltage operation. The proposed FBBCMA achieves very low noise performance because of inherent properties of current mode topology. Forward body biasing of MOS devices further reduces the flicker noise that is a critical concern in circuits operating at low frequencies. Low power consumption and other advantages are achieved by the aid of the forward body biasing and current mode topology. A complete analog readout front end is implemented and simulated using the standard TSMC 180nm parameters and P-Spice as simulator. This AFE consist of a pre amplifier followed by a band pass filter to enhance in band signals and reject the signals that are laying out of the band of interest. Tuneable bandwidth of AFE enables it to serve as the first stage in variety of bio-signal acquisition systems. The simulation results show that the designed circuits meet the basic requirements of the low power consumption under low noise operation for long time portable bio-potential recorders.

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Hu, Chih-Wei, i 胡志維. "The Design of on Oversampling ADC with Low Clock Feedthrough Noise and OP-Amp Gain-Compensation". Thesis, 1996. http://ndltd.ncl.edu.tw/handle/83813807608719011816.

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碩士
淡江大學
電機工程學系
84
The new design of a switched-capacitor(SC) delta-sigma modulator(DSM) is proposed. Generally speaking, the performance of a DSM is degraded due to theop-amp gain and clock feedthrough noise, and the right or error of chargetrnsfering between capcitors. The SC integrator is the main architecture ofa DSM, therefor, the performance of the SC integrator decides the performanceof DSM. The finite op-amp gain causes the inverting input of the op-amp notto the virture ground. If the op-amp gain is high enough that makes the voltageof inverting inputs of the op-amp approach zero, the performance of the DSM orSC integrator will be good. However, the op-amp with high gain, about 90dB, isvery difficult to design, so the performace of the DSM is poor if the op-ampwith low gain is used. Clock feedthrough noise and charge transfering areanother important nonideal properties for DSM and SC integrator.The chargetransfer depends on switches in DSM and switchs are controled by the clock.Sometime the clock feedthrough noise is caused by the clock signal is mixedwith the input signal and makes the output performance be reduced and DSM evencause error. The charge is stored in capacitors in a DSM and transfers chargeto another capacitors in the next phase, in case that is in error then it willmake the output performance degrade and even cause error.In this thesis, a new design of DSM is proposed to overcome the three nonideal properties as mentioned. We design a DSM by using a finite gain(about 60dB) and it achieves the same performance as a 100dB-gain op-amp does. Thisalso reduces the clock feedthrough noise and makes charge transfering betweencapacitors more exactly.

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Tu, Jian-Yu, i 凃建宇. "A Design of Low-Power Analog Front End with Programmable-Gain Low-Noise Amplifier and Successive-Approximation ADC for Biomedical Applications". Thesis, 2016. http://ndltd.ncl.edu.tw/handle/39479211172772254038.

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碩士
國立中央大學
電機工程學系
104
Recent years, long-term care or digital personal healthcare secretary is necessary. By improving the multi-purpose of biomedical instruments, reliability and reducing power consumption, equipment size and cost are conducive to today's society. Therefore, this thesis will present a biomedical circuit design and describe how to achieve simplification, miniaturization, low power consumption, multi-purpose and high reliability. Finally hope this research will make everyone be better. This thesis consists of two parts, the first part introduces our research about biomedical analog front-end low-noise amplifier (LNA), which has operational bandwidth of 5 KHz, covering the EEG, ECG and other bio-signals. The CCIA architecture is used to block DC offset from electrode, taking the high impedance of Pseudo-Resistor to achieve miniaturization and extremely low frequency pole. Moreover, the current-reusing technique is used to maintain low power consumption and keep flicker noise and thermal noise to lower level. Behind the main block LNA, a programmable gain amplifier (PGA) is used. Hence not just only one bio-signal can be measured, but a variety of bio-signals measured can be applied. In the second part, the successive approximation analog-to-digital converter (SAR ADC) is introduced which can meet the low-power consumption requirement. The function of SAR ADCs is converting the LNA analog signal to digital signal. The main idea of SAR ADCs is Monotonic Capacitor Switching Procedure which can effectively reduce energy loss to 19% of conventional architecture. On the other hand, by using monotonic switching procedure which can directly compare MSB, the overall capacitance array occupies only half of the conventional architecture, which can greatly reduce the chip area. The bootstrapped-switch is used to make input signal and sampling switch independent. The Ron of sampling switch will be fixed and make the S/H achieving high linearity. The main part of SAR ADCs is comparator. In this research the dynamic comparator is better for our research. Because the dynamic comparator only works in the conversion phase, by doing so the static power consumption can be saved. Our design achieves a 10-bit SAR ADC, the primary consideration of SAR ADCs design is low power requirement. These circuits are designed in TSMC 0.18 μm CMOS 1P6M process. The first circuit is LNA, when input signal frequency is 250 Hz and 1 kHz, 500 μV input amplitude, the mid-band gain of analog front-end low-noise amplifier can be programmed from 35.917 dB to 53.979 dB. The post layout simulation shows that the input-referred noise is 1.811 μV rms, the Noise efﬁciency factor (NEF) is 1.39, the chip area (including ESD PAD) is 1.322 mm2, the overall chip consumes 2.19 μW. The second circuit is the SAR. When input signal frequency is 250 Hz and input amplitude 250mV, ENOB is 9.638 bits, SNDR is 60.1969 dB, the overall merit FOM is 0.55 pJ per conversion-step, the chip area (including ESD PAD) is 1.33 mm2, the overall chip consumes 2.602 μW.

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Li, Guan-Shun, i 李冠舜. "A Low-Power Continuous-Time Delta-Sigma ADC with Low Noise Low Voltage Supply Bandgap Reference Voltage and RC Time-Constant Calibration Technique for Biomedical Systems". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/05293175008455705690.

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碩士
國立中央大學
電機工程學系
105
With the increment of average age of people, various bio-medical wearable devices have been launched, especially for the elders. Therefore, how to reduce the power consumption and area to achieve the portability as well as the long battery life-time requirements are demands of this thesis. This thesis consists of three parts, the first part designs a continuous-time delta-sigma modulator (CTDSM) for bio-medical application to ease the requirements of hardware rather than discrete-time DSM using an OPA to achieve the second-order integration. Besides, the current-reusing technique is used to maintain flicker noise and thermal noise to lower level and to keep low power consumption. In the second part, a bandgap voltage reference (BGR) is introduced to meet low-noise and low supply voltage requirements. It can provide a stale voltage reference without the variation of temperature for feedback reference of DSM and other sub-circuits. Third, the drawback of a CTDSM is the dependence on the variation of environment temperature and process. Therefore, the RC Time-Constant Calibration method is proposed for detecting and compensating the variation of RC time-constant. Finally, by introducing a decimation, we integrate all sub-circuits to a complete continuous-time delta-sigma ADC. Designs in this thesis are fabricated in the UMC 0.18 μm 1P6M CMOS process. In order to pursue low-power consumption, the supply voltage is all set up as low as 1.2 V. First, the measurement of CTDSM achieves 78.42 dB SNDR, 12.73 bits ENOB, and power consumption 15.97 μW at 10 kHz signal bandwidth with X128 OSR, 0.6 Vp-p amplitude and chip area is 0.67mm*0.56mm, including PAD and seal-ring. Second, BGR generates a stable 0.6 V voltage reference which is tunable with flicker and thermal noise 0.496nV^2/(0.1~10 kHz) in the bandwidth for 17.3 μW. Finally, the simulation of the complete CT delta-sigma ADC achieves 81.31 dB SNDR, 13.21 bits ENOB, and power consumption 71.82 μW, including CTDSM, BGR, RC Time-Constant Calibration and buffers. The whole chip area is 1.74mm*1.11mm, including PAD and seal-ring.

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Qian, Chengliang. "Low-Power Low-Noise CMOS Analog and Mixed-Signal Design towards Epileptic Seizure Detection". Thesis, 2013. http://hdl.handle.net/1969.1/149508.

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About 50 million people worldwide suffer from epilepsy and one third of them have seizures that are refractory to medication. In the past few decades, deep brain stimulation (DBS) has been explored by researchers and physicians as a promising way to control and treat epileptic seizures. To make the DBS therapy more efficient and effective, the feedback loop for titrating therapy is required. It means the implantable DBS devices should be smart enough to sense the brain signals and then adjust the stimulation parameters adaptively. This research proposes a signal-sensing channel configurable to various neural applications, which is a vital part for a future closed-loop epileptic seizure stimulation system. This doctoral study has two main contributions, 1) a micropower low-noise neural front-end circuit, and 2) a low-power configurable neural recording system for both neural action-potential (AP) and fast-ripple (FR) signals. The neural front end consists of a preamplifier followed by a bandpass filter (BPF). This design focuses on improving the noise-power efficiency of the preamplifier and the power/pole merit of the BPF at ultra-low power consumption. In measurement, the preamplifier exhibits 39.6-dB DC gain, 0.8 Hz to 5.2 kHz of bandwidth (BW), 5.86-μVrms input-referred noise in AP mode, while showing 39.4-dB DC gain, 0.36 Hz to 1.3 kHz of BW, 3.07-μVrms noise in FR mode. The preamplifier achieves noise efficiency factor (NEF) of 2.93 and 3.09 for AP and FR modes, respectively. The preamplifier power consumption is 2.4 μW from 2.8 V for both modes. The 6th-order follow-the-leader feedback elliptic BPF passes FR signals and provides -110 dB/decade attenuation to out-of-band interferers. It consumes 2.1 μW from 2.8 V (or 0.35 μW/pole) and is one of the most power-efficient high-order active filters reported to date. The complete front-end circuit achieves a mid-band gain of 38.5 dB, a BW from 250 to 486 Hz, and a total input-referred noise of 2.48 μVrms while consuming 4.5 μW from the 2.8 V power supply. The front-end NEF achieved is 7.6. The power efficiency of the complete front-end is 0.75 μW/pole. The chip is implemented in a standard 0.6-μm CMOS process with a die area of 0.45 mm^2. The neural recording system incorporates the front-end circuit and a sigma-delta analog-to-digital converter (ADC). The ADC has scalable BW and power consumption for digitizing both AP and FR signals captured by the front end. Various design techniques are applied to the improvement of power and area efficiency for the ADC. At 77-dB dynamic range (DR), the ADC has a peak SNR and SNDR of 75.9 dB and 67 dB, respectively, while consuming 2.75-mW power in AP mode. It achieves 78-dB DR, 76.2-dB peak SNR, 73.2-dB peak SNDR, and 588-μW power consumption in FR mode. Both analog and digital power supply voltages are 2.8 V. The chip is fabricated in a standard 0.6-μm CMOS process. The die size is 11.25 mm^2. The proposed circuits can be extended to a multi-channel system, with the ADC shared by all channels, as the sensing part of a future closed-loop DBS system for the treatment of intractable epilepsy.

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Książki na temat "LOW NOISE ADC"

Bertell, Maths, Frog i Kendra Willson, red. Contacts and Networks in the Baltic Sea Region. NL Amsterdam: Amsterdam University Press, 2019. http://dx.doi.org/10.5117/9789462982635.

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Since prehistoric times, the Baltic Sea has functioned as a northern mare nostrum — a crucial nexus that has shaped the languages, folklore, religions, literature, technology, and identities of the Germanic, Finnic, Sámi, Baltic, and Slavic peoples. This anthology explores the networks among those peoples. The contributions to Contacts and Networks in the Baltic Sea Region: Austmarr as a Northern mare nostrum, ca. 500-1500 ad address different aspects of cultural contacts around and across the Baltic from the perspectives of history, archaeology, linguistics, literary studies, religious studies, and folklore. The introduction offers a general overview of crosscultural contacts in the Baltic Sea region as a framework for contextualizing the volume’s twelve chapters, organized in four sections. The first section concerns geographical conceptions as revealed in Old Norse and in classical texts through place names, terms of direction, and geographical descriptions. The second section discusses the movement of cultural goods and persons in connection with elite mobility, the slave trade, and rune-carving practice. The third section turns to the history of language contacts and influences, using examples of Finnic names in runic inscriptions and Low German loanwords in Finnish. The final section analyzes intercultural connections related to mythology and religion spanning Baltic, Finnic, Germanic, and Sámi cultures. Together these diverse articles present a dynamic picture of this distinctive part of the world.

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Zhou, Clarence. Two/Four/Eight-Channel, 153. 6 Ksps, Low Noise, 16-Bit Delta-Sigma ADC. Microchip Technology Incorporated, 2020.

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Boles, Melanie. MCP3461/2/4 - Two/Four/Eight-Channel, 153. 6 Ksps, Low Noise, 16-Bit Delta-Sigma ADC. Microchip Technology Incorporated, 2020.

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Zhou, Clarence. Two/Four/Eight-Channel, 153. 6 Ksps, Low Noise 24-Bit Delta-Sigma ADCs. Microchip Technology Incorporated, 2020.

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Boles, Melanie. MCP3561/2/4 - Two/Four/Eight-Channel, 153. 6 Ksps, Low Noise 24-Bit Delta Sigma ADCs. Microchip Technology Incorporated, 2020.

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Kennelly, Spencer. MD3872 Low-Power, Low-Noise 8-Channel 50 MHz Ultrasound Front-End Receiver with LNA, VGA, AAF, CPS and 12-Bit ADCs. Microchip Technology Incorporated, 2015.

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Pierce, Linda. MCP3561/2/4 - Two/Four/Eight-Channel, 153. 6 KSPS, Low-Noise 24-Bit Delta-Sigma ADCs Data Sheet. Microchip Technology Incorporated, 2019.

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Nuccio, Aimee. MCP3461/2/4R - Two/Four/Eight-Channel, 153. 6 Ksps, Low-Noise, 16-Bit Delta-Sigma ADCs with Internal Voltage Reference, Rev. B. Microchip Technology Incorporated, 2020.

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Części książek na temat "LOW NOISE ADC"

Xhakoni, Adi, i Georges Gielen. "Low-Noise Detectors through Incremental Sigma–Delta ADCs". W Analog Electronics for Radiation Detection, 71–90. Boca Raton : Taylor & Francis, CRC Press, 2016. | Series: Devices, circuits, and systems ; 59: CRC Press, 2017. http://dx.doi.org/10.1201/b20096-4.

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Hoover, Guy. "Driving a low noise, low distortion 18-bit, 1.6Msps ADC". W Analog Circuit Design, 713–14. Elsevier, 2015. http://dx.doi.org/10.1016/b978-0-12-800001-4.00331-8.

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Hoover, Guy. "Driving lessons for a low noise, low distortion, 16-bit, 1Msps SAR ADC". W Analog Circuit Design, 715–16. Elsevier, 2015. http://dx.doi.org/10.1016/b978-0-12-800001-4.00332-x.

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Yip, Ching Wen. "The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA". W Advances in Monolithic Microwave Integrated Circuits for Wireless Systems, 157–84. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-60566-886-4.ch007.

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LNA is an electronic amplifier that is required in receiver systems to increase the amplitude of the very low level signals from the antenna without adding too much noise. Software Advance Design System (ADS) was used to simulate the circuit and design the layout. LNA was designed using cascode topology with feedback techniques which produces better matching and unconditionally stable over the entire desired frequencies. For the 2.4 GHz operation, the amplifier achieves gain of 14.949 dB, noise figure of 1.951 dB and input reflection coefficient of -10.419 dB. With operating voltage supply at 3V, the total current consumption is 13 mA. For 3.5GHz amplifier, gain is 22.985 dB, noise figure is 1.964dB, input reflection coefficient is -12.427 dB and current consumption is 18 mA.

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Fakhfakh, M., M. Boughariou, A. Sallem i M. Loulou. "Design of Low Noise Amplifiers through Flow-Graphs and their Optimization by the Simulated Annealing Technique". W Advances in Monolithic Microwave Integrated Circuits for Wireless Systems, 69–88. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-60566-886-4.ch004.

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This chapter presents the optimal design of Low Noise Amplifiers (LNAs). The basic idea consists of optimizing performances of LNAs by a direct action on the scattering parameters. A symbolic approach, namely the Coates Flow-Graph technique, is used to automatically generate symbolic expressions of the impedance parameters and, thus, those of the scattering parameters. The Simulated Annealing optimization technique is applied to determine the optimal sizing of the LNA. ADS simulation results are given to show the viability of the proposed approach.

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Pei, Cheng-Wei. "Low distortion, low noise differential amplifier drives high speed ADCs in demanding communications transceivers". W Analog Circuit Design, 1079–80. Elsevier, 2015. http://dx.doi.org/10.1016/b978-0-12-800001-4.00501-9.

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"A 0.4 ps-RMS-Jitter 1–3 GHz Clock Multiplier PLL Using Phase-Noise Preamplification". W Low-Power High-Speed ADCs for Nanometer CMOS Integration, 69–87. Dordrecht: Springer Netherlands, 2008. http://dx.doi.org/10.1007/978-1-4020-8450-8_4.

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Ng, Wan Yeen, i Xhiang Rhung Ng. "The Design and Modeling of 30 GHz Microwave Front-End". W Advances in Monolithic Microwave Integrated Circuits for Wireless Systems, 205–38. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-60566-886-4.ch009.

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This chapter aims to discuss a millimeter wave integrated circuit (MMWIC) in frequency of 30 GHz especially switch (SPDT), medium power amplifier (MPA) and low noise amplifier (LNA). The switch is developed using a commercial 0.15 µm GaAs pHEMT technology. It achieves low loss and high isolation for millimeter wave applications. The circuit and layout drawing of SPDT switch are done by using Advanced Design System (ADS) software. The layout is verified by running the Design Rules Check (DRC) to check and clear all the errors. At the operating frequency of 30 GHz, the reported SPDT switch has 1.470 dB insertion loss and 37.455 dB of isolation. It also demonstrates 26.00 dBm of input P1dB gain compression point (P1dB) and 22.975 dBm of output P1dB. At a supply voltage of 3.0 V and 30 GHz operating frequency, this two-stage LNA achieves an associated gain of 21.628 dB, noise figure (NF) of 2.509 dB and output referred 1-dB compression point (P1dB) of -11.0 dBm, the total power consumptions for the LNA is 174 mW. At a supply voltage of 6.0 V and 30 GHz operating frequency, a 2-stage MPA achieves a linear gain (S21) of 13.236 dB, P1dB of 22.5 dBm, power gain of 11.055 dB and the PAE of 14.606%. The total power consumption for the MPA is 1.122 W. The 30 GHz LNA and PA can be applied in direct broadcast satellite (DBS), automotive radar transmitter and receiver.

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Wang, Xin-Jing, Mo Yu, Lei Zhang i Wei-Ying Ma. "Argo". W Advances in Multimedia and Interactive Technologies, 67–83. IGI Global, 2011. http://dx.doi.org/10.4018/978-1-60960-189-8.ch005.

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In this chapter, we introduce the Argo system which provides intelligent advertising made possible from user generated photos. Based on the intuition that user-generated photos imply user interests which are the key for profitable targeted ads, Argo attempts to learn a user’s profile from his shared photos and suggests relevant ads accordingly. To learn a user interest, in an offline step, a hierarchical and efficient topic space is constructed based on the ODP ontology, which is used later on for bridging the vocabulary gap between ads and photos as well as reducing the effect of noisy photo tags. In the online stage, the process of Argo contains three steps: 1) understanding the content and semantics of a user’s photos and auto-tagging each photo to supplement user-submitted tags (such tags may not be available); 2) learning the user interest given a set of photos based on the learnt hierarchical topic space; and 3) representing ads in the topic space and matching their topic distributions with the target user interest; the top ranked ads are output as the suggested ads. Two key challenges are tackled during the process: 1) the semantic gap between the low-level image visual features and the high-level user semantics; and 2) the vocabulary impedance between photos and ads. We conducted a series of experiments based on real Flickr users and Amazon.com products (as candidate ads), which show the effectiveness of the proposed approach.

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Kumar, B. Satheesh, i K. Sampath Kumar. "Smart Healthcare Application Implementation of AI and Blockchain Technology". W Advances in Electronic Government, Digital Divide, and Regional Development, 199–216. IGI Global, 2023. http://dx.doi.org/10.4018/978-1-6684-7697-0.ch013.

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Patients can control, share, and manage their health records with family, friends, and healthcare professionals utilizing electronic health records (EHRs), which use an open channel, or the Internet. When a lot of data is available, DL methods show promise in these health applications. A distributed blockchain-based IoT system would benefit greatly from these ideas. This research proposes novel technique in Healthcare Data Based Feature Selection and Classification Using Blockchain and Machine Learning Architectures. The network has been secured using centralized blockchain sensor network. Here the input sensor-based healthcare data has been collected and processed for noise removal and smoothening. Then the processed data feature has been selected using Greedy Mixed Forward Colony Optimization feature selection. The suggested framework's superiority is supported by security research and experimental findings using the IoT-Botnet and ToN-IoT datasets. Proposed technique attained acc of 95%, precision of 85%, recall of 76%, F1 score of 63%, sec rate of 95%, DT Rate of 85%.

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Streszczenia konferencji na temat "LOW NOISE ADC"

Huang, Ziqi, Weilin Xu, Baolin Wei, Xueming Wei i Haiou Li. "A Low Power Active-Passive Noise Shaping SAR ADC". W 2023 IEEE 3rd International Conference on Electronic Technology, Communication and Information (ICETCI). IEEE, 2023. http://dx.doi.org/10.1109/icetci57876.2023.10176463.

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Ko-Chi Kuo i Chi-Wei Wu. "Capacitive dynamic comparator with low kickback noise for pipeline ADC". W 2013 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2013. http://dx.doi.org/10.1109/edssc.2013.6628111.

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Mandridis, Dimitrios, Charles Williams, Ibrahim Ozdur i Peter J. Delfyett. "Low Noise Stabilized Chirped Pulse Theta Laser for Photonic ADC". W CLEO: Science and Innovations. Washington, D.C.: OSA, 2011. http://dx.doi.org/10.1364/cleo_si.2011.cthi3.

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Hu, Hang, Vladimir Vesely i Un-Ku Moon. "Ultra-Low OSR Calibration Free MASH Noise Shaping SAR ADC". W 2022 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2022. http://dx.doi.org/10.1109/iscas48785.2022.9937876.

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Duong, Duc V., i Thang V. Nguyen. "A capacitive dynamic comparator with low kickback noise for pipelined ADC". W 2013 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT). IEEE, 2013. http://dx.doi.org/10.1109/conecct.2013.6469281.

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Seo, Min-Woong, Taishi Takasawa, Shoji Kawahito, Takehide Sawamoto, Tomoyuki Akahori i Zheng Liu. "A low noise wide dynamic range CMOS image sensor with low-noise transistors and 17b column-parallel ADC". W 2012 IEEE Sensors. IEEE, 2012. http://dx.doi.org/10.1109/icsens.2012.6411216.

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Li, HongXiang, Xicong Wang, Changjun He i Mingjiang Wang. "A low temperature drift and low noise bandgap voltage reference for 16 bit ADC". W International Conference on Electronic Information Technology (EIT 2023), redaktorzy Wendong Xiao i Lu Leng. SPIE, 2023. http://dx.doi.org/10.1117/12.2685743.

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Meng, Xin, Yi Zhang, Tao He i Gabor C. Temes. "A noise-coupled low-distortion delta-sigma ADC with shifted loop delays". W 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2014. http://dx.doi.org/10.1109/mwscas.2014.6908483.

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Saeidi, Mitra, i Luke Theogarajan. "A Current-to-Digital ∆Σ ADC for Low-Noise High-Precision Applications". W 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2020. http://dx.doi.org/10.1109/mwscas48704.2020.9184588.

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Kalita, Triveni, i Basab Das. "A 4 bit Quantum Voltage Comparator based flash ADC for low noise applications". W 2016 Conference on Emerging Devices and Smart Systems (ICEDSS). IEEE, 2016. http://dx.doi.org/10.1109/icedss.2016.7587689.

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Raporty organizacyjne na temat "LOW NOISE ADC"

Jay. L51710 Active Noise Silencing. Chantilly, Virginia: Pipeline Research Council International, Inc. (PRCI), styczeń 1994. http://dx.doi.org/10.55274/r0010333.

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Many natural gas compressor stations which were previously located away from residential areas are now being encroached upon by surrounding building developments. Furthermore, an increased awareness of community noise issues has proved to be the impetus for investigating and developing more effective noise control methods and treatments for natural gas compressor facilities. This project investigates the feasibility of applying Active Noise Cancellation (ANC) to the exhaust of a large, internal-combustion reciprocating type engine. Large reciprocating internal combustion engines pose significant challenges for the noise control engineer. In the case of the engines employed at Tennessee Gas Pipeline Company Compressor Station 229, these engines radiate extremely low frequency exhaust noise into the surrounding environs. These engines produce discrete frequencies in the exhaust spectra with a particularly strong component at 26.5 Hz, which corresponds to the fundamental firing frequency (the 5.0 rotational order) of the engine; significant attenuation of the raw exhaust noise can be particularly difficult due to the sound power and spectral content. Traditional methods would necessitate a very large silencer in order to realize improved attenuation of the exhaust noise, relative to the existing silencer. Measurements were conducted at the error microphone location, at 1.0 meter from the exhaust outlet and at the property line. At a distance of 1.0 meter the WNCT integrated active / passive silencer yielded 84.5 dBA (92.3 dBL) while the original equipment silencer yielded 92.7 dBA (98.8 dBL). Band-limited (DC - 200 Hz) measurements were taken at the error microphone location; control off (WNCT passive - only): 109.8 dBL overall, 107.7 dBL 26.5 Hz component. With control on (WNCT active + passive) at the same position overall noise was 99.7 dBL with the 26.5 Hz component reading 89.1 dBL. Far-field A-weighted reductions were inconclusive due to the presence of other contributing noise sources possessing similar noise characteristics. Flow resistance measurements indicated that back pressure had been reduced by 95% relative to the original equipment silencer through the use of the integrated WNCT active / passive silencer.

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Herbert, Siân, i Heather Marquette. COVID-19, Governance, and Conflict: Emerging Impacts and Future Evidence Needs. Institute of Development Studies (IDS), marzec 2021. http://dx.doi.org/10.19088/k4d.2021.029.

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This paper reviews emerging evidence of the impact of COVID-19 on governance and conflict, using a “governance and conflict first” approach in contrast to other research and synthesis on COVID-19 in the social sciences that tends to be structured through a public health lens. It largely focuses on evidence on low- and middle-income countries but also includes a number of examples from high-income countries, reflecting the global nature of the crisis. It is organised around four cross-cutting themes that have enabled the identification of emerging bodies of evidence and/or analysis: Power and legitimacy; Effectiveness, capacity, and corruption; Violence, unrest, and conflict; and Resilience, vulnerability, and risk. The paper concludes with three over-arching insights that have emerged from the research: (1) the importance of leadership; (2) resilience and what “fixing the cracks” really means; and (3) why better ways are needed to add up all the “noise” when it comes to COVID-19 and evidence.

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