Gotowe bibliografie tematyczne / Low latency

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Gotowa bibliografia na temat „Low latency”

Autor: Grafiati

Data publikacji: 4 czerwca 2021

Data aktualizacji: 8 czerwca 2024

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Artykuły w czasopismach na temat "Low latency"

Hasbrouck, Joel, i Gideon Saar. "Low-latency trading". Journal of Financial Markets 16, nr 4 (listopad 2013): 646–79. http://dx.doi.org/10.1016/j.finmar.2013.05.003.

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Murtala, I., i O. A. Tiamiyu. "Comparative Analysis of Low Latency Anonymous Communication Systems". Proceedings of Telecommunication Universities 4, nr 3 (2018): 85–97. http://dx.doi.org/10.31854/1813-324x-2018-4-3-85-97.

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Riley, Holly, Rebecca B. MacLeod i Matthew Libera. "Low Latency Audio Video". Update: Applications of Research in Music Education 34, nr 3 (17.11.2014): 15–23. http://dx.doi.org/10.1177/8755123314554403.

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Roy, Pratanu, Jens Teubner i Rainer Gemulla. "Low-latency handshake join". Proceedings of the VLDB Endowment 7, nr 9 (maj 2014): 709–20. http://dx.doi.org/10.14778/2732939.2732944.

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Liu, Qing, Heming Wang, Fangxu Lyu, Geng Zhang i Dongbin Lyu. "A Low-Latency, Low-Jitter Retimer Circuit for PCIe 6.0". Electronics 12, nr 14 (17.07.2023): 3102. http://dx.doi.org/10.3390/electronics12143102.

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As the PCIe 6.0 specification places higher requirements on signal integrity and transmission latency, it becomes especially important to improve signal transmission performance at the physical layer of the transceiver interface. Retimer circuits are a key component of high-speed serial interfaces, and their delay and jitter size directly affect the overall performance of PCIe. For the typical retimer circuit with large-latency and low-jitter performance, this paper proposes a low-latency and low-jitter Retimer circuit based on CDR + PLL architecture for PCIe 6.0, using a jitter-canceling filter circuit to eliminate the frequency difference between the retiming clock and data, reduce the retiming clock jitter, and improve the quality of Retimer output data. The data are sampled using the retiming clock and then output, avoiding the problem of large penetration latency of typical retimer circuits. The circuit is designed using the CMOS 28 nm process. Simulation results show that when 112 Gbps PAM4 data are input to the retimer circuit, the Retimer penetration latency is 27.3 ps, which is 83.5% lower than the typical Retimer structure; the output jitter data are 741 fs, a 31.4% reduction compared to the typical retimer structure.

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Marinšek, Alexander, Daan Delabie, Lieven De Strycker i Liesbet Van der Perre. "Physical Layer Latency Management Mechanisms: A Study for Millimeter-Wave Wi-Fi". Electronics 10, nr 13 (3.07.2021): 1599. http://dx.doi.org/10.3390/electronics10131599.

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Emerging applications in fields such as extended reality require both a high throughput and low latency. The millimeter-wave (mmWave) spectrum is considered because of the potential in the large available bandwidth. The present work studies mmWave Wi-Fi physical layer latency management mechanisms, a key factor in providing low-latency communications for time-critical applications. We calculate physical layer latency in an ideal scenario and simulate it using a tailor-made simulation framework, based on the IEEE 802.11ad standard. Assessing data reception quality over a noisy channel yielded latency’s dependency on transmission parameters, channel noise, and digital baseband tuning. Latency in function of the modulation and coding scheme was found to span 0.28–2.71 ms in the ideal scenario, whereas simulation results also revealed its tight bond with the demapping algorithm and the number of low-density parity-check decoder iterations. The findings yielded tuning parameter combinations for reaching Pareto optimality either by constraining the bit error rate and optimizing latency or the other way around. Our assessment shows that trade-offs can and have to be made to provide sufficiently reliable low-latency communication. In good channel conditions, one may benefit from both the very high throughput and low latency; yet, in more adverse situations, lower modulation orders and additional coding overhead are a necessity.

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Arribas, Victor, Zhenda Zhang i Svetla Nikova. "LLTI: Low-Latency Threshold Implementations". IEEE Transactions on Information Forensics and Security 16 (2021): 5108–23. http://dx.doi.org/10.1109/tifs.2021.3123527.

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Hurtig, Per, Karl-Johan Grinnemo, Anna Brunstrom, Simone Ferlin, Ozgu Alay i Nicolas Kuhn. "Low-Latency Scheduling in MPTCP". IEEE/ACM Transactions on Networking 27, nr 1 (luty 2019): 302–15. http://dx.doi.org/10.1109/tnet.2018.2884791.

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Chen, Kwang-Cheng, Tao Zhang, Richard D. Gitlin i Gerhard Fettweis. "Ultra-Low Latency Mobile Networking". IEEE Network 33, nr 2 (marzec 2019): 181–87. http://dx.doi.org/10.1109/mnet.2018.1800011.

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Oesch, Christian, i Dietmar Maringer. "Low-latency liquidity inefficiency strategies". Quantitative Finance 17, nr 5 (4.11.2016): 717–27. http://dx.doi.org/10.1080/14697688.2016.1242765.

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Rozprawy doktorskie na temat "Low latency"

Wang, Yonghao. "Low latency audio processing". Thesis, Queen Mary, University of London, 2018. http://qmro.qmul.ac.uk/xmlui/handle/123456789/44697.

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Latency in the live audio processing chain has become a concern for audio engineers and system designers because significant delays can be perceived and may affect synchronisation of signals, limit interactivity, degrade sound quality and cause acoustic feedback. In recent years, latency problems have become more severe since audio processing has become digitised, high-resolution ADCs and DACs are used, complex processing is performed, and data communication networks are used for audio signal transmission in conjunction with other traffic types. In many live audio applications, latency thresholds are bounded by human perceptions. The applications such as music ensembles and live monitoring require low delay and predictable latency. Current digital audio systems either have difficulties to achieve or have to trade-off latency with other important audio processing functionalities. This thesis investigated the fundamental causes of the latency in a modern digital audio processing system: group delay, buffering delay, and physical propagation delay and their associated system components. By studying the time-critical path of a general audio system, we focus on three main functional blocks that have the significant impact on overall latency; the high-resolution digital filters in sigma-delta based ADC/DAC, the operating system to process low latency audio streams, and the audio networking to transmit audio with flexibility and convergence. In this work, we formed new theory and methods to reduce latency and accurately predict latency for group delay. We proposed new scheduling algorithms for the operating system that is suitable for low latency audio processing. We designed a new system architecture and new protocols to produce deterministic networking components that can contribute the overall timing assurance and predictability of live audio processing. The results are validated by simulations and experimental tests. Also, this bottom-up approach is aligned with the methodology that could solve the timing problem of general cyber-physical systems that require the integration of communication, software and human interactions.

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Riddoch, David James. "Low latency distributed computing". Thesis, University of Cambridge, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.619850.

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Friston, S. "Low latency rendering with dataflow architectures". Thesis, University College London (University of London), 2017. http://discovery.ucl.ac.uk/1544925/.

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The research presented in this thesis concerns latency in VR and synthetic environments. Latency is the end-to-end delay experienced by the user of an interactive computer system, between their physical actions and the perceived response to these actions. Latency is a product of the various processing, transport and buffering delays present in any current computer system. For many computer mediated applications, latency can be distracting, but it is not critical to the utility of the application. Synthetic environments on the other hand attempt to facilitate direct interaction with a digitised world. Direct interaction here implies the formation of a sensorimotor loop between the user and the digitised world - that is, the user makes predictions about how their actions affect the world, and see these predictions realised. By facilitating the formation of the this loop, the synthetic environment allows users to directly sense the digitised world, rather than the interface, and induce perceptions, such as that of the digital world existing as a distinct physical place. This has many applications for knowledge transfer and efficient interaction through the use of enhanced communication cues. The complication is, the formation of the sensorimotor loop that underpins this is highly dependent on the fidelity of the virtual stimuli, including latency. The main research questions we ask are how can the characteristics of dataflow computing be leveraged to improve the temporal fidelity of the visual stimuli, and what implications does this have on other aspects of the fidelity. Secondarily, we ask what effects latency itself has on user interaction. We test the effects of latency on physical interaction at levels previously hypothesized but unexplored. We also test for a previously unconsidered effect of latency on higher level cognitive functions. To do this, we create prototype image generators for interactive systems and virtual reality, using dataflow computing platforms. We integrate these into real interactive systems to gain practical experience of how the real perceptible benefits of alternative rendering approaches, but also what implications are when they are subject to the constraints of real systems. We quantify the differences of our systems compared with traditional systems using latency and objective image fidelity measures. We use our novel systems to perform user studies into the effects of latency. Our high performance apparatuses allow experimentation at latencies lower than previously tested in comparable studies. The low latency apparatuses are designed to minimise what is currently the largest delay in traditional rendering pipelines and we find that the approach is successful in this respect. Our 3D low latency apparatus achieves lower latencies and higher fidelities than traditional systems. The conditions under which it can do this are highly constrained however. We do not foresee dataflow computing shouldering the bulk of the rendering workload in the future but rather facilitating the augmentation of the traditional pipeline with a very high speed local loop. This may be an image distortion stage or otherwise. Our latency experiments revealed that many predictions about the effects of low latency should be re-evaluated and experimenting in this range requires great care.

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Lancaster, Robert. "Low Latency Networking in Virtualized Environments". University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1352993532.

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Tridgell, Stephen. "Low Latency Machine Learning on FPGAs". Thesis, University of Sydney, 2020. https://hdl.handle.net/2123/23030.

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In recent years, there has been an exponential rise in the quantity of data being acquired and generated. Machine learning provides a way to use and analyze this data to provide a range of insights and services. In this thesis, two popular machine learning algorithms are explored in detail and implemented in hardware to achieve high throughput and low latency. The first algorithm discussed is the Na¨ıve Online regularised Risk Minimization Algorithm. This is a Kernel Adaptive Filter capable of high throughput online learning. In this work, a hardware architecture known as braiding is proposed and implemented on a Field-Programmable Gate Array. The application of this braiding technique to the Na¨ıve Online regularised Risk Minimization Algorithm results in a very high throughput and low latency design. Neural networks have seen explosive growth in research in the recent decade. A portion of this research has been dedicated to lowering the computational cost of neural networks by using lower precision representations. The second method explored and implemented in this work is the unrolling of ternary neural networks. Ternary neural networks can have the same structure as any floating point neural network with the key difference being the weights of the network are restricted to -1,0 and 1. Under certain assumptions, this work demonstrates that these networks can be implemented very efficiently for inference by exploiting sparsity and common subexpressions. To demonstrate the effectiveness of this technique, it is applied to two different systems and two different datasets. The first is on the common benchmarking dataset CIFAR10 and the Amazon Web Services F1 platform, and the second is for real-time automatic modulation classification of radio frequency signals using the radio frequency system on chip ZCU111 development board. These implementations both demonstrate very high throughput and low latency compared with other published literature while maintaining very high accuracy. Together this work provides techniques for real-time inference and training on parallel hardware which can be used to implement a wide range of new applications.

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Marxer, Piñón Ricard. "Audio source separation for music in low-latency and high-latency scenarios". Doctoral thesis, Universitat Pompeu Fabra, 2013. http://hdl.handle.net/10803/123808.

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Aquesta tesi proposa mètodes per tractar les limitacions de les tècniques existents de separació de fonts musicals en condicions de baixa i alta latència. En primer lloc, ens centrem en els mètodes amb un baix cost computacional i baixa latència. Proposem l'ús de la regularització de Tikhonov com a mètode de descomposició de l'espectre en el context de baixa latència. El comparem amb les tècniques existents en tasques d'estimació i seguiment dels tons, que són passos crucials en molts mètodes de separació. A continuació utilitzem i avaluem el mètode de descomposició de l'espectre en tasques de separació de veu cantada, baix i percussió. En segon lloc, proposem diversos mètodes d'alta latència que milloren la separació de la veu cantada, gràcies al modelatge de components específics, com la respiració i les consonants. Finalment, explorem l'ús de correlacions temporals i anotacions manuals per millorar la separació dels instruments de percussió i dels senyals musicals polifònics complexes.
Esta tesis propone métodos para tratar las limitaciones de las técnicas existentes de separación de fuentes musicales en condiciones de baja y alta latencia. En primer lugar, nos centramos en los métodos con un bajo coste computacional y baja latencia. Proponemos el uso de la regularización de Tikhonov como método de descomposición del espectro en el contexto de baja latencia. Lo comparamos con las técnicas existentes en tareas de estimación y seguimiento de los tonos, que son pasos cruciales en muchos métodos de separación. A continuación utilizamos y evaluamos el método de descomposición del espectro en tareas de separación de voz cantada, bajo y percusión. En segundo lugar, proponemos varios métodos de alta latencia que mejoran la separación de la voz cantada, gracias al modelado de componentes que a menudo no se toman en cuenta, como la respiración y las consonantes. Finalmente, exploramos el uso de correlaciones temporales y anotaciones manuales para mejorar la separación de los instrumentos de percusión y señales musicales polifónicas complejas.
This thesis proposes specific methods to address the limitations of current music source separation methods in low-latency and high-latency scenarios. First, we focus on methods with low computational cost and low latency. We propose the use of Tikhonov regularization as a method for spectrum decomposition in the low-latency context. We compare it to existing techniques in pitch estimation and tracking tasks, crucial steps in many separation methods. We then use the proposed spectrum decomposition method in low-latency separation tasks targeting singing voice, bass and drums. Second, we propose several high-latency methods that improve the separation of singing voice by modeling components that are often not accounted for, such as breathiness and consonants. Finally, we explore using temporal correlations and human annotations to enhance the separation of drums and complex polyphonic music signals.

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Gazi, Orhan. "Parallelized Architectures For Low Latency Turbo Structures". Phd thesis, METU, 2007. http://etd.lib.metu.edu.tr/upload/12608110/index.pdf.

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In this thesis, we present low latency general concatenated code structures suitable for parallel processing. We propose parallel decodable serially concatenated codes (PDSCCs) which is a general structure to construct many variants of serially concatenated codes. Using this most general structure we derive parallel decodable serially concatenated convolutional codes (PDSCCCs). Convolutional product codes which are instances of PDSCCCs are studied in detail. PDSCCCs have much less decoding latency and show almost the same performance compared to classical serially concatenated convolutional codes. Using the same idea, we propose parallel decodable turbo codes (PDTCs) which represent a general structure to construct parallel concatenated codes. PDTCs have much less latency compared to classical turbo codes and they both achieve similar performance. We extend the approach proposed for the construction of parallel decodable concatenated codes to trellis coded modulation, turbo channel equalization, and space time trellis codes and show that low latency systems can be constructed using the same idea. Parallel decoding operation introduces new problems in implementation. One such problem is memory collision which occurs when multiple decoder units attempt accessing the same memory device. We propose novel interleaver structures which prevent the memory collision problem while achieving performance close to other interleavers.

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Goel, Ashvin. "Operating system support for low-latency streaming /". Full text open access at:, 2003. http://content.ohsu.edu/u?/etd,194.

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Guan, Xi. "MeteorShower: geo-replicated strongly consistent NoSQL data store with low latency : Achieving sequentially consistent keyvalue store with low latency". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-180687.

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According to CAP theorem, strong consistency is usually compromised in the design of NoSQL databases. Poor performance is often observed when strong data consistency level is required, especially when a system is deployed in a geographical environment. In such an environment, servers need to communicate through cross-datacenter messages, whose latency is much higher than message within a data center. However, maintaining strong consistency usually involves extensive usage of cross-datacenter messages. Thus, the large cross-data center communication delay is one of the most dominant reasons, which leads to poor performance of most algorithms achieving strong consistency in a geographical environment. This thesis work proposes a novel data consistency algorithm – I-Write-One-Read-One based on Write-One-Read- All. The novel approach allows a read request to be responded by performing a local read. Besides, it reduces the cross-datacenter-consistency-synchronization message delay from a round trip to a single trip. Moreover, the consistency model achieved in I-Write-One-Read-One is higher than sequential consistency, however, looser than linearizability. In order to verify the correctness and effectiveness of IWrite- One-Read-One, a prototype, MeteoerShower, is implemented on Cassandra. Furthermore, in order to reduce time skews among nodes, NTP servers are deployed. Compared to Cassandra with Write-One-Read-All consistency setup, MeteoerShower has almost the same write performance but much lower read latency in a real geographical deployment. The higher cross-datacenter network delay, the more evident of the read performance improvement. Same as Cassandra, MeteorShower also has excellent horizontal scalability, where its performance grows linearly with the increasing number of nodes per data center.

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Ge, Wu. "A Continuous Dataflow Pipeline For Low Latency Recommendations". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-180695.

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The goal of building recommender system is to generate personalized recommendations to users. Recommender system has great value in multiple business verticals like video on demand, news, advertising and retailing. In order to recommend to each individual, large number of personal preference data need to be collected and processed. Processing big data usually takes long time. The long delays from data entered system to results being generated makes recommender systems can only benefit returning users. This project is an attempt to build a recommender system as service with low latency, to make it applicable for more scenarios. In this paper, different recommendation algorithms, distributed computing frameworks are studied and compared to identify the most suitable design. Experiment results reviled the logarithmical relationship between recommendation quality and training data size in collaborative filtering. By applying the finding, a low latency recommendation workflow is achieved by reduce training data size and create parallel computing partitions with minimal cost of prediction quality. In this project the calculation time is successfully limited in 3 seconds (instead of 25 in control value) while maintaining 90% of the prediction quality.

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Książki na temat "Low latency"

Credle, Rufus. WebSphere MQ low latency messaging development guide. [United States]: IBM International Technical Support Organization, 2009.

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Center, Langley Research, red. Low latency messages on distributed memory multiprocessors. Hampton, Va: National Aeronautics and Space Administration, Langley Research Center, 1993.

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Center, Langley Research, red. Low latency messages on distributed memory multiprocessors. Hampton, Va: National Aeronautics and Space Administration, Langley Research Center, 1993.

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Sladic, Daniel. Exploiting low-latency communication in single-chip multiprocessors. Ottawa: National Library of Canada, 1998.

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Sladic, Daniel. Exploiting low-latency communication in single-chip multiprocessors. Ottawa: National Library of Canada, 1998.

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K, Kokula Krishna Hari, red. Power Analysis of Embedded Low Latency Network on Chip. Chennai, India: Association of Scientists, Developers and Faculties, 2016.

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Chakravarty, Sambuddho. Traffic Analysis Attacks and Defenses in Low Latency Anonymous Communication. [New York, N.Y.?]: [publisher not identified], 2014.

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Engineers, Institute Of Electrical and Electronics. IEEE standard for heterogeneous interconnect (HIC) (low-cost, low-latency scalable serial interconnect for parallel system construction). New York, NY: The Institute, 1996.

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1955-, Katz Randy H., i United States. National Aeronautics and Space Administration., red. Robo-line storage: Low latency, high capacity storage systems over geographically distributed networks. Berkeley, Calif: Computer Science Division (EECS), University of California, Berkeley, 1991.

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Części książek na temat "Low latency"

Park, Chanho, i Hagyoung Kim. "Low Latency Video Transmission Device". W Lecture Notes in Electrical Engineering, 217–22. Berlin, Heidelberg: Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-46578-3_25.

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Kinniment, D. J., i A. V. Yakovlev. "Low Latency Synchronization Through Speculation". W Lecture Notes in Computer Science, 278–88. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30205-6_30.

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Giard, Pascal, Claude Thibeault i Warren J. Gross. "Low-Latency Software Polar Decoders". W High-Speed Decoders for Polar Codes, 31–53. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-59782-9_3.

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Pasman, W., S. Persa i F. W. Jansen. "Realistic low-latency mobile AR rendering". W Virtual and Augmented Architecture (VAA’01), 81–92. London: Springer London, 2001. http://dx.doi.org/10.1007/978-1-4471-0337-0_8.

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Yan, Ke, Huazhong Yang i Hui Wang. "A Low Latency Variance NoC Router". W Lecture Notes in Electrical Engineering, 89–97. Dordrecht: Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-94-007-5076-0_10.

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Yang, Guang, i Ming Xiao. "Low-Latency Communications with Millimeter Wave". W Encyclopedia of Wireless Networks, 733–36. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-319-78262-1_109.

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Burnside, Matthew, i Angelos D. Keromytis. "Low Latency Anonymity with Mix Rings". W Lecture Notes in Computer Science, 32–45. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11836810_3.

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Yang, Guang, i Ming Xiao. "Low-Latency Communications with Millimeter Wave". W Encyclopedia of Wireless Networks, 1–4. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-32903-1_109-1.

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McTasney, Robert, Dirk Grunwald i Douglas Sicker. "Low Latency in Wireless Mesh Networks". W Computer Communications and Networks, 379–424. London: Springer London, 2009. http://dx.doi.org/10.1007/978-1-84800-909-7_15.

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Lin, Shih-Chun, Tsung-Hui Chang, Eduard Jorswieck i Pin-Hsun Lin. "Applications: Low Latency Communications in 6G". W Information Theory, Mathematical Optimization, and Their Crossroads in 6G System Design, 249–309. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2016-5_7.

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Streszczenia konferencji na temat "Low latency"

Fischer, Martin J., Denise M. Bevilacqua Masi i John F. Shortle. "Approximating Low Latency Queueing Buffer Latency". W 2008 Fourth Advanced International Conference on Telecommunications (AICT). IEEE, 2008. http://dx.doi.org/10.1109/aict.2008.7.

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Maric, I. "Low latency communications". W 2013 Information Theory and Applications Workshop (ITA 2013). IEEE, 2013. http://dx.doi.org/10.1109/ita.2013.6502956.

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Donghyuk Lee, Yoongu Kim, V. Seshadri, Jamie Liu, L. Subramanian i O. Mutlu. "Tiered-latency DRAM: A low latency and low cost DRAM architecture". W 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2013. http://dx.doi.org/10.1109/hpca.2013.6522354.

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Vulimiri, Ashish, Philip Brighten Godfrey, Radhika Mittal, Justine Sherry, Sylvia Ratnasamy i Scott Shenker. "Low latency via redundancy". W CoNEXT '13: Conference on emerging Networking Experiments and Technologies. New York, NY, USA: ACM, 2013. http://dx.doi.org/10.1145/2535372.2535392.

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Freiberger-Verizon, Michael, David Templeton-Verizon i Engel Mercado-Verizon. "Low Latency Optical Services". W National Fiber Optic Engineers Conference. Washington, D.C.: OSA, 2012. http://dx.doi.org/10.1364/nfoec.2012.ntu2e.1.

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Kamburugamuve, Supun, Karthik Ramasamy, Martin Swany i Geoffrey Fox. "Low Latency Stream Processing". W UCC '17: 10th International Conference on Utility and Cloud Computing. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3147213.3147232.

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Hu, Yuncong, Kian Hooshmand, Harika Kalidhindi, Seung Jin Yang i Raluca Ada Popa. "Merkle2: A Low-Latency Transparency Log System". W 2021 IEEE Symposium on Security and Privacy (SP). IEEE, 2021. http://dx.doi.org/10.1109/sp40001.2021.00088.

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van der Tempel, Ward, Robert Collier, Kostas Pataridis, Ségolène Rogge, Arman Alaie, Jean-Sébastien Staelens, Mahmoud Shahin, Johannes Peeters, André Miodezky i Christian Mourad. "Low power, low latency perception for XR". W Optical Architectures for Displays and Sensing in Augmented, Virtual, and Mixed Reality (AR, VR, MR) IV, redaktorzy Bernard C. Kress i Christophe Peroz. SPIE, 2023. http://dx.doi.org/10.1117/12.2663040.

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Li, Yule, Jianping Shi i Dahua Lin. "Low-Latency Video Semantic Segmentation". W 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR). IEEE, 2018. http://dx.doi.org/10.1109/cvpr.2018.00628.

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Niehues, Jan, Ngoc-Quan Pham, Thanh-Le Ha, Matthias Sperber i Alex Waibel. "Low-Latency Neural Speech Translation". W Interspeech 2018. ISCA: ISCA, 2018. http://dx.doi.org/10.21437/interspeech.2018-1055.

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Raporty organizacyjne na temat "Low latency"

El, K., red. Low-Latency Handoffs in Mobile IPv4. RFC Editor, czerwiec 2007. http://dx.doi.org/10.17487/rfc4881.

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Luzum, Brian, i Axel Nothnagel. Improved UT1 Predictions through Low-Latency VLBI Observations. Fort Belvoir, VA: Defense Technical Information Center, marzec 2010. http://dx.doi.org/10.21236/ada524037.

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Karnitski, Anton, Christopher Gill, Aliaksandr Zhankevich i Dalius Baranauskas. 12-bit 32 Channel 500MSps Low Latency ADC. Office of Scientific and Technical Information (OSTI), listopad 2017. http://dx.doi.org/10.2172/1413257.

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De Schepper, K., M. Bagnulo i G. White. Low Latency, Low Loss, and Scalable Throughput (L4S) Internet Service: Architecture. Redaktor B. Briscoe. RFC Editor, styczeń 2023. http://dx.doi.org/10.17487/rfc9330.

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Brustoloni, Jose C., i Brian N. Bershad. Simple Protocol Processing fro High-Bandwidth Low-Latency Networking. Fort Belvoir, VA: Defense Technical Information Center, marzec 1992. http://dx.doi.org/10.21236/ada265367.

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Anderson, Ken. Low-Latency Ultra-High Capacity Holographic Data Storage Archive Library. Office of Scientific and Technical Information (OSTI), grudzień 2014. http://dx.doi.org/10.2172/1164637.

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Lee, H. W. H., i R. N. Shelton. Investigation of fullerenes for high speed low latency, photonic switching. Office of Scientific and Technical Information (OSTI), luty 1997. http://dx.doi.org/10.2172/572758.

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Bhat, Amit. Low-latency Estimates for Window-Aggregate Queries over Data Streams. Portland State University Library, styczeń 2000. http://dx.doi.org/10.15760/etd.161.

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Yoo, S. J. Ultra-Low Latency Multiprotocol Optical Routers for the Next Generation Internet. Fort Belvoir, VA: Defense Technical Information Center, maj 2003. http://dx.doi.org/10.21236/ada416409.

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De Schepper, K. The Explicit Congestion Notification (ECN) Protocol for Low Latency, Low Loss, and Scalable Throughput (L4S). Redaktor B. Briscoe. RFC Editor, styczeń 2023. http://dx.doi.org/10.17487/rfc9331.

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