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Gotowe bibliografie tematyczne / Low effective mass channel material transistors

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Gotowa bibliografia na temat „Low effective mass channel material transistors”

Autor: Grafiati

Data publikacji: 6 września 2023

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Artykuły w czasopismach na temat "Low effective mass channel material transistors"

1

van Fraassen, Niels C. A., Sanggil Han, Kham Niang, and Andrew J. John Flewitt. "(Invited) Achieving Lower Power Logic Using P-Type Metal Oxide Thin Film Transistors." ECS Meeting Abstracts MA2022-02, no. 35 (2022): 1267. http://dx.doi.org/10.1149/ma2022-02351267mtgabs.

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Thin film transistors (TFTs) have enabled the active matrix displays that are a ubiquitous part of everyday life, from mobile phones and tablets through to desktop monitors and home televisions. They are used in the circuit at each pixel over the display as they can be fabricated for relatively low cost with excellent uniformity at low temperatures over large areas on glass substrates. These pixel circuits only require either n-channel or p-channel enhancement mode TFTs. However, there has long been a desire to integrate the display driver electronics onto the display panel as an alternative t

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Yen, Te Jui, Albert Chin, Weng Kent Chan, Hsin-Yi Tiffany Chen, and Vladimir Gritsenko. "Remarkably High-Performance Nanosheet GeSn Thin-Film Transistor." Nanomaterials 12, no. 2 (2022): 261. http://dx.doi.org/10.3390/nano12020261.

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High-performance p-type thin-film transistors (pTFTs) are crucial for realizing low-power display-on-panel and monolithic three-dimensional integrated circuits. Unfortunately, it is difficult to achieve a high hole mobility of greater than 10 cm2/V·s, even for SnO TFTs with a unique single-hole band and a small hole effective mass. In this paper, we demonstrate a high-performance GeSn pTFT with a high field-effect hole mobility (μFE), of 41.8 cm2/V·s; a sharp turn-on subthreshold slope (SS), of 311 mV/dec, for low-voltage operation; and a large on-current/off-current (ION/IOFF) value, of 8.9 ×

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Pooja, Pheiroijam, Chun Che Chien, and Albert Chin. "Superior High Transistor’s Effective Mobility of 325 cm2/V-s by 5 nm Quasi-Two-Dimensional SnON nFET." Nanomaterials 13, no. 12 (2023): 1892. http://dx.doi.org/10.3390/nano13121892.

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This work reports the first nanocrystalline SnON (7.6% nitrogen content) nanosheet n-type Field-Effect Transistor (nFET) with the transistor’s effective mobility (µeff) as high as 357 and 325 cm2/V-s at electron density (Qe) of 5 × 1012 cm−2 and an ultra-thin body thickness (Tbody) of 7 nm and 5 nm, respectively. At the same Tbody and Qe, these µeff values are significantly higher than those of single-crystalline Si, InGaAs, thin-body Si-on-Insulator (SOI), two-dimensional (2D) MoS2 and WS2. The new discovery of a slower µeff decay rate at high Qe than that of the SiO2/bulk-Si universal curve

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4

Lee, Dong Hun, Yuxuan Zhang, Kwangsoo No, Han Wook Song, and Sunghwan Lee. "(Digital Presentation) Multimodal Encapsulation of p-SnOx to Engineer the Carrier Density for Thin Film Transistor Applications." ECS Meeting Abstracts MA2022-02, no. 15 (2022): 821. http://dx.doi.org/10.1149/ma2022-0215821mtgabs.

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It has been challenging to synthesize p-type SnOx (1≤x<2) and engineer the electrical properties such as carrier density and mobility due to the narrow processing window and the localized oxygen 2p orbitals near the valence band. We recently reported on the processing of p-type SnOx and an oxide-based p-n heterostructures, demonstrating high on/off rectification ratio (>103), small turn-on voltage (<0.5 V), and low saturation current (~1×10-10 A)1. In order to further understand the p-type oxide and engineer the properties for various electronic device applications, it is important to

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5

Tong, Shi Wun, and Man-Fai Ng. "(Digital Presentation) Scalable Growth of Transition Metal Dichalcogenides for Next-Generation Nanoelectronics." ECS Meeting Abstracts MA2022-02, no. 36 (2022): 1343. http://dx.doi.org/10.1149/ma2022-02361343mtgabs.

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Alternative channel materials for future ultra-scaled electronic devices have been intensively pursued nowadays since the feature size of silicon-based transistors has been scaled down to their physical limit. Atomically-thin semiconducting transitional metal dichalcogenides (TMDCs) including WS2, MoS2, WSe2, MoSe2, e. have shown a lot of unique properties compared to their bulk crystals, such as indirect-to-direct bandgap transitions, strong spin-orbit coupling and valley polarization. In particular, monolayer WS2 has shown the highest theoretical room temperature electron mobility among othe

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6

Choy, JUN-HO, Valeriy Sukharev, Armen Kteyan, Stephane Moreau, and Catherine Brunet-Manquat. "(Invited, Digital Presentation) Advanced Methodology for Assessing Chip Package Interaction Induced Stress Effects on Chip Performance and Reliability." ECS Meeting Abstracts MA2022-02, no. 17 (2022): 846. http://dx.doi.org/10.1149/ma2022-0217846mtgabs.

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In IC industry, the use of multiple die stack packaging has emerged to meet the increasing demand in miniaturization and improved functionality of mobile devices. During chip operation, transistor power dissipation raises temperature unevenly across a die. The generated thermal hotspots negatively impact reliability and degrade performance. In mechanical aspects, dies become thinner, and bumps and pitch become smaller, which makes heat dissipation more difficult, and lead to increase in mechanical stress. Such stress may cause carrier mobility degradation for transistors and could lead to para

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7

Wulf, Ulrich, and Hans Richter. "Scaling in Quantum Transport in Silicon Nano-Transistors." Solid State Phenomena 156-158 (October 2009): 517–21. http://dx.doi.org/10.4028/www.scientific.net/ssp.156-158.517.

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We develop a theory for scaling properties of quantum transport in nano-field effect transistors. Our starting point is a one-dimensional effective expression for the drain current in the Landauer-Büttiker formalism. Assuming a relatively simple total potential acting on the electrons the effective theory can be reduced to a scale-invariant form yielding a set of dimensionless control parameters. Among these control parameters are the characteristic length l and -width w of the electron channel which are its physical length and -width in units of the scaling length . Here is the Fermi energy i

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8

Zhu, Yan, and Mantu K. Hudait. "Low-power tunnel field effect transistors using mixed As and Sb based heterostructures." Nanotechnology Reviews 2, no. 6 (2013): 637–78. http://dx.doi.org/10.1515/ntrev-2012-0082.

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AbstractReducing supply voltage is a promising way to address the power dissipation in nano-electronic circuits. However, the fundamental lower limit of subthreshold slope (SS) within metal oxide semiconductor field effect transistors (MOSFETs) is a major obstacle to further scaling the operation voltage without degrading ON/OFF ratio in current integrated circuits. Tunnel field-effect transistors (TFETs) benefit from steep switching characteristics due to the quantum-mechanical tunneling injection of carriers from source to channel, rather than by conventional thermionic emission in MOSFETs.

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9

Pakmehr, Mehdi, B. D. McCombe, Olivio Chiatti, S. F. Fischer, Ch Heyn, and W. Hansen. "Characterization of High Mobility InAs/InGaAs/InAlAs Composite Channels by THz Magneto-Photoresponse Spectroscopy." International Journal of High Speed Electronics and Systems 24, no. 01n02 (2015): 1520004. http://dx.doi.org/10.1142/s0129156415200049.

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Inserted narrow InAs quantum wells in InAs/InGaAs/InAlAs heterostructures have been used to achieve higher mobility for high-electron-mobility transistors (HEMTs) with ultra-low-power and low-noise amplification characteristics and for spin-based devices. Due to the large nonparabolicity of the conduction band of InAs and the penetration of the confined electronic envelope function into the adjacent layer(s), accurate calculations of effective mass and g-factor of charge carriers can be problematic. Methods of making precise determinations of the mass and other electronic parameters are thus o

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10

John Chelliah, Cyril R. A., and Rajesh Swaminathan. "Current trends in changing the channel in MOSFETs by III–V semiconducting nanostructures." Nanotechnology Reviews 6, no. 6 (2017): 613–23. http://dx.doi.org/10.1515/ntrev-2017-0155.

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AbstractThe quest for high device density in advanced technology nodes makes strain engineering increasingly difficult in the last few decades. The mechanical strain and performance gain has also started to diminish due to aggressive transistor pitch scaling. In order to continue Moore’s law of scaling, it is necessary to find an effective way to enhance carrier transport in scaled dimensions. In this regard, the use of alternative nanomaterials that have superior transport properties for metal-oxide-semiconductor field-effect transistor (MOSFET) channel would be advantageous. Because of the e

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