Gotowa bibliografia na temat „Low effective mass channel material transistors”

Thin film transistors (TFTs) have enabled the active matrix displays that are a ubiquitous part of everyday life, from mobile phones and tablets through to desktop monitors and home televisions. They are used in the circuit at each pixel over the display as they can be fabricated for relatively low cost with excellent uniformity at low temperatures over large areas on glass substrates. These pixel circuits only require either n-channel or p-channel enhancement mode TFTs. However, there has long been a desire to integrate the display driver electronics onto the display panel as an alternative to connecting silicon-based integrated circuits using complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) to displays. More recently, there has been an increasing interest in producing other logic circuits using TFTs on glass and plastic substrates as this could enable a new generation of products with embedded electronics. However, both of these applications need low power logic circuits. CMOS is an inherently low power technology, but it requires both n-channel and p-channel transistors. Whilst this can be realised in silicon CMOS FETs, it has not yet been achieved using TFTs because it has proved difficult to realise both n-channel and p-channel devices using one material system at low cost. For example, hydrogenated amorphous silicon can be used to make reasonable n-type material but not p-type. Thin film oxide semiconductors such as amorphous indium gallium zinc oxide have been successfully commercialised in the pixel circuits of active matrix displays as they possess high field effect mobility, low threshold voltage, low off-state current and a high switching ratio. There is therefore a lot of interest in finding a suitable complementary p-type metal oxide thin film material to allow CMOS-type logic to be realised using this material system. Cuprous oxide is one such promising candidate material as the top of the valence band is dominated by states which form as a result of hybridisation of the completely filled Cu 3d orbitals and the O 2p orbitals. These hybridised states are less localised and have a higher dispersion with a resulting decrease in the effective mass of holes in these states and a higher carrier mobility. The results of an extensive study of this material shows that the grain structure is of critical importance with [100] oriented films resulting in a higher mobility. Furthermore, the impact of grain boundaries on conduction must be controlled. Although this allows TFTs with reasonable on-state current to be fabricated, it is found that there is a significant residual off-state current which is a result of electron accumulation in the channel. This is consistent with the high off-state current that has been observed widely in TFTs using p-type metal oxide thin film materials. The low off-state current in silicon MOSFETs means that the geometric transistor design in low power CMOS logic circuits only needs to focus on the effect of the on-state current in the p-channel and n-channel transistors. However, in TFTs, the much larger off-state current also becomes important as it can end up being a significant parameter when calculating the power consumption of CMOS logic circuits. An alternative geometric design parameter for TFT logic circuits is presented. This compares the maximum switching current with the static currents allowing optimisation based on both the noise margin and static power consumption. The result is improved performance of TFT-based CMOS logic circuits using the n- and p-type thin film oxide semiconductors that are currently available.

High-performance p-type thin-film transistors (pTFTs) are crucial for realizing low-power display-on-panel and monolithic three-dimensional integrated circuits. Unfortunately, it is difficult to achieve a high hole mobility of greater than 10 cm2/V·s, even for SnO TFTs with a unique single-hole band and a small hole effective mass. In this paper, we demonstrate a high-performance GeSn pTFT with a high field-effect hole mobility (μFE), of 41.8 cm2/V·s; a sharp turn-on subthreshold slope (SS), of 311 mV/dec, for low-voltage operation; and a large on-current/off-current (ION/IOFF) value, of 8.9 × 106. This remarkably high ION/IOFF is achieved using an ultra-thin nanosheet GeSn, with a thickness of only 7 nm. Although an even higher hole mobility (103.8 cm2/V·s) was obtained with a thicker GeSn channel, the IOFF increased rapidly and the poor ION/IOFF (75) was unsuitable for transistor applications. The high mobility is due to the small hole effective mass of GeSn, which is supported by first-principles electronic structure calculations.

This work reports the first nanocrystalline SnON (7.6% nitrogen content) nanosheet n-type Field-Effect Transistor (nFET) with the transistor’s effective mobility (µeff) as high as 357 and 325 cm2/V-s at electron density (Qe) of 5 × 1012 cm−2 and an ultra-thin body thickness (Tbody) of 7 nm and 5 nm, respectively. At the same Tbody and Qe, these µeff values are significantly higher than those of single-crystalline Si, InGaAs, thin-body Si-on-Insulator (SOI), two-dimensional (2D) MoS2 and WS2. The new discovery of a slower µeff decay rate at high Qe than that of the SiO2/bulk-Si universal curve was found, owing to a one order of magnitude lower effective field (Eeff) by more than 10 times higher dielectric constant (κ) in the channel material, which keeps the electron wave-function away from the gate-oxide/semiconductor interface and lowers the gate-oxide surface scattering. In addition, the high µeff is also due to the overlapped large radius s-orbitals, low 0.29 mo effective mass (me*) and low polar optical phonon scattering. SnON nFETs with record-breaking µeff and quasi-2D thickness enable a potential monolithic three-dimensional (3D) integrated circuit (IC) and embedded memory for 3D biological brain-mimicking structures.

It has been challenging to synthesize p-type SnOx (1≤x<2) and engineer the electrical properties such as carrier density and mobility due to the narrow processing window and the localized oxygen 2p orbitals near the valence band. We recently reported on the processing of p-type SnOx and an oxide-based p-n heterostructures, demonstrating high on/off rectification ratio (>103), small turn-on voltage (<0.5 V), and low saturation current (~1×10-10 A)1. In order to further understand the p-type oxide and engineer the properties for various electronic device applications, it is important to identify (or establish) the dominating doping and transport mechanisms. The low dopability in p-type SnOx, of which the causation is also closely related to the narrow processing window, needs to be mitigated so that the electrical properties of the material are to be adequately engineered 2, 3. Herein, we report on the multifunctional encapsulation of p-SnOx to limit the surface adsorption of oxygen and selectively permeate hydrogen into the p-SnOx channel for thin film transistor (TFT) applications. Time-of-flight secondary ion mass spectrometry measurements identified that ultra-thin SiO2 as a multifunctional encapsulation layer effectively suppressed the oxygen adsorption on the back channel surface of p-SnOx and augmented hydrogen density across the entire thickness of the channel. Encapsulated p-SnOx-based TFTs demonstrated much-enhanced channel conductance modulation in response to the gate bias applied, featuring higher on-state current and lower off-state current. The relevance between the TFT performance and the effects of oxygen suppression and hydrogen permeation is discussed in regard to the intrinsic and extrinsic doping mechanisms. These results are supported by density-functional-theory calculations. Acknowledgement This work was supported by the U.S. National Science Foundation (NSF) Award No. ECCS-1931088. S.L. and H.W.S. acknowledge the support from the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 20011028) by KRISS. K.N. was supported by Basic Science Research Program (NRF-2021R11A1A01051246) through the NRF Korea funded by the Ministry of Education. References Lee, D. H.; Park, H.; Clevenger, M.; Kim, H.; Kim, C. S.; Liu, M.; Kim, G.; Song, H. W.; No, K.; Kim, S. Y.; Ko, D.-K.; Lucietto, A.; Park, H.; Lee, S., High-Performance Oxide-Based p–n Heterojunctions Integrating p-SnOx and n-InGaZnO. ACS Applied Materials & Interfaces 2021, 13 (46), 55676-55686. Hautier, G.; Miglio, A.; Ceder, G.; Rignanese, G.-M.; Gonze, X., Identification and design principles of low hole effective mass p-type transparent conducting oxides. Nat Commun 2013, 4. Yim, K.; Youn, Y.; Lee, M.; Yoo, D.; Lee, J.; Cho, S. H.; Han, S., Computational discovery of p-type transparent oxide semiconductors using hydrogen descriptor. npj Computational Materials 2018, 4 (1), 17. Figure 1

Alternative channel materials for future ultra-scaled electronic devices have been intensively pursued nowadays since the feature size of silicon-based transistors has been scaled down to their physical limit. Atomically-thin semiconducting transitional metal dichalcogenides (TMDCs) including WS2, MoS2, WSe2, MoSe2, e. have shown a lot of unique properties compared to their bulk crystals, such as indirect-to-direct bandgap transitions, strong spin-orbit coupling and valley polarization. In particular, monolayer WS2 has shown the highest theoretical room temperature electron mobility among other semiconducting TMDCs as a result of its low effective mass. Combined with the large exciton/trion binding energy with high photoluminescence quantum yield, monolayer WS2 is a strong candidate as a potential channel material for high-efficiency optoelectronic applications. However, it is still challenging to grow wafer-sized, highly uniform and strictly monolayer TMDCs continuous film through the conventional chemical vapor deposition (CVD) due to the uncontrollable growth kinetics. The evaporation rates and amounts of the heated precursors are uncontrollable because the saturation vapor pressure of the precursor is exponentially dependent on the temperature inside the furnace. The sulfurized film is thus consisted of a mixture of monolayer, bilayer and multiple layers of TMDCs. The film with such unreproducible quality is not applicable for real industrial applications. In this work, we provide a self-limiting growth strategy based on modified CVD process to prepare the wafer-sized monolayer TMDCs. Theoretical simulations were performed to understand the fundamental thermodynamically mechanism of the strictly monolayer growth. The property-variation in TMDCs due to difference in electronic structure between different layers of TMDCs can be significantly reduced based on this new approach. The following figure indicates that the PL spectra detected from different spots (spot 1 to 5) of the WS2 film. All spectra measured from the 4'' wafer-sized sample show characteristics unique to monolayer WS2. This poses a reliable route for the growth of large-area monolayer TMDCs, which is essential for their reliable and robust applications in nanoelectronic devices. Figure 1

In IC industry, the use of multiple die stack packaging has emerged to meet the increasing demand in miniaturization and improved functionality of mobile devices. During chip operation, transistor power dissipation raises temperature unevenly across a die. The generated thermal hotspots negatively impact reliability and degrade performance. In mechanical aspects, dies become thinner, and bumps and pitch become smaller, which makes heat dissipation more difficult, and lead to increase in mechanical stress. Such stress may cause carrier mobility degradation for transistors and could lead to parametric circuit failure. In the back-end-of-line (BEoL) interconnects, the employed ultra-low k materials prone to damage interconnects when mechanical stress is present, due to its brittle nature and poor adhesion to the barrier materials. These stresses originated at the die packaging step due to thermal mismatch between die and package materials, which is termed as chip package interaction (CPI). We call mechanical CPI (mCPI) when such stress affects reliability of the whole chip, i.e., BEoL, RDL (redistribution layer), bump, or TSVs (through silicon vias). When such stress affects device performance, we call electrical CPI (eCPI). To analyze CPI effects on a feature scale, i.e., in transistor channel or in the individual metal line or ILD (inter layer dielectric) /IMD (inter metal dielectric) gap, an analysis tool must generate accurate feature-scale stress variation across a die. Finite element analysis (FEA) is widely used for analyzing CPI induced problems. However, the traditional FEA cannot effectively handle feature-scale geometries due to huge memory consumption, and instead, treats a die as a uniform material block. Therefore, this approach cannot describe stress distribution caused by local non-uniformity of metal line distribution and fail to provide the needed accuracy for feature-scale analysis. [1] Here, we present an advanced physics-based EDA tool that overcomes the above-mentioned problems by introducing the novel methodology of extracting effective anisotropic thermal-mechanical properties (EMP), as well as employing FEA-based multi-scale simulation procedure. Prior to running FEA, the tool extracts EMP that accurately represent non-uniformities at different scales within a simulation domain. Here, each metal layer in a die is considered a binary system that consists of metal inclusions embedded in an insulator matrix. By dividing the die area into bins, metal density dependent effective properties for each bin are calculated according to theory of anisotropic composite materials. Anisotropy of properties can be obtained by taking routing direction of metal lines into account [2, 3]. EMP can adjust to multi-scale by varying bin size as shown in Fig.1. Here, Young’s modulus is extracted globally with coarse grid, and on sub-modeling region with very fine grid, which shows the corresponding property variation with much finer scale. Since EMP constructs no actual geometrical objects, the methodology can efficiently handle feature-scale objects on a large layout region. When a user selects a circuit block, or a region to be analyzed in detail, the automated tool flow enables two step stress simulation procedure, which is schematically shown in Fig. 2. First, the global-scale stress simulation is performed with coarse both the simulation mesh and EMP bin and extracts the boundary displacements for the circuit block. These boundary displacements are employed in the sub-modeling, with employed fine mesh and EMP bin. Figure 3 demonstrates the importance of EMP for accurate resolution of stress field. The 2D color maps show the x-component of stress distributions in a circuit block as a result of sub-modeling. Here, die BEoL is represented by EMP in (a), while in (b), the entire die including BEoL is represented by silicon, which is employed in traditional FEA. The stress pattern due to interconnect layout details are visible only when EMP is employed. The difference is even more pronounced when 1D stress profile is compared. By back annotating the obtained stress components in a SPICE netlist, the tool enables a user to perform accurate circuit simulation with accounted CPI effects. In eCPI analysis, the tool has been validated by employing measurements of different types of devices [4]. The additional tool capabilities that will be presented are mCPI analysis and thermomechanical stress analysis during chip operating conditions. [1] R. Radojcic, More-than-Moore 2.5D and 3D SiP Integration, Springer, 2017. [2] V. Sukharev et al. J. Electron Test, vol. 28, pp. 63-72, 2012 [3] V. Sukharev et al., Proc. Int. 3D Systems Integration Conference, 2019 [4]. A. Kteyan, et al. Proc. ISPD 2022 Figure 1

We develop a theory for scaling properties of quantum transport in nano-field effect transistors. Our starting point is a one-dimensional effective expression for the drain current in the Landauer-Büttiker formalism. Assuming a relatively simple total potential acting on the electrons the effective theory can be reduced to a scale-invariant form yielding a set of dimensionless control parameters. Among these control parameters are the characteristic length l and -width w of the electron channel which are its physical length and -width in units of the scaling length . Here is the Fermi energy in the source contact and is the effective mass in the electron channel. In the limit of wide transistors and low temperatures we evaluate the scale-invariant i-v characteristics as a function of the characteristic length. In the strong barrier regime, i. e. for long-channel behavior is found. At weaker barriers source-drain tunneling leads to increasingly significant deviations from the long-channel behavior.

AbstractReducing supply voltage is a promising way to address the power dissipation in nano-electronic circuits. However, the fundamental lower limit of subthreshold slope (SS) within metal oxide semiconductor field effect transistors (MOSFETs) is a major obstacle to further scaling the operation voltage without degrading ON/OFF ratio in current integrated circuits. Tunnel field-effect transistors (TFETs) benefit from steep switching characteristics due to the quantum-mechanical tunneling injection of carriers from source to channel, rather than by conventional thermionic emission in MOSFETs. TFETs based on group III-V compound semiconductor materials further improve the ON-state current and reduce SS due to the low band gap energies and smaller carrier tunneling mass. The mixed arsenide/antimonide (As/Sb) InxGa1-xAs/GaAsySb1-y heterostructures allow a wide range of band gap energies and various staggered band alignments depending on the alloy compositions in the source and channel materials. Band alignments at source/channel heterointerface can be well modulated by carefully controlling the compositions of the mixed As/Sb material system. In particular, this review introduces and summarizes the progress in the development and optimization of low-power TFETs using mixed As/Sb based heterostructures including basic working principles, design considerations, material growth, interface engineering, material characterization, device fabrication, device performance investigation, band alignment determination, and high temperature reliability. A review of TFETs using mixed As/Sb based heterostructures shows superior structural properties and distinguished device performance, both of which indicate the mixed As/Sb staggered gap TFET as a promising option for high-performance, low-standby power, and energy-efficient logic circuit application.

Inserted narrow InAs quantum wells in InAs/InGaAs/InAlAs heterostructures have been used to achieve higher mobility for high-electron-mobility transistors (HEMTs) with ultra-low-power and low-noise amplification characteristics and for spin-based devices. Due to the large nonparabolicity of the conduction band of InAs and the penetration of the confined electronic envelope function into the adjacent layer(s), accurate calculations of effective mass and g-factor of charge carriers can be problematic. Methods of making precise determinations of the mass and other electronic parameters are thus of interest. We have applied magneto-photoresponse and -transmissions measurements at several THz laser frequencies in concert with dc magnetotransport measurements at low temperature (T = 1.6 K) to determine various electronic parameters (effective mass, carrier density, g-factor, mobility and the quantum scattering time) of the 2DEG in an InAs/In0.75Ga0.25As/In0.75Al0.25As inserted channel structure. This characterization method can also be used to probe the effect of strain, Rashba field, etc on the properties of charge carriers in such structures.

AbstractThe quest for high device density in advanced technology nodes makes strain engineering increasingly difficult in the last few decades. The mechanical strain and performance gain has also started to diminish due to aggressive transistor pitch scaling. In order to continue Moore’s law of scaling, it is necessary to find an effective way to enhance carrier transport in scaled dimensions. In this regard, the use of alternative nanomaterials that have superior transport properties for metal-oxide-semiconductor field-effect transistor (MOSFET) channel would be advantageous. Because of the extraordinary electron transport properties of certain III–V compound semiconductors, III–Vs are considered a promising candidate as a channel material for future channel metal-oxide-semiconductor transistors and complementary metal-oxide-semiconductor devices. In this review, the importance of the III–V semiconductor nanostructured channel in MOSFET is highlighted with a proposed III–V GaN nanostructured channel (thickness of 10 nm); Al2O3 dielectric gate oxide based MOSFET is reported with a very low threshold voltage of 0.1 V and faster switching of the device.