Gotowe bibliografie tematyczne / Low-density parity-check Decoders

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Gotowa bibliografia na temat „Low-density parity-check Decoders”

Autor: Grafiati

Data publikacji: 6 września 2023

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Artykuły w czasopismach na temat "Low-density parity-check Decoders"

Mao, Yun, Ying Guo, Jun Peng, Xueqin Jiang i Moon Ho Lee. "Double-Layer Low-Density Parity-Check Codes over Multiple-Input Multiple-Output Channels". International Journal of Antennas and Propagation 2012 (2012): 1–6. http://dx.doi.org/10.1155/2012/716313.

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We introduce a double-layer code based on the combination of a low-density parity-check (LDPC) code with the multiple-input multiple-output (MIMO) system, where the decoding can be done in both inner-iteration and outer-iteration manners. The present code, called low-density MIMO code (LDMC), has a double-layer structure, that is, one layer defines subcodes that are embedded in each transmission vector and another glues these subcodes together. It supports inner iterations inside the LDPC decoder and outeriterations between detectors and decoders, simultaneously. It can also achieve the desired design rates due to the full rank of the deployed parity-check matrix. Simulations show that the LDMC performs favorably over the MIMO systems.

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Xia, Tian, Hsiao-Chun Wu i Hong Jiang. "New Stopping Criterion for Fast Low-Density Parity-Check Decoders". IEEE Communications Letters 18, nr 10 (październik 2014): 1679–82. http://dx.doi.org/10.1109/lcomm.2014.2349988.

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Djordjevic, Ivan B. "Photonic entanglement-assisted quantum low-density parity-check encoders and decoders". Optics Letters 35, nr 9 (30.04.2010): 1464. http://dx.doi.org/10.1364/ol.35.001464.

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Perez-Pascual, Asun, Alex Hamilton, Robert G. Maunder i Lajos Hanzo. "Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check Decoders". IEEE Access 6 (2018): 55741–53. http://dx.doi.org/10.1109/access.2018.2872113.

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Mohsenin, Tinoosh, i Bevan M. Baas. "A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders". Journal of Signal Processing Systems 61, nr 3 (26.02.2010): 329–45. http://dx.doi.org/10.1007/s11265-010-0456-y.

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Psota, Eric, i Lance C. Pérez. "The Manifestation of Stopping Sets and Absorbing Sets as Deviations on the Computation Trees of LDPC Codes". Journal of Electrical and Computer Engineering 2010 (2010): 1–17. http://dx.doi.org/10.1155/2010/432495.

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The error mechanisms of iterative message-passing decoders for low-density parity-check codes are studied. A tutorial review is given of the various graphical structures, including trapping sets, stopping sets, and absorbing sets that are frequently used to characterize the errors observed in simulations of iterative decoding of low-density parity-check codes. The connections between trapping sets and deviations on computation trees are explored in depth using the notion ofproblematictrapping sets in order to bridge the experimental and analytic approaches to these error mechanisms. A new iterative algorithm for finding low-weight problematic trapping sets is presented and shown to be capable of identifying many trapping sets that are frequently observed during iterative decoding of low-density parity-check codes on the additive white Gaussian noise channel. Finally, a new method is given for characterizing the weight of deviations that result from problematic trapping sets.

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Ismail, Mohamed, Imran Ahmed i Justin Coon. "Low Power Decoding of LDPC Codes". ISRN Sensor Networks 2013 (17.01.2013): 1–12. http://dx.doi.org/10.1155/2013/650740.

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Wireless sensor networks are used in many diverse application scenarios that require the network designer to trade off different factors. Two such factors of importance in many wireless sensor networks are communication reliability and battery life. This paper describes an efficient, low complexity, high throughput channel decoder suited to decoding low-density parity-check (LDPC) codes. LDPC codes have demonstrated excellent error-correcting ability such that a number of recent wireless standards have opted for their inclusion. Hardware realisation of practical LDPC decoders is a challenging area especially when power efficient solutions are needed. Implementation details are given for an LDPC decoding algorithm, termed adaptive threshold bit flipping (ATBF), designed for low complexity and low power operation. The ATBF decoder was implemented in 90 nm CMOS at 0.9 V using a standard cell design flow and was shown to operate at 250 MHz achieving a throughput of 252 Gb/s/iteration. The decoder area was 0.72 mm2 with a power consumption of 33.14 mW and a very small energy/decoded bit figure of 1.3 pJ.

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Wang, Biao. "Novel Early Termination Method of an ADMM-Penalized Decoder for LDPC Codes in the IoT". Security and Communication Networks 2022 (14.10.2022): 1–13. http://dx.doi.org/10.1155/2022/4599105.

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As a critical communication technology, low-density parity-check (LDPC) codes are widely concerned with the Internet of things (IoT). To increase the convergence rate of the alternating direction method of multiplier (ADMM)-penalized decoder for LDPC codes, a novel early termination (ET) method is presented by computing the average sum of the hard decision (ASHD) during each ADMM iteration. In terms of the flooding scheduling and layered scheduling ADMM-penalized decoders, the simulation results show that the proposed ET method can significantly reduce the average number of iterations at low signal-to-noise ratios (SNRs) with negligible decoding performance loss.

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Stark, Maximilian, Jan Lewandowsky i Gerhard Bauch. "Information-Bottleneck Decoding of High-Rate Irregular LDPC Codes for Optical Communication Using Message Alignment". Applied Sciences 8, nr 10 (11.10.2018): 1884. http://dx.doi.org/10.3390/app8101884.

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In high-throughput applications, low-complexity and low-latency channel decoders are inevitable. Hence, for low-density parity-check (LDPC) codes, message passing decoding has to be implemented with coarse quantization—that is, the exchanged beliefs are quantized with a small number of bits. This can result in a significant performance degradation with respect to decoding with high-precision messages. Recently, so-called information-bottleneck decoders were proposed which leverage a machine learning framework (i.e., the information bottleneck method) to design coarse-precision decoders with error-correction performance close to high-precision belief-propagation decoding. In these decoders, all conventional arithmetic operations are replaced by look-up operations. Irregular LDPC codes for next-generation fiber optical communication systems are characterized by high code rates and large maximum node degrees. Consequently, the implementation complexity is mainly influenced by the memory required to store the look-up tables. In this paper, we show that the complexity of information-bottleneck decoders remains manageable for irregular LDPC codes if our proposed construction approach is deployed. Furthermore, we reveal that in order to design information bottleneck decoders for arbitrary degree distributions, an intermediate construction step which we call message alignment has to be included. Exemplary numerical simulations show that incorporating message alignment in the construction yields a 4-bit information bottleneck decoder which performs only 0.15 dB worse than a double-precision belief propagation decoder and outperforms a min-sum decoder.

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Dinh, The Cuong, Huyen Pham Thi, Hung Dao Tuan i Nghia Pham Xuan. "ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE". Journal of Computer Science and Cybernetics 37, nr 2 (31.05.2021): 91–106. http://dx.doi.org/10.15625/1813-9663/37/2/15917.

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Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, an One-Minimum-Only basic-set trellis min-max (OMO-BS-TMM) algorithm and the corresponding decoder architecture are proposed for NBLDPC codes to greatly reduce the complexity of the check node unit (CNU) as well as the whole decoder. In the proposed OMO-BS-TMM algorithm, only the first minimum values are used for generating the check node messages instead of using both the first and second minimum values, and the number of messages exchanged between the check node and the variable node is reduced in comparison with the previous works. Layered decoder architectures based on the proposed algorithm were implemented for the (837, 726) NB-LDPC code over GF(32) using 90-nm CMOS technology. The implementation results showed that the OMO-BS-TMM algorithm achieves the almost similar error-correcting performance, and a reduction of the complexity by 31.8% and 20.5% for the whole decoder, compared to previous works. Moreover, the proposed decoder achieves a higher throughput at 1.4 Gbps, compared with the other state-of-the-art NBLDPC decoders.

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Rozprawy doktorskie na temat "Low-density parity-check Decoders"

Planjery, Shiva Kumar. "Low-Complexity Finite Precision Decoders for Low-Density Parity-Check Codes". International Foundation for Telemetering, 2010. http://hdl.handle.net/10150/605947.

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ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, California
We present a new class of finite-precision decoders for low-density parity-check (LDPC) codes. These decoders are much lower in complexity compared to conventional floating-point decoders such as the belief propagation (BP) decoder, but they have the potential to outperform BP. The messages utilized by the decoders assume values (or levels) from a finite discrete set. We discuss the implementation aspects as well as describe the underlying philosophy in designing these decoders. We also provide results to show that in some cases, only 3 bits are required in the proposed decoders to outperform floating-point BP.

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Vijayakumar, Suresh Mikler Armin. "FPGA implementation of low density parity check codes decoder". [Denton, Tex.] : University of North Texas, 2009. http://digital.library.unt.edu/permalink/meta-dc-11003.

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Yang, Lei. "VLSI implementation of low-error-floor multi-rate capacity-approaching low-density parity-check code decoder /". Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/5966.

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Blad, Anton. "Low Complexity Techniques for Low Density Parity Check Code Decoders and Parallel Sigma-Delta ADC Structures". Doctoral thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-69432.

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Since their rediscovery in 1995, low-density parity-check (LDPC) codes have received wide-spread attention as practical capacity-approaching code candidates. It has been shown that the class of codes can perform arbitrarily close to the channel capacity, and LDPC codes are also used or suggested for a number of important current and future communication standards. However, the problem of implementing an energy-efficient decoder has not yet been solved. Whereas the decoding algorithm is computationally simple, with uncomplicated arithmetic operations and low accuracy requirements, the random structure and irregularity of a theoretically well-defined code does not easily allow efficient VLSI implementations. Thus the LDPC decoding algorithm can be said to be communication-bound rather than computation-bound. In this thesis, a modification to the sum-product decoding algorithm called earlydecision decoding is suggested. The modification is based on the idea that the values of the bits in a block can be decided individually during decoding. As the sumproduct decoding algorithm is a soft-decision decoder, a reliability can be defined for each bit. When the reliability of a bit is above a certain threshold, the bit can be removed from the rest of the decoding process, and thus the internal communication associated with the bit can be removed in subsequent iterations. However, with the early decision modification, an increased error probability is associated. Thus, bounds on the achievable performance as well as methods to detect graph inconsistencies resulting from erroneous decisions are presented. Also, a hybrid decoder achieving a negligible performance penalty compared to the sum-product decoder is presented. With the hybrid decoder, the internal communication is reduced with up to 40% for a rate-1/2 code with a length of 1152 bits, whereas increasing the rate allows significantly higher gains. The algorithms have been implemented in a Xilinx Virtex 5 FPGA, and the resulting slice utilization and energy dissipation have been estimated. However, due to increased logic overhead of the early decision decoder, the slice utilization increases from 14.5% to 21.0%, whereas the logic energy dissipation reduction from 499 pJ to 291 pJ per iteration and bit is offset by the clock distribution power, increased from 141 pJ to 191 pJ per iteration and bit. Still, the early decision decoder shows a net 16% estimated decrease of energy dissipation.

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Gunnam, Kiran Kumar. "Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation". [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1049.

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Selvarathinam, Anand Manivannan. "High throughput low power decoder architectures for low density parity check codes". Texas A&M University, 2005. http://hdl.handle.net/1969.1/2529.

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A high throughput scalable decoder architecture, a tiling approach to reduce the complexity of the scalable architecture, and two low power decoding schemes have been proposed in this research. The proposed scalable design is generated from a serial architecture by scaling the combinational logic; memory partitioning and constructing a novel H matrix to make parallelization possible. The scalable architecture achieves a high throughput for higher values of the parallelization factor M. The switch logic used to route the bit nodes to the appropriate checks is an important constituent of the scalable architecture and its complexity is high with higher M. The proposed tiling approach is applied to the scalable architecture to simplify the switch logic and reduce gate complexity. The tiling approach generates patterns that are used to construct the H matrix by repeating a fixed number of those generated patterns. The advantages of the proposed approach are two-fold. First, the information stored about the H matrix is reduced by onethird. Second, the switch logic of the scalable architecture is simplified. The H matrix information is also embedded in the switch and no external memory is needed to store the H matrix. Scalable architecture and tiling approach are proposed at the architectural level of the LDPC decoder. We propose two low power decoding schemes that take advantage of the distribution of errors in the received packets. Both schemes use a hard iteration after a fixed number of soft iterations. The dynamic scheme performs X soft iterations, then a parity checker cHT that computes the number of parity checks in error. Based on cHT value, the decoder decides on performing either soft iterations or a hard iteration. The advantage of the hard iteration is so significant that the second low power scheme performs a fixed number of iterations followed by a hard iteration. To compensate the bit error rate performance, the number of soft iterations in this case is higher than that of those performed before cHT in the first scheme.

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Zhang, Kai. "High-Performance Decoder Architectures For Low-Density Parity-Check Codes". Digital WPI, 2012. https://digitalcommons.wpi.edu/etd-dissertations/17.

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The Low-Density Parity-Check (LDPC) codes, which were invented by Gallager back in 1960s, have attracted considerable attentions recently. Compared with other error correction codes, LDPC codes are well suited for wireless, optical, and magnetic recording systems due to their near- Shannon-limit error-correcting capacity, high intrinsic parallelism and high-throughput potentials. With these remarkable characteristics, LDPC codes have been adopted in several recent communication standards such as 802.11n (Wi-Fi), 802.16e (WiMax), 802.15.3c (WPAN), DVB-S2 and CMMB. This dissertation is devoted to exploring efficient VLSI architectures for high-performance LDPC decoders and LDPC-like detectors in sparse inter-symbol interference (ISI) channels. The performance of an LDPC decoder is mainly evaluated by area efficiency, error-correcting capability, throughput and rate flexibility. With this work we investigate tradeoffs between the four performance aspects and develop several decoder architectures to improve one or several performance aspects while maintaining acceptable values for other aspects. Firstly, we present a high-throughput decoder design for the Quasi-Cyclic (QC) LDPC codes. Two new techniques are proposed for the first time, including parallel layered decoding architecture (PLDA) and critical path splitting. Parallel layered decoding architecture enables parallel processing for all layers by establishing dedicated message passing paths among them. The decoder avoids crossbar-based large interconnect network. Critical path splitting technique is based on articulate adjustment of the starting point of each layer to maximize the time intervals between adjacent layers, such that the critical path delay can be split into pipeline stages. Furthermore, min-sum and loosely coupled algorithms are employed for area efficiency. As a case study, a rate-1/2 2304-bit irregular LDPC decoder is implemented using ASIC design in 90 nm CMOS process. The decoder can achieve an input throughput of 1.1 Gbps, that is, 3 or 4 times improvement over state-of-art LDPC decoders, while maintaining a comparable chip size of 2.9 mm^2. Secondly, we present a high-throughput decoder architecture for rate-compatible (RC) LDPC codes which supports arbitrary code rates between the rate of mother code and 1. While the original PLDA is lack of rate flexibility, the problem is solved gracefully by incorporating the puncturing scheme. Simulation results show that our selected puncturing scheme only introduces the BER performance degradation of less than 0.2dB, compared with the dedicated codes for different rates specified in the IEEE 802.16e (WiMax) standard. Subsequently, PLDA is employed for high throughput decoder design. As a case study, a RC- LDPC decoder based on the rate-1/2 WiMax LDPC code is implemented in CMOS 90 nm process. The decoder can achieve an input throughput of 975 Mbps and supports any rate between 1/2 and 1. Thirdly, we develop a low-complexity VLSI architecture and implementation for LDPC decoder used in China Multimedia Mobile Broadcasting (CMMB) systems. An area-efficient layered decoding architecture based on min-sum algorithm is incorporated in the design. A novel split-memory architecture is developed to efficiently handle the weight-2 submatrices that are rarely seen in conventional LDPC decoders. In addition, the check-node processing unit is highly optimized to minimize complexity and computing latency while facilitating a reconfigurable decoding core. Finally, we propose an LDPC-decoder-like channel detector for sparse ISI channels using belief propagation (BP). The BP-based detection computationally depends on the number of nonzero interferers only and are thus more suited for sparse ISI channels which are characterized by long delay but a small fraction of nonzero interferers. Layered decoding algorithm, which is popular in LDPC decoding, is also adopted in this paper. Simulation results show that the layered decoding doubles the convergence speed of the iterative belief propagation process. Exploring the special structure of the connections between the check nodes and the variable nodes on the factor graph, we propose an effective detector architecture for generic sparse ISI channels to facilitate the practical application of the proposed detection algorithm. The proposed architecture is also reconfigurable in order to switch flexible connections on the factor graph in the time-varying ISI channels.

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Kopparthi, Sunitha. "Flexible encoder and decoder designs for low-density parity-check codes". Diss., Manhattan, Kan. : Kansas State University, 2010. http://hdl.handle.net/2097/4190.

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Hussein, Ahmed Refaey Ahmed. "Universal Decoder for Low Density Parity Check, Turbo and Convolutional Codes". Thesis, Université Laval, 2011. http://www.theses.ulaval.ca/2011/28154/28154.pdf.

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Cai, Fang. "Efficient VLSI Architectures for Non-binary Low Density Parity Check Decoding". Case Western Reserve University School of Graduate Studies / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1300821245.

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Streszczenia konferencji na temat "Low-density parity-check Decoders"

Zhang, Z., L. Dolecek, M. Wainwright, V. Anantharam i B. Nikolic. "Quantization Effects in Low-Density Parity-Check Decoders". W 2007 IEEE International Conference on Communications. IEEE, 2007. http://dx.doi.org/10.1109/icc.2007.1032.

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Chung, Cha-Hao, Yeong-Luh Ueng, Ming-Che Lu i Mao-Chao Lin. "Adaptive quantization for low-density-parity-check decoders". W Its Applications (Isita2010). IEEE, 2010. http://dx.doi.org/10.1109/isita.2010.5649830.

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Balatsoukas-Stimming, Alexios, Pascal Giard i Andreas Burg. "Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders". W 2017 IEEE Wireless Communications and Networking Conference Workshops (WCNCW). IEEE, 2017. http://dx.doi.org/10.1109/wcncw.2017.7919106.

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Li, Bohua, Yukui Pei i Ning Ge. "Area-Efficient Fault-Tolerant Design for Low-Density Parity-Check Decoders". W 2016 IEEE 84th Vehicular Technology Conference (VTC-Fall). IEEE, 2016. http://dx.doi.org/10.1109/vtcfall.2016.7880909.

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Tian Xia, Hsiao-Chun Wu i Scott C.-H. Huang. "A new stopping criterion for fast low-density parity-check decoders". W 2013 IEEE Global Communications Conference (GLOBECOM 2013). IEEE, 2013. http://dx.doi.org/10.1109/glocom.2013.6831642.

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Ratnayake, Ruwan N. S., Erich F. Haratsch i Gu-Yeon Wei. "A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders". W IEEE GLOBECOM 2007-2007 IEEE Global Telecommunications Conference. IEEE, 2007. http://dx.doi.org/10.1109/glocom.2007.57.

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Porcello, John C. "Designing and implementing Low Density Parity Check (LDPC) Decoders using FPGAs". W 2014 IEEE Aerospace Conference. IEEE, 2014. http://dx.doi.org/10.1109/aero.2014.6836261.

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Djordjevic, Ivan B. "Cavity quantum electrodynamics based quantum low-density parity-check encoders and decoders". W SPIE OPTO, redaktorzy Zameer U. Hasan, Philip R. Hemmer, Hwang Lee i Charles M. Santori. SPIE, 2011. http://dx.doi.org/10.1117/12.873975.

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Yin, Dawei, Yuan Liy, Xianbin Wang, Jiajie Tong, Huazi Zhang, Jun Wang, Guanghui Wang, Guiying Yan i Zhiming Ma. "On the Message Passing Efficiency of Polar and Low-Density Parity-Check Decoders". W 2022 IEEE Globecom Workshops (GC Wkshps). IEEE, 2022. http://dx.doi.org/10.1109/gcwkshps56602.2022.10008677.

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Aziz, Syed Mahfuzul, i Sunil Sharma. "New methodologies for high level modeling and synthesis of low density parity check decoders". W 2008 11th International Conference on Computer and Information Technology (ICCIT). IEEE, 2008. http://dx.doi.org/10.1109/iccitechn.2008.4803046.

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