Rozprawy doktorskie: „LNA CIRCUIT”

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Yu, Chuanzhao. "STUDY OF NANOSCALE CMOS DEVICE AND CIRCUIT RELIABILITY". Doctoral diss., University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3551.

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The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices – low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices – from device level to circuit level; The more real voltage stress case – high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future.
Ph.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering

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Green, Matthew Richard. "Development of a temperature insensitive current controlled current source for LNA bias circuit applications". Thesis, Oxford Brookes University, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.444330.

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The research described in this thesis is concerned with the analysis, design and development of a novel temperature insensitive Current Controlled Current Source (CCCS), in bipolar technology, in order to provide accurate amplification of a Proportional To Absolute Temperature (PTAT) reference current. The output current of the CCCS is intended for application as the bias current for a bipolar Low Noise Amplifier (LNA) in order to minimise gain variations with temperature across the industrial temperature range (-40·C to 8S·C). The thesis begins with an explanation of key parameters concerned with LNA design and a target specification is defined. In Chapter 2, a conventional LNA, with constant with temperature bias current, is developed following a methodical approach based on conventional techniques. This meets the previously defined specification at room temperature but exhibits large gain variations with changes in temperature. The analysis and simulation results of this conventional LNA serve as a benchmark for comparison with later designs. In order to minimise any gain variations with temperature of a bipolar amplifier it is well known that the applied bias current should be PT AT. Thus, a thorough analysis and comparative review of traditional and novel PTAT reference current generator circuits is conducted in Chapters 3 and 4. Based on these findings the PTAT generator exhibiting best performance in terms of output current accuracy and insensitivity to power supply variations is presented. However, this circuit cannot accurately produce large rnA level currents necessary for LNA bias applications so that sufficient linearity of the LNA is maintained. Thus, a need for some form of accurate CCCS or Voltage Controlled Current Source (VCCS), which should be temperature insensitive in order to preserve the desired temperature coefficient of the reference current/voltage, is highlighted.Traditional VCCS/CCCS designs are investigated in Chapter 5. Limitations of these approaches leads to the design and development ofa novel CCCS with built in PTAT reference. The presented CCCS utilises a new, previously unseen, architecture and has led to a patent application [1]. The author has reported the majority of this work in technical literature [2-4]. In Chapter 6, the output of the novel CCCS is adapted to include the conventional LNA circuit designed previously in Chapter 2. The results of the combined LNA and CCCS are compared with the conventional LNA. The combined LNA and CCCS offers a dramatic reduction in gain variation with temperature.

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Costa, Arthur Liraneto Torres. "Inductorless balun low-noise amplifier (LNA) for RF wideband application to IEEE 802.22". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/106442.

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Um novo circuito amplificador de 50 MHz - 1 GHz com alta linearidade para o padrão IEEE 802.22 “wireless regional area” (WRAN) é apresentado. Ele foi implementado sem nenhum indutor e oferece uma saída diferencial para ser utilizada como balun. Técnicas de cancelamento de ruído e aumento de linearidade foram usadas para melhorar a performace do amplificador de modo que eles pudessem ser otimizados separadamente. A linearidade foi melhorada utilizando transistores conectados como diodo. O amplificador foi implementado em um processo CMOS 130 nm, em uma área compacta de 136 m x 71 m. As simulações são apresentadas para esquemáticos pós-leiaute para duas classes diferentes de projeto: um visando a melhor linearidade e o outro a melhor Figura de Ruído (FR). Quando otimizado para melhor linearidade, os resultados de simulação atingem um ganho de tensão > 23.7 dB (ganho de potência > 19.1 dB), uma figura de ruído < 3.6 dB na banda inteira (com 2.4 dB min), um ponto de intersecção de terceira ordem (IIP3) > 3.3 dBm (7.6 dBm max) e um coeficiente de reflexão de entrada S11 < -16 dB. Quando otimizado para melhor figura de ruído, ele atinge um ganho de tensão > 24.7 dB (ganho de potência > 19.8 dB), uma FR < 2 dB na banda inteira, um IIP3 > -0.3 dBm e um S11 < -11 dB. Resultados de simulação Monte Carlo confirmam baixa sensibilidade à variabilidade de processo. Além disso, uma baixa sensibilidade com a temperatura na faixa de -55 até 125 C foi observada para Ganho, FR e S11. Consumo de potência é 17.6 mA sob fonte de alimentação de 1.2 V.
A new 50 MHz - 1 GHz low-noise amplifier circuit with high linearity for IEEE 802.22 wireless regional area network (WRAN) is presented. It was implemented without any inductor and offers a differential output for balun use. Noise cancelling and linearity boosting techniques were used to improve the amplifier performance in a way they can be separately optimized. Linearity was improved using diode-connected transistors. The amplifier was implemented in a 130 nm CMOS process in a compact 136 m x 71 m area. Simulations are presented for post-layout schematics for two classes of design: one for best linearity, another for best noise figure (NF). When optimized for best linearity, simulation results achieve a voltage gain > 23.7 dB (power gain > 19.1 dB), a NF < 3.6 dB over the entire band (with 2.4 dB min figure), an input third-order intercept point (IIP3) > 3.3 dBm (7.6 dBm max.) and an input power reflection coefficient S11 < -16 dB. When optimized for best NF, it achieves a voltage gain > 24.7 dB (power gain > 19.8 dB), a NF < 2 dB over the entire band, an IIP3 > -0.3 dBm and an S11 < -11 dB. Monte Carlo simulation results confirm low sensitivity to process variations. Also a low sensitivity to temperature within the range -55 to 125 C was observed for Gain, NF and S11. Power consumption is 17.6 mA under a 1.2 V supply.

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yasami, saeed. "Design and Evaluation of an Ultra-Low PowerLow Noise Amplifier LNA". Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-50923.

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This master thesis deals with the study of ultra low power Low Noise Amplifier (LNA) for use inmedical implant device. Usually, low power consumption is required for a long battery lifetime andlonger operation. The target technology is 90nm CMOS process.First basic principle of LNA is discussed. Then based on a literature review of LNA design, theproposed LNA is presented in sub-threshold region which reduce power consumption through scalingthe supply voltage and through scaling current.The circuit implementation and simulations is presented to testify the performance of LNA .Besides thepower consumption simulated under the typical supply voltage (1V), it is also measured under someother low supply voltages (down to 0.5V) to investigate the minimum power consumption and theminimum noise figure. Evaluation results show that at a supply voltage of 1V the LNA performs a totalpower consumption of 20mW and a noise of 1dB. Proper performance is achieved with a current ofdown to 200uA and supply voltage of down to 0.45V, and a total power consumption of 200uW

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Janse, van Rensburg Christo. "A SiGe BiCMOS LNA for mm-wave applications". Diss., University of Pretoria, 2012. http://hdl.handle.net/2263/26501.

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A 5 GHz continuous unlicensed bandwidth is available at millimeter-wave (mm-wave) frequencies around 60 GHz and offers the prospect for multi gigabit wireless applications. The inherent atmospheric attenuation at 60 GHz due to oxygen absorption makes the frequency range ideal for short distance communication networks. For these mm-wave wireless networks, the low noise amplifier (LNA) is a critical subsystem determining the receiver performance i.e., the noise figure (NF) and receiver sensitivity. It however proves challenging to realise high performance mm-wave LNAs in a silicon (Si) complementary metal-oxide semiconductor (CMOS) technology. The mm-wave passive devices, specifically on-chip inductors, experience high propagation loss due to the conductivity of the Si substrate at mm-wave frequencies, degrading the performance of the LNA and subsequently the performance of the receiver architecture. The research is aimed at realising a high performance mm-wave LNA in a Si BiCMOS technology. The focal points are firstly, the fundamental understanding of the various forms of losses passive inductors experience and the techniques to address these issues, and secondly, whether the performance of mm-wave passive inductors can be improved by means of geometry optimising. An associated hypothesis is formulated, where the research outcome results in a preferred passive inductor and formulates an optimised passive inductor for mm-wave applications. The performance of the mm-wave inductor is evaluated using the quality factor (Q-factor) as a figure of merit. An increased inductor Q-factor translates to improved LNA input and output matching performance and contributes to the lowering of the LNA NF. The passive inductors are designed and simulated in a 2.5D electromagnetic (EM) simulator. The electrical characteristics of the passive structures are exported to a SPICE netlist which is included in a circuit simulator to evaluate and investigate the LNA performance. Two LNAs are designed and prototyped using the 13μ-m SiGe BiCMOS process from IBM as part of the experimental process to validate the hypothesis. One LNA implements the preferred inductor structures as a benchmark, while the second LNA, identical to the first, replaces one inductor with the optimised inductor. Experimental verification allows complete characterization of the passive inductors and the performance of the LNAs to prove the hypothesis. According to the author's knowledge, the slow-wave coplanar waveguide (S-CPW) achieves a higher Q-factor than microstrip and coplanar waveguide (CPW) transmission lines at mm-wave frequencies implemented for the 130 nm SiGe BiCMOS technology node. In literature, specific S-CPW transmission line geometry parameters have previously been investigated, but this work optimises the signal-to-ground spacing of the S-CPW transmission lines without changing the characteristic impedance of the lines. Optimising the S-CPW transmission line for 60 GHz increases the Q-factor from 38 to 50 in simulation, a 32 % improvement, and from 8 to 10 in measurements. Furthermore, replacing only one inductor in the output matching network of the LNA with the higher Q-factor inductor, improves the input and output matching performance of the LNA, resulting in a 5 dB input and output reflection coefficient improvement. Although a 5 dB improvement in matching performance is obtained, the resultant noise and gain performance show no significant improvement. The single stage LNAs achieve a simulated gain and NF of 13 dB and 5.3 dB respectively, and dissipate 6 mW from the 1.5 V supply. The LNA focused to attain high gain and a low NF, trading off linearity and as a result obtained poor 1 dB compression of -21.7 dBm. The LNA results are not state of the art but are comparable to SiGe BiCMOS LNAs presented in literature, achieving similar gain, NF and power dissipation figures.
Dissertation (MEng)--University of Pretoria, 2012.
Electrical, Electronic and Computer Engineering
unrestricted

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Gong, Fei. "Front End Circuit Module Designs for A Digitally Controlled Channelized SDR Receiver Architecture". The Ohio State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=osu1322606039.

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De, Sousa Marinho Rafael. "Co-design methodology of 60 GHz filter-L-NA". Thesis, Limoges, 2019. http://www.theses.fr/2019LIMO0095.

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Ce travail montre les résultats et discussions à propos du projet partagé des structures pour un récepteur radio-fréquence des ondes millimétriques. Deux structures ont été étudiés : Le LNA et le résonateur en anneau. Ces structures ont été développes en utilisant des nouvelles techniques de projet de circuit micro-électroniques et utilisation des outils CAD.Les circuit ont été fabriqués avec la technologie QuBIC NXP®BiCMOS SiGe:C de 0.25μm.Les résultats de mesure sont en conformité avec l’état de l’art pour des LNA
This work presents the results and discussions about shared design (co-design)of structures for a RF receptor in millimetric waves. Two structures were mainly studied: TheLNA and the resonator filter. Both structures were developed using novel microelectronic circuitdesign techniques and with the extensive use of CAD software. The circuits were fabricatedusing a0.25μmBiCMOS SiGe:C QuBIC technology from NXP®semiconductors, and themeasurement results are in conformity with the state-of-the-art

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Thrivikraman, Tushar. "Analysis and Design of Low-Noise Amplifiers in Silicon-Germanium Hetrojunction Bipolar Technology for Radar and Communication Systems". Thesis, Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19755.

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This thesis presents an overview of the simulation, design, and measurement of state-of-the-art Silicon-Germanium Hetro-Junction Bipolar Transistor (SiGe HBT) low-noise amplifiers (LNAs). The LNA design trade-off space is presented and methods for achieving an optimized design are discussed. In Chapter 1, we review the importance of LNAs and the benefits of SiGe HBT technology in high frequency amplifier design. Chapter 2 introduces LNA design and basic noise theory. A graphical LNA design approach is presented to aid in understanding of the high-frequency LNA design process. Chapter 3 presents an LNA design optimization method for power constrained applications. Measured results using this design technique are highlighted and shown to have record performance. Lastly, in Chapter 4, we highlight cryogenic noise performance and present measured results from cryogenic operation of SiGe HBT LNAs. We demonstrate in this thesis that SiGe HBT LNAs have the capability to meet the demanding needs for next generation wireless systems. The aim of the analysis presented herein is to provide designers with the fundamentals of designing SiGe HBT LNAs through relevant design examples and measured results.

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Poh, Chung Hang. "Radio frequency circuit design and packaging for silicon-germanium hetrojunction bipolar technology". Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31662.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: Cressler, John; Committee Member: Laskar, Joy; Committee Member: Papapolymerou, John. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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Gaubert, Jean. "Contribution à l'étude d'interfaces analogiques hautes fréquences pour objets communicants à faible coût de fabrication". Habilitation à diriger des recherches, Université de Provence - Aix-Marseille I, 2007. http://tel.archives-ouvertes.fr/tel-00796512.

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Le premier chapitre de ce mémoire intitulé "Amplificateurs faible bruit accordés pour systèmes intégrés CMOS" s'intéresse aux méthodes de conception permettant l'intégration complète de l'amplificateur faible bruit d'une (LNA) depuis la gamme des radiofréquences jusqu'à la gamme des fréquences millimétriques. Ces travaux ont été menés dans le cadre de la Thèse de Mathieu Egels et dans le cadre d'une convention de recherche avec la société ST-Microélectronics financée par le Conseil Général des Bouches du Rhône. Le deuxième chapitre est intitulé "Amplificateurs bas niveau large bande pour systèmes intégrés CMOS". Ce chapitre présente les solutions que nous avons développées au laboratoire qui permettent de contrôler la bande passante des amplificateurs faible bruit pour systèmes intégrés destinés aux applications utilisant les normes UWB ainsi que des études plus prospectives sur l'amplification distribuée CMOS pour des applications à très grandes bandes passantes. Dans la dernière partie de ce chapitre nous décrivons nos travaux concernant la mise en boîtier des circuits et systèmes intégrés haute fréquence et large bande. Ces différents travaux ont été réalisés d'une part dans le cadre des Thèses de Mathieu Egels, et de Marc Battista, dans le cadre d'une convention de recherche avec la société ST-Microélectronics financée par le Conseil Général des Bouches du Rhône, et d'autre part dans le cadre de la thèse de Romen Cubillo avec le soutien de la plateforme conception du Centre Intégré de Microélectronique de la région PACA (CIMPACA). Le troisième chapitre "Convertisseurs RF/DC pour la téléalimentation haute fréquence en RFID" décrit nos activités de recherche concernant les circuits et architectures pour la télé-alimentation des circuits intégrés au moyen d'une onde électromagnétique. Les applications ciblées concernent essentiellement les étiquettes électroniques sans contact dans le domaine des fréquences UHF pour lesquelles nous avons développé des circuits et des architectures pour les technologies CMOS standard. Ces travaux ont été réalisés dans le cadre de la Thèse de Emmanuel Bergeret dans le cadre d'une convention de recherche avec la société ST-Microélectronics soutenue par le Conseil Général des Bouches du Rhône. Dans ce mémoire nous nous attacherons à décrire l'état de l'art des différents thèmes de recherche abordés et à situer nos travaux vis-à-vis de cet état de l'art. Le détail de nos travaux de recherche étant disponible dans les différents articles et thèses référencés, nous donnerons dans ce mémoire uniquement les grandes lignes de nos études et les principaux résultats obtenus.

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Johnson, Daniel Austin. "5-6 GHz RFIC Front-End Components in Silicon Germanium HBT Technology". Thesis, Virginia Tech, 2001. http://hdl.handle.net/10919/32356.

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In 1997 the Federal Communications Commission (FCC) released 300 MHz of spectrum between 5-6 GHz designated the unlicensed national information infrastructure (U-NII) band. The intention of the FCC was to provide an unlicensed band of frequencies that would enable high-speed wireless local area networks (WLANs) and facilitate wireless access to the national information infrastructure with a minimum interference to other devices. Currently, there is a lack of cost-effective technologies for developing U-NII band components. With the commercial market placing emphasis on low cost, low power, and highly integrated implementations of RF circuitry, alternatives to the large and expensive distributed element components historically used at these frequencies are needed. Silicon Germanium (SiGe) BiCMOS technology represents one possible solution to this problem. The SiGe BiCMOS process has the potential for low cost since it leverages mature Si process technologies and can use existing Si fabrication infrastructure. In addition, SiGe BiCMOS processes offer excellent high frequency performance through the use of SiGe heterojunction bipolar transistors (HBTs), while coexisting Si CMOS offers compatibility with digital circuitry for high level 'system-on-a-chip' integration. The work presented in this thesis focuses on the development of a SiGe RFIC front-end for operation in the U-NII bands. Specifically, three variants of a packaged low noise amplifier (LNA) and a packaged active x2 sub-harmonic mixer (SHM) have been designed, simulated and measured. The fabrication of the Rifts was through the IBM SiGe foundry; the packaging was performed by RF Micro devices. The mixer and LNA designs were fabricated on separate die, packaged individually, and on-chip matched to a 50 ohm system so they could be fully characterized. Measurements were facilitated in a coaxial system using standard FR4 printed circuit boards. The LNA designs use a single stage, cascoded topology. The input ports are impedance matched using inductive emitter degeneration through bondwires to ground. One version of the LNA uses an shunt inductor/series capacitor output match while the other two variation use a series inductor output match. Gain, isolation, match, linearity and noise figure (NF) were used to characterize the performance of the LNAs in the 5 - 6 GHz frequency band. The best LNA design has a maximum gain of 9 dB, an input VSWR between 1.6:1 and 2:1, an output match between 1.7:1 and 3.6:1, a NF better than 3.9 dB and an input intercept point (IIP3) greater than 5.4 dBm. The LNA operates from a 3.3 V supply voltage and consumes 4 mA of current. The SHM is an active, double-balance mixer that achieves x2 sub-harmonic mixing through two quadrature (I/Q) driven, stacked Gilbert-cell switching stages. Single-ended-to-differential conversion, buffering and I/Q phase separation of the LO signal are integrated on-chip. Measurements were performed to find the optimal operating range for the mixer, and the mixer was characterized under these sets of conditions. It was found that the optimal performance of the mixer occurs at an IF of 250-450 MHz and an LO power of -5 dBm. Under these conditions, the mixer has a measured conversion gain of 9.3 dB, a P_1-dB of -15.7 dBm and an 2LO/RF isolation greater than 35 dB at 5.25 GHz. At 5.775 GHz, the conversion gain is 7.7 dB, the P_1-dB is -15.0 dBm, and the isolation is greater than 35 dB. The mixer core consumes 9.5 mA from a 5.0 V supply voltage. This work is sponsored by RF Microdevices (RFMD)through the CWT a liate program.The author was supported under a Bradley Foundation fellowship.
Master of Science

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Chen, Tingsu. "CMOS High Frequency Circuits for Spin Torque Oscillator Technology". Licentiate thesis, KTH, Integrerade komponenter och kretsar, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-139588.

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Spin torque oscillator (STO) technology has a unique blend of features, including but not limited to octave tunability, GHz operating frequency, and nanoscaled size, which makes it highly suitable for microwave and radar applications. This thesis studies the fundamentals of STOs, utilizes the state-of-art STO's advantages, and proposes two STO-based microwave systems targeting its microwave applications and measurement setup, respectively. First, based on an investigation of possible STO applications, the magnetic tunnel junction (MTJ) STO shows a great suitability for microwave oscillator in multi-standard multi-band radios. Yet, it also imposes a large challenge due to its low output power, which limits it from being used as a microwave oscillator. In this regard, different power enhancement approaches are investigated to achieve an MTJ STO-based microwave oscillator. The only possible approach is to use a dedicated CMOS wideband amplifier to boost the output power of the MTJ STO. The dedicated wideband amplifier, containing a novel Balun-LNA, an amplification stage and an output buffer, is proposed, analyzed, implemented, measured and used to achieve the MTJ STO-based microwave oscillator. The proposed amplifier core consumes 25.44 mW from a 1.2 V power supply and occupies an area of 0.16 mm2 in a 65 nm CMOS process. The measurement results show a S21 of 35 dB, maximum NF of 5 dB, bandwidth of 2 GHz - 7 GHz. This performance, as well as the measurement results of the proposed MTJ STO-based microwave oscillator, show that this microwave oscillator has a highly-tunable range and is able to drive a PLL. The second aspect of this thesis, firstly identifies the major difficulties in measuring the giant magnetoresistance (GMR) STO, and hence studying its dynamic properties. Thereafter, the system architecture of a reliable GMR STO measurement setup, which integrates the GMR STO with a dedicated CMOS high frequency IC to overcome these difficulties in precise characterization of GMR STOs, is proposed. An analysis of integration methods is given and the integration method based on wire bonding is evaluated and employed, as a first integration attempt of STO and CMOS technologies. Moreover, a dedicated high frequency CMOS IC, which is composed of a dedicated on-chip bias-tee, ESD diodes, input and output networks, and an amplification stage for amplifying the weak signal generated by the GMR STO, is proposed, analyzed, developed, implemented and measured. The proposed dedicated high frequency circuits for GMR STO consumes 14.3 mW from a 1.2 V power supply and takes a total area of 0.329 mm2 in a 65 nm CMOS process. The proposed on-chip bias-tee presents a maximum measured S12 of -20 dB and a current handling of about 25 mA. Additionally, the proposed dedicated IC gives a measured gain of 13 dB with a bandwidth of 12.5 GHz - 14.5 GHz. The first attempt to measure the (GMR STO+IC) pair presents no RF signal at the output. The possible cause and other identified issues are given.

QC 20140114

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VIJAY, VIKAS. "A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS". University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283.

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Tartarin, Jean-Guy. "LE BRUIT DE FOND ÉLECTRIQUE DANS LES COMPOSANTS ACTIFS, CIRCUITS ET SYSTÈMES DES HAUTES FRÉQUENCES : DES CAUSES VERS LES EFFETS". Habilitation à diriger des recherches, Université Paul Sabatier - Toulouse III, 2009. http://tel.archives-ouvertes.fr/tel-00539034.

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Les travaux présentés dans ce mémoire d'habilitation portent sur l'impact du bruit de fond électrique sur les technologies des composants actifs, les circuits et les systèmes des hautes fréquences. Durant nos 12 dernières années de recherche, nous nous sommes notamment intéressés à des filières émergentes à fort potentiel d'intégration (BiCMOS Silicium-Germanium) ou encore à forte puissance (GaN) : nous avons ainsi développé des modèles électriques (petit signal et fort signal) et en bruit (basse fréquence et haute fréquence) des composants actifs pour identifier les pistes d'améliorations technologiques, pour localiser les défauts structurels ou pour étudier le comportement de ces mêmes défauts après l'application de contraintes simulant un vieillissement accéléré. Sur la base de la connaissance des composants actifs (transistor bipolaire à hétérojonction et transistors à effet de champ), nous avons développé des circuits intégrés MMIC faible bruit à 10 GHz et 20 GHz (amplificateurs et oscillateurs) dont certains se positionnent à l'état de l'art : des comparaisons de topologies ont notamment été réalisées sur différentes versions intégrées d'oscillateurs contrôlés en tension de type MMIC SiGe. Nous proposons également une discussion sur la pertinence des facteurs de mérite usuellement employés. D'autres études sur des atténuateurs programmables MMIC SiGe ont fait l'objet de brevets. La troisième partie, orientée système, aborde l'étude du bruit d'un récepteur : nous traitons ainsi le cas d'un étage de réception affecté par la chaîne d'émission, en proposant différentes parades permettant de limiter les dégradations de son plancher de bruit ; une technique de filtre compact intégré à l'amplificateur faible bruit a ainsi été brevetée. Enfin, le cas d'un système de liaison hertzienne embarqué sur automobile est abordé. Diverses stratégies sont ainsi proposées pour pallier les évènements conduisant à une rupture de la liaison (diversité temporelle, diversité spatiale et diversité de polarisation). Ces études reposent sur une approche mixte de traitement de mesures par des modèles théoriques, et des simulations électromagnétiques.

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Ahmad, Norhawati Binti. "Modelling and design of Low Noise Amplifiers using strained InGaAs/InAlAs/InP pHEMT for the Square Kilometre Array (SKA) application". Thesis, University of Manchester, 2012. https://www.research.manchester.ac.uk/portal/en/theses/modelling-and-design-of-low-noise-amplifiers-using-strained-ingaasinalasinp-phemt-for-the-square-kilometre-array-ska-application(b2b50fd8-0a13-4f71-b3f0-616ee4b2a82b).html.

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The largest 21st century radio telescope, the Square Kilometre Array (SKA) is now being planned, and the first phase of construction is estimated to commence in the year 2016. Phased array technology, the key feature of the SKA, requires the use of a tremendous number of receivers, estimated at approximately 37 million. Therefore, in the context of this project, the Low Noise Amplifier (LNA) located at the front end of the receiver chain remains the critical block. The demanding specifications in terms of bandwidth, low power consumption, low cost and low noise characteristics make the LNA topologies and their design methodologies one of the most challenging tasks for the realisation of the SKA. The LNA design is a compromise between the topology selection, wideband matching for a low noise figure, low power consumption and linearity. Considering these critical issues, this thesis describes the procedure for designing a monolithic microwave integrated circuit (MMIC) LNA for operation in the mid frequency band (400 MHz to 1.4 GHz) of the SKA. The main focus of this work is to investigate the potential of MMIC LNA designs based on a novel InGaAs/InAlAs/InP pHEMT developed for 1 µm gate length transistors, fabricated at The University of Manchester. An accurate technique for the extraction of empirical linear and nonlinear models for the fabricated active devices has been developed. In addition to the linear and nonlinear model of the transistors, precise models for passive devices have also been obtained and incorporated in the design of the amplifiers. The models show excellent agreement between measured and modelled DC and RF data. These models have been used in designing single, double and differential stage MMIC LNAs. The LNAs were designed for a 50 Ω input and output impedance. The excellent fits between the measured and modelled S-parameters for single and double stage single-ended LNAs reflects the accurate models that have been developed. The single stage LNA achieved a gain ranging from 9 to 13 dB over the band of operation. The gain was increased between 27 dB and 36 dB for the double stage and differential LNA designs. The measured noise figures obtained were higher by ~0.3 to ~0.8 dB when compared to the simulated figures. This is due to several factors which are discussed in this thesis. The single stage design consumes only a third of the power (47 mW) of that required for the double stage design, when driven from a 3 V supply. All designs were unconditionally stable. The chip sizes of the fabricated MMIC LNAs were 1.5 x 1.5 mm2 and 1.6 x 2.5 mm2 for the single and double stage designs respectively. Significantly, a series of differential input to single-ended output LNAs became of interest for use in the Square Kilometre Array (SKA), as it utilises differential output antennas in some of its configurations. The single-ended output is preferable for interfacing to the subsequent stages in the analogue chain. A noise figure of less than 0.9 dB with a power consumption of 180 mW is expected for these designs.

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Pabón, Armando Ayala. "Projeto de um bloco LNA-misturador para radiofrequência em tecnologia CMOS". Universidade de São Paulo, 2009. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-11082010-172655/.

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Este trabalho apresenta o projeto de um bloco LNA-Misturador dentro de um mesmo circuito integrado para aplicações em um receptor Bluetooth 2;45GHz. Uma estratégia de projeto bem clara, concisa e com uma boa base física e matemática foi desenvolvida para auxiliar o processo de projeto de um bloco LNA-Misturador, composto por um LNA cascode em cascata com um misturador de chaveamento de corrente com entradas simples e degeneração indutiva nas fontes dos estágios de transcondutância. Esta estratégia foi adaptada de trabalhos apresentados na literatura. A estratégia de projeto proposta considera o compromisso entre ruído, linearidade, ganho, dissipação de potência, casamento de impedâncias e isolamento de portas, usando as dimensões dos dispositivos e condições de polarização como variáveis de projeto. Com base nesta estratégia se obteve um bloco LNA-Misturador que atinge algumas especificações propostas. Um bloco LNA-Misturador foi projetado e fabricado em uma tecnologia CMOS 0;35µm para validar a estratégia de projeto proposta. Além disso, para atingir os objetivos, durante o desenvolvimento deste trabalho foi dada atenção especial no projeto dos indutores. Foi projetado, fabricado e medido um chip de teste. Para tal fim foram aplicadas técnicas e estruturas de de-embedding nas medidas para conseguir resultados mais confiáveis. Os resultados experimentais obtidos para os indutores e os resultados preliminares do bloco LNA-Misturador s~ao satisfatórios de acordo com as especificações e os esperados das simulações. No entanto, os indutores integrados degradam significativamente o desempenho do bloco LNA-Misturador. Se forem usados processos de fabricação nos quais os indutores apresentem melhor desempenho, os resultados do bloco LNA-Misturador aplicando a estratégia de projeto desenvolvida neste trabalho podem ser melhorados. Finalmente, é importante ressaltar que a estratégia de projeto proposta neste trabalho já está sendo usada e adaptada em outros projetos com o propósito de melhorar os resultados obtidos, e conseguir auxiliar o processo de projeto deste tipo de blocos.
This work presents a fully integrated LNA-Mixer design for a Bluetooth receiver application at 2:45GHz. A concise design strategy with good physics and mathematics basis was developed to assist the design process of a LNA-Mixer block, formed by a cascode LNA in cascade to a single balanced current commutation Mixer with inductive degeneration. This strategy was adapted from literature and considers the trade-offs between noise, linearity, gain, power dissipation, impedance matching and ports isolation, using the device dimensions and bias conditions as design variables. Based on this strategy, the proposed LNA-Mixer design specifications were achieved. To validate the proposed design strategy, the LNA-Mixer were fabricated in a 0:35µm CMOS process. Furthermore, to achieve the specifications, during the development of this work a special attention to the RF CMOS inductors was given. A test chip was designed, fabricated and measured applying de-embedding structures to obtain more reliable results. The experimental results obtained for the inductors and the preliminary results for the LNA-Mixer are satisfactory compared to the specifications and as expected from simulations. However, the integrated inductors degrade the performance of the block significantly and if a manufacturing process in which the inductor has better performance is used, the resulting LNA-Mixer design applying the strategy developed in this work can be improved. Finally, it is important to highlight that the design strategy proposed in this work is already being used and adapted in other designs in order to improve the results, and to assist the design process of such blocks.

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Xin, Chunyu. "Radio frequency circuits for wireless receiver front-ends". Texas A&M University, 2004. http://hdl.handle.net/1969.1/2757.

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The beginning of the 21st century sees great development and demands on wireless communication technologies. Wireless technologies, either based on a cable replacement or on a networked environment, penetrate our daily life more rapidly than ever. Low operational power, low cost, small form factor, and function diversity are the crucial requirements for a successful wireless product. The receiver??s front-end circuits play an important role in faithfully recovering the information transmitted through the wireless channel. Bluetooth is a short-range cable replacement wireless technology. A Bluetooth receiver architecture was proposed and designed using a pure CMOS process. The front-end of the receiver consists of a low noise ampliﬁer (LNA) and mixer. The intermediate frequency was chosen to be 2MHz to save battery power and alleviate the low frequency noise problem. A conventional LNA architecture was used for reliability. The mixer is a modiﬁed Gilbert-cell using the current bleeding technique to further reduce the low frequency noise. The front-end draws 10 mA current from a 3 V power supply, has a 8.5 dB noise ﬁgure, and a voltage gain of 25 dB and -9 dBm IIP3. A front-end for dual-mode receiver is also designed to explore the capability of a multi-standard application. The two standards are IEEE 802.11b and Bluetooth. They work together making the wireless experience more exciting. The front-end is designed using BiCMOS technology and incorporating a direct conversion receiver architecture. A number of circuit techniques are used in the front-end design to achieve optimal results. It consumes 13.6 mA from a 2.5 V power supply with a 5.5 dB noise ﬁgure, 33 dB voltage gain and -13 dBm IIP3. Besides the system level contributions, intensive studies were carried out on the development of quality LNA circuits. Based on the multi-gated LNA structure, a CMOS LNA structure using bipolar transistors to provide linearization is proposed. This LNA conﬁguration can achieve comparable linearity to its CMOS multi-gated counterpart and work at a higher frequency with less power consumption. A LNA using an on-chip transformer source degeneration is proposed to realize input impedance matching. The possibility of a dual-band cellular application is studied. Finally, a study on ultra-wide band (UWB) LNA implementation is performed to explore the possibility and capability of CMOS technology on the latest UWB standard for multimedia applications.

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Alvarado, Miguel A. "A Ka-band switch-LNA MMIC for radiometry applications". Connect to this title online, 2008. http://scholarworks.umass.edu/theses/79/.

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Pache, Denis. "Étude de nouvelles architectures pour l'intégration de fonctions radio fréquence en technologie BiCMOS". Grenoble INPG, 1996. http://www.theses.fr/1996INPG0079.

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Ce travail est consacre a l'integration des fonctions radio frequence (rf) de la partie reception d'un terminal mobile 2ghz en technologie silicium bicmos. Dans une premiere partie, les differentes caracteristiques des systemes rf sont rappelees. Ces systemes sont particulierement complexes (architecture, fiabilite) et les problemes lies a leur integration sont mis en evidence. Dans la partie suivante les principes de base et les proprietes des modulations analogiques et numeriques sont donnes. Dans une troisieme partie les composants silicium sont analyses. En particulier, une comparaison entre les transistors bipolaire et mos montre leurs limitations respectives et leur complementarite. Les systemes rf utilisent des inductances ; une modelisation de ce composant passif est proposee pour son integration sur silicium. Dans la derniere partie, quatre architectures pour une integration complete des quatre fonctions principales d'un recepteur (lna, filtre de frequence image et melangeur, filtre de frequence intermediaire, synthetiseur de frequence) sont proposees. Ces architectures ont ete validees par des mesures sur circuit. Leurs performances et leur souplesse permettent d'envisager maintenant la conception d'un recepteur rf totalement integre et adaptable a la plupart des normes des systemes rf (actuels ou futurs)

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Venkatasubramanian, Radhika. "High frequency continuous-time circuits and built-in-self-test using CMOS RMS detector". Texas A&M University, 2005. http://hdl.handle.net/1969.1/4746.

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The expanding wireless market has resulted in complex integrated transceivers that involve RF, analog and mixed-signal circuits, resulting in expensive and complicated testing. The most important challenges that test engineering faces today are (1) providing a fast and accurate fault-diagnosis and performance characterization so as to accelerate the time-to-market and (2) providing an inexpensive test strategy that can be integrated with the design so as to aid the high-volume manufacturing process. The first part of the research focuses on the design of an RMS detector for built-in-self-test (BIST) of an RF integrated transceiver that can directly provide information at various test points in the design. A cascode low noise amplifier (LNA) has been chosen as the device under test (DUT). A compact (< 0.031 mm2) RF RMS detector with negligible input capacitance (< 13 fF) has been implemented in 0.35 ÃÂµm CMOS technology along with the DUT. Experimental results are currently being assimilated and compared with the simulation results. Frequency limitations were encountered during the testing process due to unexpected increase in the value of the N-well resistors. All other problems faced during the testing, as well as the results obtained so far, are presented in this thesis. In the second part of the research, the use of the RMS detector for BIST has been extended to a continuous-time high-frequency boost-filter. The proposed HF RMS detector has been implemented along with a 24 dB 350 MHz boost filter as the DUT on 0.35 ÃÂµm CMOS technology. The HF RMS detector occupies 0.07 mm2 and has an input capacitance of 7 fF. The HF RMS detector has a dynamic range greater than 24 dB starting from -38 dBm of input power. The bandwidth and boost of the filter have been accurately estimated in simulation using the HF RMS detector. The sensitivity of an intermediate band pass node of the filter has also been monitored to predict the filter's sensitivity to Q errors. The final part of the research describes the design of a single-ended to differential converter for use in a broadband transceiver operating from 50-850 MHz. This circuit is used as the second stage in the transceiver after the LNA. The design has been simulated on a 0.35 um CMOS process and has a power consumption of 13.5 mW and less than 8 dB of noise figure over the entire band. It is capable of driving a 500fF load with less than 1dB of gain ripple over the entire band (50-850 MHz).

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Saini, Kanika. "Linearity Enhancement of High Power GaN HEMT Amplifier Circuits". Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/94361.

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Gallium Nitride (GaN) technology is capable of very high power levels but suffers from high non-linearity. With the advent of 5G technologies, high linearity is in greater demand due to complex modulation schemes and crowded RF (Radio Frequency) spectrum. Because of the non-linearity issue, GaN power amplifiers have to be operated at back-off input power levels. Operating at back-off reduces the efficiency of the power amplifier along-with the output power. This research presents a technique to linearize GaN amplifiers. The linearity can be improved by splitting a large device into multiple smaller devices and biasing them individually. This leads to the cancellation of the IMD3 (Third-order Intermodulation Distortion) components at the output of the FETs and hence higher linearity performance. This technique has been demonstrated in Silicon technology but has not been previously implemented in GaN. This research work presents for the first time the implementation of this technique in GaN Technology. By the application of this technique, improvement in IMD3 of 4 dBc has been shown for a 0.8-1.0 GHz PA (Power Amplifier), and 9.5 dBm in OIP3 (Third-order Intercept Point) for an S-Band GaN LNA, with linearity FOM (IP3/DC power) reaching up to 20. Large-signal simulation and analysis have been done to demonstrate linearity improvement for two parallel and four parallel FETs. A simulation methodology has been discussed in detail using commercial CAD software. A power sampler element is used to compute the IMD3 currents coming out of various FETs due to various bias currents. Simulation results show by biasing one device in Class AB and others in deep Class AB, IMD3 components of parallel FETs can be made out of phase of each other, leading to cancellation and improvement in linearity. Improvement up to 20 dBc in IMD3 has been reported through large-signal simulation when four parallel FETs with optimum bias were used. This technique has also been demonstrated in simulation for an X-Band MMIC PA from 8-10 GHz in GaN technology. Improvements up to 25-30 dBc were shown using the technique of biasing one device with Class AB and other with deep class AB/class B. The proposed amplifier achieves broadband linearization over the entire frequency compared to state-of-the-art PA's. The linearization technique demonstrated is simple, straight forward, and low cost to implement. No additional circuitry is needed. This technique finds its application in high dynamic range RF amplifier circuits for communications and sensing applications.
Doctor of Philosophy
Power amplifiers (PAs) and Low Noise Amplifiers (LNAs) form the front end of the Radio Frequency (RF) transceiver systems. With the advent of complex modulation schemes, it is becoming imperative to improve their linearity. Through this dissertation, we propose a technique for improving the linearity of amplifier circuits used for communication systems. Meanwhile, Gallium Nitride (GaN) is becoming a technology of choice for high-power amplifier circuits due to its higher power handling capability and higher breakdown voltage compared with Gallium Arsenide (GaAs), Silicon Germanium (SiGe) and Complementary Metal-Oxide-Semiconductor (CMOS) technologies. A circuit design technique of using multiple parallel GaN FETs is presented. In this technique, the multiple parallel FETs have independently controllable gate voltages. Compared to a large single FET, using multiple FETs and biasing them individually helps to improve the linearity through the cancellation of nonlinear distortion components. Experimental results show the highest linearity improvement compared with the other state-of-the-art linearization schemes. The technique demonstrated is the first time implementation in GaN technology. The technique is a simple and cost-effective solution for improving the linearity of the amplifier circuits. Applications include base station amplifiers, mobile handsets, radars, satellite communication, etc.

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Pimentel, Henrique Luiz Andrade. "Projeto de um amplificador de baixo ruído em tecnologia CMOS 130nm para frequências de 50MHZ a 1GHz". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/67180.

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O presente trabalho tem por objetivo fornecer o embasamento teórico para o projeto de um amplificador de baixo ruído (LNA – Low Noise Amplifier) em tecnologia CMOS que opere em mais de uma faixa de frequência, de modo a permitir seu uso em receptores multibanda e de banda larga. A base teórica que este trabalho abrange desde a revisão bibliográfica do assunto em questão, passando pela análise dos modelos de transistores para alta-frequência, pelo estudo das especificações deste bloco e das métricas utilizadas em projetos de circuitos integrados de RF, bem como pela revisão de topologias clássicas existentes. Com os conhecimentos acima adquiridos, foi possível realizar o projeto de um LNA diferencial de banda larga utilizando tecnologia CMOS IBM 130nm, o qual pode ser aplicado ao padrão IEEE 802.22 para rádios cognitivos (CR). O projeto é baseado na técnica de cancelamento de ruído, sendo validado após apresentar efetiva redução de figura de ruído para banda de frequência desejada, com moderado consumo de potência e utilização moderada de área de silício, devido a solução sem o uso de indutores. O LNA banda larga opera em frequências de 50Mhz a 1GHz e apresenta uma figura de ruído abaixo de 4dB, em 90% da faixa, um ganho acima de 12dB, e perda de retorno na entrada e na saída maiores que 12dB. O IIP3 e a frequência de ocorrência de compressão a 1dB com a entrada em 580MHz estão acima de 0dBm e -10dBm respectivamente. Possui consumo de 46,5mWpara fonte de 1,5V e ocupa uma área ativa de apenas 0,28mm x 0,2mm.
This work presents the theoretical basis for the design of a low noise amplifier (LNA) in CMOS technology that operates in more than one frequency band, which enables its use in multi-band and wideband receivers. The theoretical basis that this work will address extends from the literature review on the subject, through the analysis of models of MOS transistors for high frequencies, study of specifications of this block and the metrics used in RF integrated circuit design, as well as the review of existing classical LNA topologies. Based on the knowledge acquired above, the design of a differential wideband LNA is developed using IBM 130nm RF CMOS process, which can be used in IEEE 802.22 Cognitive Radio (CR) applications. The design is based on the noise-canceling technique, with an indutctorless solution, showing that this technique effectively reduces the noise figure over the desired frequency range with moderate power consumption and a moderate utilization of silicon die area. The wideband LNA covers the frequency range from 50 MHz to 1 GHz, achieving a noise figure below 4dB in over 90% of the band of interest, a gain of 11dB to 12dB, and an input/output return loss higher than -12 dB. The input IIP3 and input P1dB at 580MHz are above 0dB and -10dB, respectively. It consumes 46.5mW from a 1.5V supply and occupies an active area of only 0.056mm2 (0.28mm x 0.2mm).

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Ortigueira, Eduardo José Resende. "A combined LNA-oscillator-mixer for biomedical applications". Master's thesis, Faculdade de Ciências e Tecnologia, 2011. http://hdl.handle.net/10362/6320.

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Woo, Sang Hyun. "Low noise RF CMOS receiver integrated circuits". Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50127.

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The objective of this research is to design and implement low-noise wideband RFIC components with CMOS technology for the direct-conversion architecture. This research proposes noise reduction techniques to improve the thermal noise and flicker noise contribution of a low noise amplifier (LNA) and a mixer. Of these techniques, the LNA is found to reduce noise, boost gain, and consume a relatively low amount of power without sacrificing the wideband and linearity advantages of a conventional common gate (CG) topology. The research concludes by investigating the proposed mixer topology, which senses and compensates local oscillator (LO) phase mismatches, the dominant cause of flicker noise.

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Chirala, Mohan Krishna. "Passive and active circuits in cmos technology for rf, microwave and millimeter wave applications". [College Station, Tex. : Texas A&M University, 2007. http://hdl.handle.net/1969.1/ETD-TAMU-2069.

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Hoffman, Anton, i Mikael Johansson. "Framtagning av universell fixtur för SMD-lina". Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-49415.

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Det här projektet har utförts i samarbete med företaget Eskilstuna Elektronikpartner AB (EEPAB). Företaget arbetar med tillverkning av kretskort där de använder sig av ytmontering och hålmontering. Vissa mönsterkort kan vara böjda och kan därmed orsaka problem i Surface Mount Device (SMD)-linan. Syftet med projektet var att ta fram en fixtur som gör mönsterkorten planare vilket innebär att minska höjdskillnaden mellan högsta och lägsta punkten på korten. Detta för att effektivisera och förhindra stopp i produktionen. Två forskningsfrågor togs fram som fungerade som ett stöd under projektets gång: F1:Hur förbättras produktionen i en SMD-lina när mönsterkorten hålls plana? F2:Vilka faktorer bör beaktas när en fixtur tas fram för en SMD-lina? Projektet har följt en produktutvecklingsprocess där fokuset har legat på konceptstadiet. Data har samlats in genomen litteraturstudie, intervjuer samt ett formulär. Projektet resulterade i ett slutgiltigt koncept i form av en fixtur. Resultatet i projektet visar att genom att spänna fast mönsterkortets kortsidor så minskas nedböjningen. Genom planare mönsterkort minskas risken för fel mängdapplicering av lödpasta som i sin tur kan orsaka kortslutning eller en öppen slutning. Att problemen med fel mängd lödpasta minskas leder även till att manuellt arbete som tvättning och applicering av lödpasta kan reduceras. När lödpasta appliceras för hand är det även svårt att veta om rätt mängd har applicerats, detta kan även leda till problem under lödningen. Sedan kan det konstateras att designen av fixturen måste samspela med alla maskiner i SMD-linan för att inte orsaka problem eller hindra maskinerna från att utföra dess arbete. Utifrån ett koncepttest visade det sig att det framtagna konceptet gör mönsterkorten cirka 42% planare. Detta bör kunna minska problemen i SMD-linan och spara in tiden det tar att åtgärda dessa problem. Koncepttestet utfördes inte i den rätta maskinen och måste därmed undersökas ordentligt. Det var endast ett sorts mönsterkort som testades, dessa faktorer är exempel på felkällor. I framtiden bör ett flertal olika mönsterkort testas för att få en högre reliabilitet. Det behövs även tas fram en exakt tolerans för när mönsterkorten är för böjda och problem uppstår. I dagsläget finns endast maskinens egentolerans som inte stämmer särskilt bra och en generell tolerans för SMD-linor.

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Suenaga, Portuguès Kay. "Test estructural i predictiu per a circuits RF CMOS". Doctoral thesis, Universitat de les Illes Balears, 2008. http://hdl.handle.net/10803/9431.

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En aquesta tesi s'ha desenvolupat una tècnica de test que permet testar un LNA i un mesclador, situats en el capçal RF d'un receptor CMOS, en una configuració de test semblant al mode normal de funcionament.
La circuiteria necessària per a implementar aquesta tècnica consta d'un generador IF, per a generar el senyal IF de test, i d'un mesclador auxiliar, per a obtenir el senyal RF de test.
Les observables de test escollides han estat l'amplitud de la tensió de sortida del mesclador i el component DC del corrent de consum.
S'ha estudiat l'eficàcia de la tècnica de test proposada utilitzant les estratègies de test estructural i predictiu, mitjançant simulacions i mesures experimentals. La seva eficàcia és comparable a altres tècniques de test existents, però l'àrea addicional dedicada a la circuiteria test és inferior.
En esta tesis se ha desarrollado una técnica de test que permite verificar un LNA y un mezclador, situados en el cabezal RF de un receptor CMOS, en una configuración de test similar al modo normal de funcionamiento.
Los circuitos necesarios para implementar esta técnica son: un generador IF, que permite generar la señal IF de test, y un mezclador auxiliar, para obtener la señal RF de test.
Las observables de test seleccionadas han sido la amplitud de la tensión de salida y la componente DC de la corriente de consumo.
Se ha estudiado la eficacia de la técnica propuesta usando las estrategias de test estructural y predictiva, mediante simulaciones y medidas experimentales. Su eficacia es comparable a otras técnicas existentes, pero el área dedicada a la circuiteria de test es inferior.
This PhD thesis develops a test technique intended for the RF front end of CMOS integrated receivers. This test technique allows testing individually the building blocks of the receiver in a sequential way. The test mode configuration of each block is similar to the normal mode operation.
The auxiliary circuitry required to generate the test stimuli consists of an IF generator, which generates the IF test signal, and an auxiliary mixer that produces the RF test signal by mixing the IF test signal with the local oscillator signal.
The test observables selected for the test are the voltage amplitude after the IF amplifier, and the DC component of the supply current in each block.
The capability of the proposed test technique to perform structural and predictive test strategies has been validated by simulation and experimentally. Its efficiency is comparable to other existing techniques, but the silicon area overhead is lower.

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Bu, Long. "Linearity and Interference Robustness Improvement Methods for Ultra-Wideband Cmos Rf Front-End Circuits". The Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=osu1211476269.

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Severino, Raffaele Roberto. "Design methodology for millimeter wave integrated circuits : application to SiGe BiCMOS LNAs". Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14284/document.

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Grace aux récents développements des technologies d’intégration, il est aujourd’hui possible d’envisager la réalisation de circuits et systèmes intégrés sur Silicium fonctionnant à des fréquences auparavant inatteignables. Par conséquence, depuis quelques années, on assiste à la naissance de nouvelles applications en bande millimétrique, comme la communication sans fil à haut-débit à 60GHz, les radars automobiles à 76-77 et 79-82GHz, et l’imagerie millimétrique à 94GHz.Cette thèse vise, en premier lieu, à la définition d’une méthodologie de conception des circuits intégrés en bande millimétrique. Elle est par la suite validée au travers de son application à la conception des amplificateurs faible-bruit en technologie BiCMOS SiGe. Dans ce contexte, une attention particulière a été portée au développement d’une stratégie de conception et de modélisation des inductances localisées. Plusieurs exemples d’amplificateurs faible-bruit ont été réalisés, à un ou deux étages, employant des composants inductifs localisés ou distribués, à 60, 80 et 94 GHz. Tous ces circuits présentent des caractéristiques au niveau de l’état de l’art dans le domaine, ainsi en confirmant l’exactitude de la méthodologie de conception et son efficacité sur toute la planche de fréquence considérée. En outre, la réalisation d’un récepteur intégré pour applications automobiles à 80GHz est aussi décrite comme exemple d’une possible application système, ainsi que la co-intégration d’un amplificateur faible-bruit avec une antenne patch millimétrique intégrée sur Silicium
The interest towards millimeter waves has rapidly grown up during the last few years, leading to the development of a large number of potential applications in the millimeter wave band, such as WPANs and high data rate wireless communications at 60GHz, short and long range radar at 77-79GHz, and imaging systems at 94GHz.Furthermore, the high frequency performances of silicon active devices (bipolar and CMOS) have dramatically increased featuring both fT and fmax close or even higher than 200GHz. As a consequence, modern silicon technologies can now address the demand of low-cost and high-volume production of systems and circuits operating within the millimeter wave range. Nevertheless, millimeter wave design still requires special techniques and methodologies to overcome a large number of constraints which appear along with the augmentation of the operative frequency.The aim of this thesis is to define a design methodology for integrated circuits operating at millimeter wave and to provide an experimental validation of the methodology, as exhaustive as possible, focusing on the design of low noise amplifiers (LNAs) as a case of study.Several examples of LNAs, operating at 60, 80, and 94 GHz, have been realized. All the tested circuits exhibit performances in the state of art. In particular, a good agreement between measured data and post-layout simulations has been repeatedly observed, demonstrating the exactitude of the proposed design methodology and its reliability over the entire millimeter wave spectrum. A particular attention has been addressed to the implementation of inductors as lumped devices and – in order to evaluate the benefits of the lumped design – two versions of a single-stage 80GHz LNA have been realized using, respectively, distributed transmission lines and lumped inductors. The direct comparison of these circuits has proved that the two design approaches have the same potentialities. As a matter of fact, design based on lumped inductors instead of distributed elements is to be preferred, since it has the valuable advantage of a significant reduction of the circuit dimensions.Finally, the design of an 80GHz front-end and the co-integration of a LNA with an integrated antenna are also considered, opening the way to the implementation a fully integrated receiver

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Li, Zhenbiao. "Radio frequency circuits for tunable multi-band CMOS receivers for wireless LAN applications". [Gainesville, Fla.] : University of Florida, 2004. http://purl.fcla.edu/fcla/etd/UFE0006637.

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Anjos, Angélica dos. "Integração de blocos RF CMOS com indutores usando tecnologia Flip Chip". Universidade de São Paulo, 2012. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-15072013-164829/.

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Neste trabalho foi feita uma ampla pesquisa sobre blocos de RF, VCOs e LNAs, que fazem parte de transceptores. Esses blocos foram projetados utilizando um indutor externo com um alto Q, com o intuito de melhorar as principais características de desempenho de cada um dos blocos. Com a finalidade de ter um ponto de comparação foram projetados os mesmos blocos implementando todos os indutores integrados (internos). Foi proposta a utilização da tecnologia flip chip para interconectar os indutores externos aos dies dos circuitos, devido às vantagens que ela apresenta. Para implementar os indutores externos propôs-se um processo de fabricação completo, incluindo especificação das etapas de processos e dos materiais utilizados para estes indutores. Adicionalmente foi projetado um conjunto de máscaras para fabricar os indutores externos e fazer a montagem e teste dos circuitos que os utilizam. Para validar o processo proposto e caracterizar os indutores externos foram projetadas diferentes estruturas de teste. O Q do indutor externo é da ordem de 6 vezes maior que do indutor integrado, para a tecnologia escolhida. Foram projetados e fabricados dois VCOs LC: FC-VCO (Flip Chip VCO com o indutor externo), OC-VCO (On Chip VCO com o indutor interno), e dois LNAs CMOS de fonte comum cascode com degeneração indutiva: FC-LNA (Flip Chip LNA com o indutor Lg externo) e OC-LNA (On Chip LNA com todos os indutores internos). O objetivo desses quatro circuitos é demonstrar que o desempenho de circuitos RF pode ser melhorado, usando indutores externos com alto Q, conectados através de flip chip. Para implementação desses circuitos utilizou-se a tecnologia de processo AMS 0,35µm CMOS, para aplicações na banda 2,4GHz ISM, considerando o padrão Bluetooth. Foram medidos apenas os blocos com os indutores internos (OC-VCO e OC-LNA). Para os blocos com os indutores externos (FC-VCO e FC-LNA) foram apresentados os resultados de simulação pós-layout. Através da comparação dos resultados de simulação entre os VCOs foi comprovado que o uso de um indutor externo com alto Q conectado via flip chip pode melhorar significativamente o ruído de fase dos VCOs, atingindo -117dBc/Hz a 1MHz de frequência de offset para o FC-VCO, em 2,45GHz, onde a FOM é 8dB maior que o OC-VCO. Outro ganho foi através da área poupada, o FC-VCO tem uma área cerca de 83% menor que a do OC-VCO. Após as medidas elétricas do OC-VCO obteve-se um desempenho do ruído de fase de -110dBc/Hz@1MHz para 2,45GHz, e -112dBc/Hz@1MHz para 2,4GHz, o qual atende as especificações de projeto. O FC-LNA, que foi implementado com o indutor de porta Lg externo ao die, conectado via flip chip, atingiu uma figura de ruído de 2,39dB, 1,1dB menor que o OC-LNA com o mesmo consumo de potência. A área ocupada pelo FC-LNA é aproximadamente 30% menor do que o OC-LNA. Através das medidas elétricas do OC-LNA verificou-se que o circuito apresenta resultados adequados de S11 (perda de retorno da entrada) e S22 (perda de retorno da saída) na banda de frequências de interesse. No entanto, o valor do ganho apresenta uma redução em relação ao esperado. A proposta do trabalho de unir a tecnologia flip chip ao uso de indutores externos, proporciona circuitos mais compactos e consecutivamente mais baratos, pela economia de área de Si. Adicionalmente, após os indutores externos serem caracterizados, os mesmos indutores podem ser reutilizados independente da tecnologia CMOS utilizada facilitando o projeto dos blocos de RF em processos mais avançados.
This work presents a research about RF blocks that are used in Transceivers, VCOs and LNAs. These blocks were designed using a high-Q RF external inductor in order to improve the main performance characteristics. The same blocks were designed implementing all inductors on-chip (internal) in order to have a point of comparison. It was proposed the use of Flip Chip technology to interconnect the external inductors to the dies of the circuits due to the advantages that this technology offers. A full manufacturing process was proposed to implement the external inductors, including the specification of process steps and materials used for these inductors. Additionally, a set of masks was designed to fabricate the external inductors, to mount and test the circuits that used these inductors. Different test structures were designed to validate the proposed process and to characterize the external inductors. Q factor of the external inductor is around 6 times larger than the inductor integrated into the chosen IC technology. Two LC VCOs and two common-source cascode CMOS LNAs with inductive degeneration were designed and fabricated: FC-VCO (Flip Chip VCO using external inductor), OC-VCO (On Chip VCO using on-chip inductor), FCLNA (Flip Chip LNA using an external Lg inductor) and OC-LNA (On Chip LNA with all inductors implemented on-chip). The purpose of these four circuits is to demonstrate that the performance of RF circuits can be improved by using high-Q external inductors, connected by flip chip. The 0.35µm CMOS AMS technology was used to implement these circuits intended for applications in the 2.4 GHz ISM band, considering the Bluetooth standard. Were measured only the blocks with internal inductors (OC-VCO and OC-LNA). For the blocks with external inductors (FCVCO and FC-LNA) were presented the results of post-layout simulation. The comparison between the VCOs simulations results demonstrates that using an external high-Q inductor connected by flip chip can significantly improve the phase noise of VCOs. FC-VCO reached a phase noise of -117dBc/Hz at 1MHz offset frequency and a FOM 8dB greater than the OC-VCO. Another important improvement was the saved area, the FC-VCO has an area approximately 83% lower than that of OC-VCO. After electrical characterizations of the OC-VCO, phase noise performances of -110dBc/Hz@1MHz for 2.45GHz and -112dBc/Hz@1MHz for 2.4GHz were obtained, that accomplish the design specifications. FC-LNA reached a noise figure of 2.39dB, 1.1dB lower than that of OC-LNA with the same power comsumption. The total area occupied by FC-LNA is around 30% lower than that OC-LNA. Measurement results of the OC-LNA showed that the circuit presents suitable S11 (input return loss) and S22 (output return loss) values in the desired frequency band. However, the gain value presents a reduction compared with the expected values. The proposal to use the flip chip technology together with external inductors, allows more compact and cheap circuits, because Silicon area can be saved. Moreover, after the external inductors being characterized, the same inductors can be reused regardless of the CMOS technology facilitating the design of RF blocks in more advanced processes.

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Al, Khoury Michel. "Intégration de filtres Radio Fréquences en technologie intégrée Silicium". Limoges, 2011. https://aurore.unilim.fr/theses/nxfile/default/8d644bc8-5cd6-464f-a4e4-4ac00c82ac27/blobholder:0/2011LIMO4038.pdf.

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Les systèmes de télécommunications sans fil ont évolué de façon rapide depuis une vingtaine d’année. La conception de ces systèmes est soumise à de nombreuses contraintes : le coût de production, les techniques d’intégration des composants, l’encombrement, etc. La technologie monolithique et plus précisément les procédés de fabrication de circuits silicium (CMOS et BiCMOS) offrent depuis plusieurs années une possibilité de pallier à ce type de difficultés. Ils permettent aujourd’hui l’intégration de plusieurs fonctions RF et mixte sur une seule puce. Malheureusement, la conception de certaines fonctions RF pose encore problème. C’est le cas des filtres radiofréquences qui constituent les éléments essentiels du système de télécommunication. Les exigences demandées pour ces filtres conduisent à étudier des solutions de filtres actifs ; en effet les structures passives (à cavités ou à résonateurs diélectriques ou à ondes acoustiques de surface) ne permettent pas d’avoir de meilleures performances en termes de pertes d’insertion, sélectivité, encombrement et accordabilité fréquentielle. Dans cette thèse préparée avec le soutien contractuel de l’ANR (projet SRAMM - Systèmes de Réception Adaptatifs Multimodes Multistandards), nous nous sommes intéressés à l’étude d’une nouvelle topologie de filtrage actif LC basée sur l’utilisation d’une inductance compensée à trois inductances couplées. Notre travail consiste également à définir une méthodologie de modélisation des trois inductances couplées et à utiliser cette dernière pour la réalisation d’un circuit LNA filtrant accordable utilisable en bande GSM3G
Wireless communications have evolved rapidly over the past twenty years. The design of these systems face some challenges: production cost, components integration techniques, size reduction, etc. Since many years, monolithic technology and specifically the manufacturing processes of silicon circuits (CMOS and BiCMOS) offer an opportunity to overcome such difficulties. Nowadays, they allow the integration of several RF and mixed functions on a single chip. However, the design of some RF functions is still a problem. This is the case of RF filters which constitute the essential elements of GSM telecommunications system. The demanded requirements by these filters lead to study solutions of active filters because passive structures (cavity, dielectric or SAW - Surface Acoustic Wave) do not allow better performance in term of insertion losses, selectivity, size reduction and frequency tuning. In this thesis, supported by an ANR contract (SRAMM project - Systèmes de Réception Adaptatifs Multimodes Multistandards), we were interested in the study of a new topology for active LC filter using Q-enhanced inductors. Our research analysis also consisted in defining a methodology for modeling three coupled inductors and using it to implement tunable LNA filter circuit useable in GSM3G system

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Madan, Anuj. "Design and reliability of high dynamic range RF building blocks in SOI CMOS and SiGe BiCMOS technologies". Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/45853.

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The objective of the proposed research is to understand the design and reliability of RF front-end building blocks using SOI CMOS and SiGe BiCMOS technologies for high dynamic-range applications. This research leads to a comprehensive understanding of dynamic range in SOI CMOS devices and contributes to knowledge leading to improvement in overall dynamic range and reliability of RF building blocks. While the performance of CMOS transistors has been improving naturally with scaling, this work aims to explore the possibilities of improvement in RF performance and reliability using standard layouts (that don't need process modifications). The total-ionizing dose tolerance of SOI CMOS devices has been understood with extensive measurements. Furthermore, the role of body contacts in SOI technology is understood for dynamic range performance improvement. In this work, CMOS low-noise amplifier design for high linearity WLAN applications and its integration with RF switch on the same chip is presented. The LNA and switches designed provide state-of-the-art performance in silicon based technologies. Further, the work aims to explore applications of SiGe HBT in the context of highly linear and reliable RF building blocks. The RF reliability of SiGe HBT based RF switches is investigated and compared with CMOS counterparts. The inverse-mode operation of SiGe HBT based switches is understood to give considerably higher linearity.

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Matos, Gonçalo da Conceição. "As Minas Barrojeiras das Alcanadas: um estudo para a sua valorização patrimonial". Master's thesis, Universidade de Évora, 2016. http://hdl.handle.net/10174/18959.

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O património industrial mineiro assume cada vez mais, uma importância crescente em Portugal. As estruturas abandonadas deste período industrial que tanto marcou o nosso país estão a ser cada vez mais desprotegidas, sofrendo uma degradação crescente à medida que o tempo passa. É, portanto, relevante recuperá-las e elaborar projetos de valorização que visem dinamizar essas áreas preservando a memória coletiva. É neste panorama que se inserem as Minas das Barrojeiras das Alcanadas, concelho da Batalha. Pertencentes ao Couto Mineiro do Lena, laborando entre 1854 e 1956, estas minas foram abandonadas e entretanto despidas das estruturas que a compunham. Tendo isto em conta, foi proposta a realização de um circuito de valorização que complementa a exposição presente no MCCB, e que irá dinamizar aquele local; ABSTRACT: The industrial mining heritage, has nowadays an increasing importance in Portugal. The abandoned structures of this industrial time that defined so intensely our country are being forsaken more and more, suffering a growing degradation though out the time. Is therefore imperative to recover them and produce valuation projects that aim on enhancing the sites. Is in this perspective that the Minas of Barrojeiras of Alcanadas (in Batalha) are inserted. Belonging in the Couto Mineiro do Lena, and being active from 1854 till 1956, these mines were forsaken and later on, stripped from the structures that followed the activities of exploring the mineral. With this in mind, was proposed a valorization circuit that will enhance the location of the mine´s and will be a complement to the exhibition in Batalha´s MCCB.

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Joshi, Shital. "Analysis and Optimization of Graphene FET based Nanoelectronic Integrated Circuits". Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849755/.

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Like cell to the human body, transistors are the basic building blocks of any electronics circuits. Silicon has been the industries obvious choice for making transistors. Transistors with large size occupy large chip area, consume lots of power and the number of functionalities will be limited due to area constraints. Thus to make the devices smaller, smarter and faster, the transistors are aggressively scaled down in each generation. Moore's law states that the transistors count in any electronic circuits doubles every 18 months. Following this Moore's law, the transistor has already been scaled down to 14 nm. However there are limitations to how much further these transistors can be scaled down. Particularly below 10 nm, these silicon based transistors hit the fundamental limits like loss of gate control, high leakage and various other short channel effects. Thus it is not possible to favor the silicon transistors for future electronics applications. As a result, the research has shifted to new device concepts and device materials alternative to silicon. Carbon is the next abundant element found in the Earth and one of such carbon based nanomaterial is graphene. Graphene when extracted from Graphite, the same material used as the lid in pencil, have a tremendous potential to take future electronics devices to new heights in terms of size, cost and efficiency. Thus after its first experimental discovery of graphene in 2004, graphene has been the leading research area for both academics as well as industries. This dissertation is focused on the analysis and optimization of graphene based circuits for future electronics. The first part of this dissertation considers graphene based transistors for analog/radio frequency (RF) circuits. In this section, a dual gate Graphene Field Effect Transistor (GFET) is considered to build the case study circuits like voltage controlled oscillator (VCO) and low noise amplifier (LNA). The behavioral model of the transistor is modeled in different tools: well accepted EDA (electronic design automation) and a non-EDA based tool i.e. \simscape. This section of the dissertation addresses the application of non-EDA based concepts for the analysis of new device concepts, taking LC-VCO and LNA as a case study circuits. The non-EDA based approach is very handy for a new device material when the concept is not matured and the model files are not readily available from the fab. The results matches very well with that of the EDA tools. The second part of the section considers application of multiswarm optimization (MSO) in an EDA tool to explore the design space for the design of LC-VCO. The VCO provides an oscillation frequency at 2.85 GHz, with phase noise of less than -80 dBc/Hz and power dissipation less than 16 mW. The second part of this dissertation considers graphene nanotube field effect transistors (GNRFET) for the application of digital domain. As a case study, static random access memory (SRAM) hs been design and the results shows a very promising future for GNRFET based SRAM as compared to silicon based transistor SRAM. The power comparison between the two shows that GNRFET based SRAM are 93% more power efficient than the silicon transistor based SRAM at 45 nm. In summary, the dissertation is to expected to aid the state of the art in following ways: 1) A non-EDA based tool has been used to characterize the device and measure the circuit performance. The results well matches to that obtained from the EDA tools. This tool becomes very handy for new device concepts when the simulation needs to be fast and accuracy can be tradeoff with. 2)Since an analog domain lacks well-design design paradigm, as compared to digital domain, this dissertation considers case study circuits to design the circuits and apply optimization. 3) Performance comparison of GNRFET based SRAM to the conventional silicon based SRAM shows that with maturation of the fabrication technology, graphene can be very useful for digital circuits as well.

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Collot, Ludovic. "Étude de nouvelles architectures de filtres RF intégrés dans le contexte de la radio opportuniste". Limoges, 2011. https://aurore.unilim.fr/theses/nxfile/default/790e39b6-b073-4378-9625-215ed53b5b21/blobholder:0/2011LIMO4020.pdf.

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Ce travail de thèse porte sur la conception de fonctions filtrantes passe-bandes microondes à la fois intégrables en technologie MMIC, accordables et différentielles. L’objectif principal est de réaliser des structures filtrantes et accordables utilisables dans un context de radio opportuniste. Le second objectif est de montrer que l’utilisation d’inductances ferromagnétiques dans ces structures en améliore les performances. Les chaînes de reception actuelles sont figées de part leurs architectures et les composants utilisés (SAW filter, LNA par exemple). Nous proposons de concevoir de nouveaux circuits intégrés : LNA filtrant et filtres à 1, 2 et 3 pôles permettant de rendre la chaîne RF agile en fréquence. Ces circuits reposent sur une topologie très simple de résonateurs LC compensés et permettent d’obtenir une accordabilité continue de la bande passante et de la fréquence centrale sur une octave. Les résultats obtenus, et principalement ceux du LNA filtrant, montent qu’il est possible de concilier fonction de filtrage accordable, gain et faible facteur de bruit sur une unique puce MMIC, ce qui constitue un premier pas vers la conception d’une chaîne de reception opportuniste
This work concerns the conception of microwaves filtering functions at the same time band-pass, MMIC technology compliant, tunable and differential. The main objective is to realize filtering structures compatible with opportunist radio. The second objective is to demonstrate that ferromagnetics inductors improves the performance of such devices. Commersialised RF receivers are deadlocked due to their topologies and used components (SAW filter, LNA for example). We put forward new integrated circuits : filtering LNA and 1, 2 and 3 poles filters usable in fully frequency tunable receivers. These circuits are Q-enhanced resonator based. They have a continuous frequency and bandwidth tunability over an octave. The observed results at first for filtering LNA mixe wide tunablility, gain and low noise figure on a unique MMIC circuit. This contribution is a first step toward opportunists receivers

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Fadhuile-Crepy, François. "Méthodologie de conception de circuits analogiques pour des applications radiofréquence à faible consommation de puissance". Thesis, Bordeaux, 2015. http://www.theses.fr/2015BORD0028/document.

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Les travaux de thèse présentés se situent dans le contexte de la conception de circuits intégrés en technologie CMOS avancée pour des applications radiofréquence à très faible consommation de puissance. Les circuits sont conçus à travers deux concepts. Le premier est l'utilisation du coefficient d'inversion qui permet de normaliser le transistor en fonction de sa taille et de sa technologie, ceci permet une analyse rapide pour différentes performances visées ou différentes technologies. La deuxième approche est d'utiliser un facteur de mérite pour trouver la polarisation la plus adéquate d'un circuit en fonction de ses performances. Ces deux principes ont été utilisés pour définir des méthodes de conception efficaces pour deux blocs radiofréquence : l'amplificateur faible bruit et l'oscillateur
Thesis work are presented in the context of the integrated circuits design in advanced CMOS technology for ultra low power RF applications. The circuits are designed around two concepts. The first is the use of the inversion coefficient to normalize the transistor as a function of its size and its technology, this allows a quick analysis for different performances or different technologies. The second approach is to use a figure of merit to find the most appropriate polarization of a circuit based on its performance. These two principles were used to define effective design methods for two RF blocks: low noise amplifier and oscillator

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Busquere, Jean-Pierre. "Développement et intégration de MEMS RF dans les architectures d'amplificateur faible bruit reconfigurables". Phd thesis, INSA de Toulouse, 2005. http://tel.archives-ouvertes.fr/tel-00446353.

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De nos jours, les modules hyperfréquences doivent de plus en plus présenter non seulement des performances électriques sans cesse améliorées mais aussi des fonctionnalités nouvelles ainsi que de fortes compacités, et des coûts de fabrication les plus réduits possibles. Les perspectives attractives apportées par l'utilisation des technologies SiGe permettent aujourd'hui d'envisager la réalisation de circuits intégrés jusqu'aux fréquences millimétriques tandis que, dans le même temps, le développement rapide des technologies MEMS RF permet de réaliser de nouvelles fonctionnalités au niveau des circuits radiofréquences. Dans la première partie de ce mémoire, nous proposons un concept d'amplificateur faible bruit reconfigurable en fréquence (HIPERLAN et BLUETOOTH), basé sur l'association des technologies SiGe et MEMS RF. Conception et performances simulées des amplificateurs élaborés à la fois pour une intégration monolithique et une autre par fil de souduresont alors présentées. La deuxième partie est entièrement consacrée à la conception et la réalisation des MEMS RF suivant les spécifications que nous avons établi lors de la première partie. Conception, réalisation et caractérisation des structures MEMS RF sont présentés, pour aboutir à l'obtention de performances situées à l'état de l'art pour des capacités autant séries que parallèles. La dernière partie, traite de l'assemblage entre les deux technologies MEMS et SiGe, avec trois études réalisées sur une intégration monolithique dite « Above IC », un assemblage par fils de soudure et un assemblage Flip Chip. Au final, des modules de test assemblés sont présentés et caractérisés

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Chen, Tingsu. "Spin Torque Oscillator Modeling, CMOS Design and STO-CMOS Integration". Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-176890.

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Spin torque oscillators (STOs) are microwave oscillators with an attractive blend of features, including a more-than-octave tunability, GHz operating frequencies, nanoscale size, nanosecond switching speed and full compatibility with CMOS technology. Over the past decade, STOs' physical phenomena have been explored to a greater extent, their performance has been further improved, and STOs have already shown great potential for a wide range of applications, from microwave sources and detectors to neuromorphic computing. This thesis is devoted to promoting the STO technology towards its applications, by means of implementing the STO's electrical model, dedicated CMOS integrated circuits (ICs), and STO-CMOS IC integration. An electrical model, which can capture magnetic tunnel junction (MTJ) STO's characteristics, while enabling system- and circuit-level designs and performance evaluations, is of great importance for the development of MTJ STO-based applications. A comprehensive and compact analytical model, which is based on macrospin approximations and can fulfill the aforementioned requirements, is proposed. This model is fully implemented in Verilog-A, and can be used for efficient simulations of various MTJ STOs. Moreover, an accurate phase noise generation approach, which ensures a reliable model, is proposed and successfully used in the Verilog-A model implementation. The model is experimentally validated by three different MTJ STOs under different bias conditions. CMOS circuits, which can enhance the limited output power of MTJ STOs to levels that are required in different applications, are proposed, implemented and tested. A novel balun-low noise amplifier (LNA), which can offer sufficient gain, bandwidth and linearity for MTJ STO-based magnetic field sensing applications, is proposed. Additionally, a wideband amplifier, which can be connected to an MTJ STO to form a highly-tunable microwave oscillator in a phase-locked loop (PLL), is also proposed. The measurement results demonstrate that the proposed circuits can be used to develop MTJ STO-based magnetic field sensing and microwave source applications. The investigation of possible STO-CMOS IC integration approaches demonstrates that the wire-bonding-based integration is the most suitable approach. Therefore, a giant magnetoresistance (GMR) STO is integrated with its dedicated CMOS IC, which provides the necessary functions, using the wire-bonding-based approach. The RF characterization of the integrated GMR STO-CMOS IC system under different magnetic fields and DC currents shows that such an integration can eliminate wave reflections. These findings open the possibility of using GMR STOs in magnetic field sensing and microwave source applications.

QC 20151112

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Perumana, Bevin George. "Low-power CMOS front-ends for wireless personal area networks". Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/26712.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.
Committee Chair: Laskar, Joy; Committee Member: Chakraborty, Sudipto; Committee Member: Chang, Jae Joon; Committee Member: Divan, Deepakraj; Committee Member: Kornegay, Kevin; Committee Member: Tentzeris, Emmanouil. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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Aja, Abelán Beatriz. "Amplificadores de banda ancha y bajo ruido basados en tecnología de GaAs para aplicaciones de radiometría". Doctoral thesis, Universidad de Cantabria, 2007. http://hdl.handle.net/10803/10664.

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En esta Tesis se ha realizado análisis, diseño y caracterización de los amplificadores de bajoruido y banda ancha en tecnología de GaAs PHEMT con aplicación a los módulos posteriores delradiómetro del instrumento de baja frecuencia del satélite Planck. La Tesis se compone de las siguientes partes:- Introducción y estudio del funcionamiento del radiómetro del instrumento de baja frecuencia de Planck.- Diseño y caracterización de amplificadores de bajo ruido utilizando tecnología de GaAs. Se presentan diseños MMIC en la banda Ka y en la banda Q, y un diseño MIC en la banda Q.- Diseño y construcción de los módulos posteriores en las bandas de 30 y 44 GHz. Se presentan varios prototipos fabricados en ambas bandas, así como medidas de cada uno de los subsistemas que los forman.- Desarrollo de técnicas de medida para receptores de banda ancha con detección directa y su aplicación a la caracterización de los módulos posteriores, mostrando el funcionamiento de los prototipos representativos para las dos bandas de frecuencia.- Integración de los módulos posteriores con los módulos frontales y presentación de algunos de los resultados de medida de los radiómetros completos.
This Thesis deals with the analysis, design and characterization of broadband low noise amplifiersin GaAs PHEMT technology with application to the radiometer Back-End Modules for the Planck Low Frequency Instrument (LFI). The Thesis is composed of the next parts:- Introduction and study about the radiometer of the Planck low frequency instrument.- Design and characterization of low noise amplifiers using GaAs technology. Ka-band MMIC designs and Q-band MMIC and a MIC design are presented.- Design and assembly of the 30 and 44 GHz back-end modules. Several prototypes have been manufactured in both frequency bands and the most representative test results of each subsystem are presented.- Development of measurement techniques for broadband direct detection receivers and their application to the characterization of the back-end modules. Performance of representative prototypes in both frequency bands is included.- Integration of the back end modules and front end modules and significant results of the tests for a radiometer in each frequency band.

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42

Coustou, Anthony. "Conception et caractérisation de circuits intégrés en technologie BiCMOS SiGe pour application de télécommunication en bande X". Phd thesis, Université Paul Sabatier - Toulouse III, 2001. http://tel.archives-ouvertes.fr/tel-00131800.

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Les progrès de la technologie silicium germanium (SiGe) suscitent sa possible utilisation dans les applications à haute fréquence. Les travaux décrit dans ce mémoire visent à étudier les potentialités de cette technologie pour la réalisation de circuits intégrés monolithiques (MMIC) faibles bruit dans la bande de 10 GHz. Ce mémoire est articulé autour de trois chapitres. Le premier rappelle les contraintes auxquelles doit répondre un transistor bipolaire afin d'être utilisable dans les circuits RF millimétriques. La technologie qu'à développé STMicroelectronics pour ce domaine d'application est ensuite présentée. Enfin, le travail de caractérisation qui a été réalisé afin de valider le comportement des modèles que nous allons utiliser pour concevoir des circuits RF est présenté. Le second chapitre est consacré à la conception de circuits amplificateurs à faible bruit. La méthode de travail ainsi que les topologies de circuits sont présentées. Le résultat des caractérisations effectuées est ensuite présenté. Nous terminons en concluant au sujet des performances en terme de consommation, linéarité, gain et facteur de bruit des différents circuits. Le troisième chapitre aborde la conception de sources radiofréquence à faible bruit de phase. Les différentes topologies de circuits que nous avons étudiés sont présentées, ce qui nous a permis de mettre en évidence les topologies offrant les meilleures performances. Enfin, une technique basée sur le principe de dégénérescence de bruit, est également présentée. Ce travail nous a permis d'intégrer sur un circuit MMIC, autour d'un circuit oscillateur de type Colpitts, un dispositif réducteur de bruit. Les résultats théoriques de cette étude ont montré l'efficacité de cette méthode.

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Desai, Dileep Reddy. "Analog Non-Linear Multi-Variable Function Evaluation By Piece-wise Linear Approximation". University of Akron / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=akron1280110386.

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Aissi, Mohammed. "Conception de circuits WLAN 5 GHZ à résonateurs BAW-FBAR intégrés : oscillateurs et amplificateurs filtrants". Phd thesis, Université Paul Sabatier - Toulouse III, 2006. http://tel.archives-ouvertes.fr/tel-00127363.

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Les travaux de recherche présentés dans cette thèse consistent principalement en la conception de fonctions intégrées radiofréquences BiCMOS SiGe exploitant des résonateurs à ondes acoustiques de volume FBAR. Contrairement aux techniques actuelles rencontrées dans l'industrie qui consistent à réaliser des filtres et des résonateurs discrets et à les associer par la suite avec les circuits actifs des émetteurs-récepteurs au niveau du boîtier, nos résonateurs sont directement réalisés sur le substrat silicium des circuits actifs RF par une technique appelée intégration " above-IC ". Avec cette méthode d'intégration, les parasites et la modélisation associés aux microsoudures (Wire Bonding) sont éliminés. Elle permet aussi de se passer des circuits d'interface et d'adaptation nécessaires dans le cas de filtres RF discrets. Ceci permet de réduire considérablement la consommation et le volume des systèmes. Des amplificateurs faible bruit filtrants et des oscillateurs visant le standard WLAN IEEE 802.11a ont ainsi été implantés en utilisant cette technique d'intégration "above IC". Les circuits obtenus sont très compacts, et leurs performances, notamment celles des oscillateurs, sont à l'état de l'art. Par ailleurs, des amplificateurs faible bruit et des VCO LC SiGe intégrés pour application WLAN 5GHz sont également présentés et leurs techniques d'optimisation sont données.

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Akbay, Selim Sermet. "Constraint-driven RF test stimulus generation and built-in test". Diss., Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/33913.

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With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.

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46

Wilson, James Edward. "Design techniques for first pass silicon in SOC radio transceivers". Columbus, Ohio : Ohio State University, 2007. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1180555088.

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El, Ghouli Salim. "UTBB FDSOI mosfet dynamic behavior study and modeling for ultra-low power RF and mm-Wave IC Design". Thesis, Strasbourg, 2018. http://www.theses.fr/2018STRAD015/document.

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Ce travail de recherche a été principalement motivé par les avantages importants apportés par la technologie UTBB FDSOI aux applications analogiques et RF de faible puissance. L'objectif principal est d'étudier le comportement dynamique du transistor MOSFET du type UTBB FDSOI et de proposer des modèles prédictifs et des recommandations pour la conception de circuits intégrés RF, en mettant un accent particulier sur le régime d'inversion modérée. Après une brève analyse des progrès réalisés au niveau des architectures du transistor MOSFET, un état de l’art de la modélisation du transistor MOSFET UTBB FDSOI est établi. Les principaux effets physiques impliqués dans le transistor à double grille avec une épaisseur du film de 7 nm sont passés en revue, en particulier l’impact de la grille arrière, à l’aide de mesures et de simulations TCAD. La caractéristique gm/ID en basse fréquence et la caractéristique ym/ID proposée pour la haute fréquence sont étudiées et utilisées dans une conception analogique efficace. Enfin, le modèle NQS haute fréquence proposé reproduit les mesures dans toutes les conditions de polarisation y compris l’inversion modérée jusqu’à 110 GHz
This research work has been motivated primarily by the significant advantages brought about by the UTBB FDSOI technology to the Low power Analog and RF applications. The main goal is to study the dynamic behavior of the UTBB FDSOI MOSFET in light of the recent technology advances and to propose predictive models and useful recommendations for RF IC design with particular emphasis on Moderate Inversion regime. After a brief review of progress in MOSFET architectures introduced in the semiconductor industry, a state-of-the-art UTBB FDSOI MOSFET modeling status is compiled. The main physical effects involved in the double gate transistor with a 7 nm thick film are reviewed, particularly the back gate impact, using measurements and TCAD. For better insight into the Weak Inversion and Moderate Inversion operations, both the low frequency gm/ID FoM and the proposed high frequency ym/ID FoM are studied and also used in an efficient first-cut analog design. Finally, a high frequency NQS model is developed and compared to DC and S-parameters measurements. The results show excellent agreement across all modes of operation including very low bias conditions and up to 110 GHz

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Moon, Sung Tae. "Design of high performance frequency synthesizers in communication systems". Texas A&M University, 2005. http://hdl.handle.net/1969.1/2329.

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Frequency synthesizer is a key building block of fully-integrated wireless communication systems. Design of a frequency synthesizer requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. This dissertation presents a full cycle of the synthesizer design procedure starting from the interpretation of standards to the testing and measurement results. A new methodology of interpreting communication standards into low level circuit specifications is developed to clarify how the requirements are calculated. A detailed procedure to determine important design variables is presented incorporating the fundamental theory and non-ideal effects such as phase noise and reference spurs. The design procedure can be easily adopted for different applications. A BiCMOS frequency synthesizer compliant for both wireless local area network (WLAN) 802.11a and 802.11b standards is presented as a design example. The two standards are carefully studied according to the proposed standard interpretation method. In order to satisfy stringent requirements due to the multi-standard architecture, an improved adaptive dual-loop phase-locked loop (PLL) architecture is proposed. The proposed improvements include a new loop filter topology with an active capacitance multiplier and a tunable dead zone circuit. These improvements are crucial for monolithic integration of the synthesizer with no off-chip components. The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time performance while making it more suitable for monolithic integration. It opens a new possibility of using an integer-N architecture for various other communication standards, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption.

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Ara?jo, Katia Cristiane Vasconcelos de. "A experi?ncia da crian?a com a droga :caracter?sticas do uso e circunst?ncias familiares". Universidade Federal do Rio Grande do Norte, 2006. http://repositorio.ufrn.br:8080/jspui/handle/123456789/17466.

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Made available in DSpace on 2014-12-17T15:38:50Z (GMT). No. of bitstreams: 1 KatiaCVAB.pdf: 1446099 bytes, checksum: 1566a0ab8e73fa2d8681f190faa7c2ff (MD5) Previous issue date: 2006-05-19
Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior
The study is a reflexion of the use of drugs among children, pointing that as one of the most serious social problem nowadays. Customize the abuse of drugs reflecting on the childhood and the family s influence of the problem of the children that use drugs, is the main objective of this thesis. Choosing the qualitative method of research, the investigation starts with the reports of the children and mothers assisted at Centro de Refer?ncia e Apoio ? Crian?a e ao Adolescente Usu?rios de Drogas, program of specialized assistance of 1? Vara da Inf?ncia e da Juventude de Natal/RN. The research was done through semi-structured interviews, in a total of six subjects: three children and their respective mothers. Through the reports of the subjects, it is brought theorical reflexions that illustrates their perceptions and conceptions about topics like the usage of drugs, the circumstances the usage of drugs was started, the family s structure and dynamic, the situation on the streets, and other factors that affect the development of a child in her/his environment. It is proved that the usage of drugs in Brazil, problem that has been increasing the number of children affected by, is a multi faceted and complex phenomenon but some factors of social and family risks deserve to be pointed out like the manner of support future actions in the prevention area
O estudo faz uma reflex?o sobre o uso de drogas entre crian?as situando-o como um dos mais graves problemas sociais da atualidade. Caracterizar o abuso de drogas, refletindo sobre sua condi??o de inf?ncia e investigar a influ?ncia da fam?lia no desencadeamento do problema nestas crian?as, se configura como o objetivo central deste trabalho. Optando pelo m?todo de pesquisa qualitativa, a investiga??o se d? a partir dos relatos de crian?as e m?es atendidas pelo Centro de Refer?ncia e Apoio ? Crian?a e ao Adolescente Usu?rios de Drogas, programa de atendimento especializado da 1? Vara da Inf?ncia e da Juventude de Natal/RN. Os dados foram coletados atrav?s de entrevistas semi-estruturadas, com um total de seis sujeitos, sendo tr?s crian?as e suas respectivas m?es. Atrav?s das falas e depoimentos dos sujeitos, busca-se trazer reflex?es te?ricas que ilustrem as percep??es e concep??es deles acerca de temas como o uso de drogas, as circunst?ncias em que se iniciou o uso, a estrutura e din?mica familiares, a situa??o de rua, e outros fatores que comprometem o desenvolvimento da crian?a no meio em que vive. Comprova-se que o uso de drogas no Brasil, problema que acomete cada vez um maior n?mero de crian?as, ? um fen?meno multifacetado e complexo, por?m, alguns fatores de risco sociais e familiares merecem destaque como forma de subsidiar futuras interven??es na ?rea de preven??o

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Shapero, Samuel Andre. "Configurable analog hardware for neuromorphic Bayesian inference and least-squares solutions". Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/51719.

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Sparse approximation is a Bayesian inference program with a wide number of signal processing applications, such as Compressed Sensing recovery used in medical imaging. Previous sparse coding implementations relied on digital algorithms whose power consumption and performance scale poorly with problem size, rendering them unsuitable for portable applications, and a bottleneck in high speed applications. A novel analog architecture, implementing the Locally Competitive Algorithm (LCA), was designed and programmed onto a Field Programmable Analog Arrays (FPAAs), using floating gate transistors to set the analog parameters. A network of 6 coefficients was demonstrated to converge to similar values as a digital sparse approximation algorithm, but with better power and performance scaling. A rate encoded spiking algorithm was then developed, which was shown to converge to similar values as the LCA. A second novel architecture was designed and programmed on an FPAA implementing the spiking version of the LCA with integrate and fire neurons. A network of 18 neurons converged on similar values as a digital sparse approximation algorithm, with even better performance and power efficiency than the non-spiking network. Novel algorithms were created to increase floating gate programming speed by more than two orders of magnitude, and reduce programming error from device mismatch. A new FPAA chip was designed and tested which allowed for rapid interfacing and additional improvements in accuracy. Finally, a neuromorphic chip was designed, containing 400 integrate and fire neurons, and capable of converging on a sparse approximation solution in 10 microseconds, over 1000 times faster than the best digital solution.

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