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Artykuły w czasopismach na temat "Itanium"
Šetar, Domen. "IZUM itanium workshop". Organizacija znanja 8, nr 2 (2003): 112–13. http://dx.doi.org/10.3359/oz0302112.
Pełny tekst źródłaSharangpani, H., i H. Arora. "Itanium processor microarchitecture". IEEE Micro 20, nr 5 (2000): 24–43. http://dx.doi.org/10.1109/40.877948.
Pełny tekst źródłaGreer, Bruce, John Harrison, Greg Henry, Wei Li i Peter Tang. "Scientific Computing on the Itanium® Processor". Scientific Programming 10, nr 4 (2002): 329–37. http://dx.doi.org/10.1155/2002/193478.
Pełny tekst źródłaCrawford, J. "Introducing the itanium processors". IEEE Micro 20, nr 5 (wrzesień 2000): 9–11. http://dx.doi.org/10.1109/mm.2000.877946.
Pełny tekst źródłaMcNairy, C., i D. Soltis. "Itanium 2 processor microarchitecture". IEEE Micro 23, nr 2 (marzec 2003): 44–55. http://dx.doi.org/10.1109/mm.2003.1196114.
Pełny tekst źródłaFumio Aono i Masayuke Kimura. "The AzusA 16-way itanium server". IEEE Micro 20, nr 5 (2000): 54–60. http://dx.doi.org/10.1109/40.877950.
Pełny tekst źródłaSamaras, W. A., N. Cherukuri i S. Venkataraman. "The IA-64 Itanium processor cartridge". IEEE Micro 21, nr 1 (2001): 82–89. http://dx.doi.org/10.1109/40.903064.
Pełny tekst źródłaSnavely, N., S. Debray i G. R. Andrews. "Unpredication, unscheduling, unspeculation: reverse engineering Itanium executables". IEEE Transactions on Software Engineering 31, nr 2 (luty 2005): 99–115. http://dx.doi.org/10.1109/tse.2005.27.
Pełny tekst źródłaNaffziger, S. D., G. Colon-Bonet, T. Fischer, R. Riedlinger, T. J. Sullivan i T. Grutkowski. "The implementation of the Itanium 2 microprocessor". IEEE Journal of Solid-State Circuits 37, nr 11 (listopad 2002): 1448–60. http://dx.doi.org/10.1109/jssc.2002.803943.
Pełny tekst źródłaIikbahar, A., S. Venkataraman i H. Muljono. "Itanium/sup TM/ Processor system bus design". IEEE Journal of Solid-State Circuits 36, nr 10 (2001): 1565–73. http://dx.doi.org/10.1109/4.953486.
Pełny tekst źródłaRozprawy doktorskie na temat "Itanium"
Sharma, Saurabh. "WELD FOR ITANIUM PROCESSOR". NCSU, 2002. http://www.lib.ncsu.edu/theses/available/etd-11182002-120028/.
Pełny tekst źródłaBjerke, Håvard K. F. "HPC Virtualization with Xen on Itanium". Thesis, Norwegian University of Science and Technology, Department of Computer and Information Science, 2005. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9263.
Pełny tekst źródłaThe Xen Virtual Machine Monitor has proven to achieve higher efficiency in virtualizing the x86 architecture than competing x86 virtualization technologies. This makes virtualization on the x86 platform more feasible in High-Performance and mainframe computing, where virtualization can offer attractive solutions for managing resources between users. Virtualization is also attractive on the Itanium architecture. Future x86 and Itanium computer architectures include extensions which make virtualization more efficient. Moving to virtualizing resources through Xen may ready computer centers for the possibilities offered by these extensions. The Itanium architecture is ``uncooperative'' in terms of virtualization. Privilege-sensitive instructions make full virtualization inefficient and impose the need for para-virtualization. Para-virtualizing Linux involves changing certain native operations in the guest kernel in order to adapt it to the Xen virtual architecture. Minimum para-virtualizing impact on Linux is achieved by, instead of replacing illegal instructions, trapping them by the hypervisor, which then emulates them. Transparent para-virtualization allows the same Linux kernel binary to run on top of Xen and on physical hardware. Itanium region registers allow more graceful distribution of memory between guest operating systems, while not disturbing the Translation Lookaside Buffer. The Extensible Firmware Interface provides a standardized interface to hardware functions, and is easier to virtualize than legacy hardware interfaces. The overhead of running para-virtualized Linux on Itanium is reasonably small and measured to be around 4.9 %. Also, the overhead of running transparently para-virtualized Linux on physical hardware is reasonably small compared to non-virtualized Linux.
Wienand, Ian Raymond Computer Science & Engineering Faculty of Engineering UNSW. "Transparent large-page support for Itanium linux". Publisher:University of New South Wales. Computer Science & Engineering, 2008. http://handle.unsw.edu.au/1959.4/41021.
Pełny tekst źródłaTayeb, Jamel. "Optimisation des performances et de la consommation de puissance électrique pour architecture Intel Itanium/EPIC". Valenciennes, 2008. http://ged.univ-valenciennes.fr/nuxeo/site/esupversions/9eed6aef-dfaf-4a17-883f-d217a1d9a000.
Pełny tekst źródłaThis thesis proposes, in its first part, to extend the EPIC architecture of the Itanium processor family by providing a hardware stack. The principal idea defended here is that it is possible to close the existing performance gap between generic architectures and application specific designs to run virtual machines (FORTH,. NET, Java, etc). With this intention, we propose to reallocate dynamically a subset of the EPIC architecture’s resources to implement a hardware evaluation stack. Two implementations are proposed, both non-intrusive and compatible with existing binary codes. The fundamental difference between these stacks lies in their manager: software or hardware. The hardware controlled evaluation stack offers support for advanced functions such as the support of strongly typed evaluation stacks required by. NET’s CIL. Thus, we propose a single pass CIL binary translator into EPIC binary, using the hardware evaluation stack. In the second part of this thesis, we studied the energy efficiency of software applications. First, we defined a methodology and developed tools to measure the energy consumption and the useful work provided by the software. In a second time, we engaged the study of source code transformation rules in order to reduce/control the quantity of consumed energy by the software
Varanavičius, Andrius. "Kompiliatorių optimizavimas IA-64 architektūroje". Master's thesis, Lithuanian Academic Libraries Network (LABT), 2010. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2009~D_20101125_190732-76081.
Pełny tekst źródłaThis thesis deeply explored Intel Itanium architecture features that improve a code generated by compiler. Compiler optimizations which are tuned to this architecture are also described. Accomplished research showed that there were several types of optimizations which can be improved on IA-64 architecture. Firstly, optimizations which are dependent on architecture can be optimized using predication and speculation or other unique IA-64 features. Secondly, optimizations that are undependable from traditional architecture can be improved using more aggressive compilation controllable parameters than they are by default. Loop optimizations were chosen for final research. Research proved that changing values of these parameters from default can improve program performance.
Carribault, Patrick. "Contribution to the compilation of irregular programs for complex architectures". Versailles-St Quentin en Yvelines, 2007. http://www.theses.fr/2007VERS0012.
Pełny tekst źródłaContribution to the Compilation of Irregular Programs for Complex ArchitecturesMulticore architectures are ubiquitous in general purpose and embedded systems. Modern processors execute several instruction flows (threads) increasing the parallelism and accommodating for resource stalls. Both the execution of a thread and its interaction with the others shape the overall performance of an application. Thus, an accurate exploitation of a single core is mandatory: it leads to the necessity to discover the instruction-level parallelism (ILP) within an instruction flow. This thesis focuses on the monocore optimization of irregular codes hoseparallelism is "hidden" behind complex control flow. We designedtransformations to increase their ILP: Deep Jam converting coarse-grain parallelism, decision tree reshaping and an instruction-scheduling framework unifying data dependences and complex resource constraints. Everytransformation leads to significant speedups on a wide issue architecture(Itanium), compared to state-of-the-art techniques and compilers
Quiñones, Moreno Eduardo. "Predicated execution and register windows for out-of-order processors". Doctoral thesis, Universitat Politècnica de Catalunya, 2008. http://hdl.handle.net/10803/6023.
Pełny tekst źródłaIn-order processors specially benefit from using both ISA extensions to overcome the limitations that control dependences and memory hierarchy impose on static scheduling. Predicate execution allows to move control dependence instructions past branches. Register windows reduce the amount of memory operations across procedure calls. Although if-conversion and register windows techniques have not been exclusively developed for in-order processors, their use for out-of-order processors has been studied very little. In this thesis we show that the uses of if-conversion and register windows introduce new performance opportunities and new challenges to face in out-of-order processors.
The use of if-conversion in out-of-order processors helps to eliminate hard-to-predict branches, alleviating the severe performance penalties caused by branch mispredictions. However, the removal of some conditional branches by if-conversion may adversely affect the predictability of the remaining branches, because it may reduce the amount of correlation information available to the branch predictor. Moreover, predicate execution in out-of-order processors has to deal with two performance issues. First, multiple definitions of the same logical register can be merged into a single control flow, where each definition is guarded with a different predicate. Second, instructions whose guarding predicate evaluates to false consume unnecessary resources. This thesis proposes a branch prediction scheme based on predicate prediction that solves the three problems mentioned above. This scheme, which is built on top of a predicated ISA that implement a compare-and-branch model such as the one considered in this thesis, has two advantages: First, the branch accuracy is improved because the correlation information is not lost after if-conversion and the mechanism we propose permits using the computed value of the branch predicate when available, achieving 100% of accuracy. Second it avoids the predicate out-of-order execution problems.
Regarding register windows, we propose a mechanism that reduces physical register requirements of an out-of-order processor to the bare minimum with almost no performance loss. The mechanism is based on identifying which architectural registers are in use by current in-flight instructions. The registers which are not in use, i.e. there is no in-flight instruction that references them, can be early released.
In this thesis we propose a very efficient and low-cost hardware implementation of predicate execution and register windows that provide important benefits to out-of-order processors.
Khan, Minhaj Ahmad. "Techniques de spécialisation de code pour des architectures à hautes performances". Versailles-St Quentin en Yvelines, 2008. http://www.theses.fr/2008VERS0032.
Pełny tekst źródłaDe nombreuses applications sont incapables d'utiliser les performances crêtes offertes par des architectures modernes comme l'Itanium et Pentium-IV. Cela rend critique les optimisations de code réalisée par les compilateurs. Parmis toutes les optimisations réalisées par les compilateurs, la spécialisation de code, qui fournit aux compilateurs les valeurs des paramètres importants dans le code, est très efficace. La spécialisation statique a comme défault de produire une grande taille du code, appelée, l'explosion du code. Cette grande taille implique des défaults de caches et des coûts de branchements. Elle même impose des contraintes sur d'autres optimisations. Tous ces effets rendent nécessaire de spécialiser le code dynamiquement. La spécialisation de code est donc effectué par lescompilateurs/specialiseurs dynamiques, qui générent le code àl'exécution. Ces approches ne sont pas toujours bénéfique puisque l'exécution doit subir un grand surcoût de géneration à l'exécution qui peut détériorer la performance. De plus, afin d'être amorti, ce coût exige plusieurs invocations du même code. Visant à améliorer les performances des applications complexes, cettethèse propose différentes stratégies pour la spécialisation du code. En utilisant la compilation statique, dynamique et itérative, nous ciblons les problèmes d'explosion de la taille du code et le surcoût en temps induit par la génération du code à l'exécution. Notre "Spécialisation Hybride" génère des versions équivalentes du code après l'avoir specialisé statiquement. Au lieu de conserver toutes les versions, l'une de ces versions peut être utilisée comme un template dont les instructions sont modifiées pendant exécution afin d'être adaptée à d'autres versions. La performance est améliorée puisque le code est spécialisé au moment de la compilation statique. La spécialisation dynamique est donc limitée à la modification d'un petit nombre d'instructions. Différentes variantes de ces approches peuvent améliorer laspécialisation en choisissant des variables adéquates, en diminuant le nombre de compilations et en réduisant la fréquence de laspécialisation dynamique. Notre approche "Spécialisation Itérative" est en mesure d'optimiser les codes régulier en obtenant plusieurs classes optimales du code spécialisé au moment de la compilation statique. En suite, une transformation itérative est appliquée sur le code afin de bénéficier des classes optimales générées et obtenir la meilleure version. Les expérimentations ont été effectuées sur des architectures IA-64 et Pentium- IV, en utilisant les compilateurs gcc et icc. Les approches proposées (Spécialisation Hybride et Itérative), nous permettent d'obtenir une amélioration significative pour plusieurs benchmarks, y compris ceux de SPEC, FFTW et ATLAS
Vieira, Mirna Lygia [UNESP]. "Imagem turística de Itanhém, litoral sul paulista". Universidade Estadual Paulista (UNESP), 1997. http://hdl.handle.net/11449/104442.
Pełny tekst źródłaEste trabalho chama a atenção para o papel das imagens no desenvolvimento do turismo, partindo do pressuposto que, sem imagens nítidas e duradouras, as localidades não florescem, ficando restritas a um estado letárgico. Procurou-se trabalhar com os enunciados de Miossec, geógrafo tunisiano, que reconhece no turismo três imagens: global, tradicional e atual. Por imagem global entende-se a necessidade do ser humano em sair do seu mundo cotidiano e rotineiro; por imagem tradicional, aquela fixada pela cultura através dos tempos; e, finalmente, por imagem atual, aquela ditada pelos padrões de beleza contemporâneos. Dessa forma, escolheu-se a cidade de Itanhaém para desenvolver uma pesquisa que pudesse focalizar essas três imagens enunciadas. Itanhaém, localidade do litoral sul paulista que possui antecedentes históricos, é meio de atração permanente, com o mar e suas praias. Além disso, é tombada pelo Patrimônio Histórico Cultural, legitimando sua condição de cidade histórica e turística.
This work call attention to the role of images in tourism development, assuming that without lasting and clear images, the locations do not bloom, being restricted to a lethargic state. We attempted to work with the enunciations of Miossec, Tunisian geographer who recognizes three images in tourism: global, traditional and recent. Global image is understood as the necessity of the human being to leave his daily and ordinary world; traditional image is that fixed by culture through time; and finally, recent image is the one dictated by the contemporary beauty standards.This way, the city of Itanhaém was chosen as the site to develop a research focusing on the three images above mentioned. Itanhaém, located in the south coastal regional of the state of São Paulo, has numerous historical antecedents, it is a place of permanent touristic attraction with its beaches. Besides, it is a cultural and historic patrimony, legitimizing its condition of historic and touristic city.
Vieira, Mirna Lygia. "Imagem turística de Itanhém, litoral sul paulista /". Rio Claro : [s.n.], 1997. http://hdl.handle.net/11449/104442.
Pełny tekst źródłaBanca: Juergen Richard Langenbuch
Banca: Lineu Bley
Banca: Herbe Xavier
Banca: Marlene Teresinha de Muno Colesanti
Resumo: Este trabalho chama a atenção para o papel das imagens no desenvolvimento do turismo, partindo do pressuposto que, sem imagens nítidas e duradouras, as localidades não florescem, ficando restritas a um estado letárgico. Procurou-se trabalhar com os enunciados de Miossec, geógrafo tunisiano, que reconhece no turismo três imagens: global, tradicional e atual. Por imagem global entende-se a necessidade do ser humano em sair do seu mundo cotidiano e rotineiro; por imagem tradicional, aquela fixada pela cultura através dos tempos; e, finalmente, por imagem atual, aquela ditada pelos padrões de beleza contemporâneos. Dessa forma, escolheu-se a cidade de Itanhaém para desenvolver uma pesquisa que pudesse focalizar essas três imagens enunciadas. Itanhaém, localidade do litoral sul paulista que possui antecedentes históricos, é meio de atração permanente, com o mar e suas praias. Além disso, é tombada pelo Patrimônio Histórico Cultural, legitimando sua condição de cidade histórica e turística.
Abstract: This work call attention to the role of images in tourism development, assuming that without lasting and clear images, the locations do not bloom, being restricted to a lethargic state. We attempted to work with the enunciations of Miossec, Tunisian geographer who recognizes three images in tourism: global, traditional and recent. Global image is understood as the necessity of the human being to leave his daily and ordinary world; traditional image is that fixed by culture through time; and finally, recent image is the one dictated by the contemporary beauty standards.This way, the city of Itanhaém was chosen as the site to develop a research focusing on the three images above mentioned. Itanhaém, located in the south coastal regional of the state of São Paulo, has numerous historical antecedents, it is a place of permanent touristic attraction with its beaches. Besides, it is a cultural and historic patrimony, legitimizing its condition of historic and touristic city.
Doutor
Książki na temat "Itanium"
Gwennap, Linley. Intel's Itanium and IA-64: Technology and market forecast. Wyd. 2. Sunnyvale, CA: MicroDesign Resources, 2000.
Znajdź pełny tekst źródłaJerry, Huck, red. Itanium rising: Breaking through Moore's second law of computing power. Upper Saddle River, N.J: Prentice Hall PTR, 2003.
Znajdź pełny tekst źródłaLinux on HP Integrity Servers: System administration for Itanium-based systems. Upper Saddle River, NJ: Prentice Hall PTR, 2005.
Znajdź pełny tekst źródłaMurādābādī, Hullaṛa. Itanī un̐cī mata choṛo. Nayī Dillī: Pustakāyana, 1996.
Znajdź pełny tekst źródłaNaumovsky, Yosef. ha-Regesh tamid itanu. [Israel]: Yosef Publishing, 2006.
Znajdź pełny tekst źródłaMāheśvarī, Baṃśī. Āvāza itanī pahacānī ki lagī apanī. Bīkānera: Vāgdevī Prakāśana, 1988.
Znajdź pełny tekst źródłaSharviṭ, Elʻazar. Itanu poh: Shirim ṿe-soneṭot. Tel-Aviv: ʻEḳed, 1986.
Znajdź pełny tekst źródłaSharviṭ, Elʻazar. Itanu poh: Shirim ṿe-soneṭot. Tel Aviv: ʻEḳed, 1986.
Znajdź pełny tekst źródłaDiasporic narratives of sexuality : identity formation among Itanian-Swedish women. Stockholm: Acta Universitatis Stockholmiensis, 2007.
Znajdź pełny tekst źródłaAmrami, J. ha-Devarim gedolim hem me-itanu: Pirḳe ʻavar. Tel-Aviv: Hadar, 1994.
Znajdź pełny tekst źródłaCzęści książek na temat "Itanium"
Tan, Chih Jeng Kenneth, David Hagan i Matthew Dixon. "A Performance Comparison of Matrix Solvers on Compaq Alpha, Intel Itanium, and Intel Itanium II Processors". W Computational Science and Its Applications — ICCSA 2003, 818–27. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/3-540-44839-x_86.
Pełny tekst źródłaHigham, Lisa, LillAnne Jackson i Jalal Kawash. "Programmer-Centric Conditions for Itanium Memory Consistency". W Distributed Computing and Networking, 58–69. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11947950_7.
Pełny tekst źródłaFurukawa, Kazuyoshi, Masahiko Takenaka i Kouichi Itoh. "A Fast RSA Implementation on Itanium 2 Processor". W Information and Communications Security, 507–18. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11935308_36.
Pełny tekst źródłaDesai, Darshan, Gerolf F. Hoflehner, Arun Kejariwal, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum i Cameron McNairy. "Performance Characterization of Itanium® 2-Based Montecito Processor". W Computer Performance Evaluation and Benchmarking, 36–56. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-540-93799-9_3.
Pełny tekst źródłaLi, Wenlong, Haibo Lin, Yu Chen i Zhizhong Tang. "Increasing Software-Pipelined Loops in the Itanium-Like Architecture". W Parallel and Distributed Processing and Applications, 947–51. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30566-8_108.
Pełny tekst źródłaDouillet, Alban, José Nelson Amaral i Guang R. Gao. "Fine-Grain Stacked Register Allocation for the Itanium Architecture". W Languages and Compilers for Parallel Computing, 344–61. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11596110_23.
Pełny tekst źródłaDonath, S., J. Götz, C. Feichtinger, K. Iglberger i U. Rüde. "waLBerla: Optimization for Itanium-based Systems with Thousands of Processors". W High Performance Computing in Science and Engineering, Garching/Munich 2009, 27–38. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-13872-0_3.
Pełny tekst źródłaLin, Haibo, Wenlong Li i Zhizhong Tang. "Overcoming Static Register Pressure for Software Pipelining in the Itanium Architecture". W Lecture Notes in Computer Science, 109–13. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-39425-9_12.
Pełny tekst źródłaYang, Yue, Ganesh Gopalakrishnan, Gary Lindstrom i Konrad Slind. "Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT". W Lecture Notes in Computer Science, 81–95. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-39724-3_9.
Pełny tekst źródłaHigham, Lisa, LillAnne Jackson i Jalal Kawash. "Capturing Register and Control Dependence in Memory Consistency Models with Applications to the Itanium Architecture". W Lecture Notes in Computer Science, 164–78. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11864219_12.
Pełny tekst źródłaStreszczenia konferencji na temat "Itanium"
Desai, Utpal, Simon Tam, Robert Kim, Ji Zhang i Stefan Rusu. "Itanium processor clock design". W the 2000 international symposium. New York, New York, USA: ACM Press, 2000. http://dx.doi.org/10.1145/332357.332380.
Pełny tekst źródłaGreer, Bruce, John Harrison, Greg Henry, Wei Li i Peter Tang. "Scientific computing on the Itanium#8482; processor". W the 2001 ACM/IEEE conference. New York, New York, USA: ACM Press, 2001. http://dx.doi.org/10.1145/582034.582075.
Pełny tekst źródłaRichfield, Steve. "Dealing with the "itanium effect" (abstract only)". W the 19th ACM/SIGDA international symposium. New York, New York, USA: ACM Press, 2011. http://dx.doi.org/10.1145/1950413.1950466.
Pełny tekst źródłaCornea, Marius, John Harrison i Ping Tak Peter Tang. "Intel® Itanium® floating-point architecture". W the 2003 workshop. New York, New York, USA: ACM Press, 2003. http://dx.doi.org/10.1145/1275521.1275526.
Pełny tekst źródłaBelady, Christian, Gary Williams i Shaun Harris. "MX2 Processor Module: Twice the Processors in Half the Volume". W ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/ipack2005-73321.
Pełny tekst źródłaWunderlich, Roland E., i James C. Hoe. "In-system FPGA prototyping of an itanium microarchitecture". W Proceeding of the 2004 ACM/SIGDA 12th international symposium. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/968280.968346.
Pełny tekst źródłaStinson, Jason, i Stefan Rusu. "A 1.5GHz third generation itanium® 2 processor". W the 40th conference. New York, New York, USA: ACM Press, 2003. http://dx.doi.org/10.1145/775832.776011.
Pełny tekst źródłaHigham, Lisa, i LillAnne Jackson. "Translating between itanium and sparc memory consistency models". W the eighteenth annual ACM symposium. New York, New York, USA: ACM Press, 2006. http://dx.doi.org/10.1145/1148109.1148138.
Pełny tekst źródłaDeLano, Eric. "Tukwila - a quad-core Intel® Itanium® processor". W 2008 IEEE Hot Chips 20 Symposium (HCS). IEEE, 2008. http://dx.doi.org/10.1109/hotchips.2008.7476561.
Pełny tekst źródłaStackhouse, B., B. Cherkauer, M. Gowan, P. Gronowski i C. Lyles. "A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor". W 2008 IEEE International Solid-State Circuits Conference. IEEE, 2008. http://dx.doi.org/10.1109/isscc.2008.4523072.
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