Rozprawy doktorskie: „Integrated Heterogeneous Systems”

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Papistas, Ioannis. "Design methodologies for heterogeneous 3-D integrated systems". Thesis, University of Manchester, 2018. https://www.research.manchester.ac.uk/portal/en/theses/design-methodologies-for-heterogeneous-3d-integrated-systems(1df2e366-34e1-460c-8534-690ea5edaedb).html.

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Design techniques for heterogeneous three-dimensional (3-D) integrated circuits are developed in this thesis. Heterogeneous 3-D integration is a platform for multifunctional, high performance, and low power electronics. For the advancement of heterogeneous 3-D ICs, contactless solutions are investigated to implement inter-tier communication between tiers manufactured with disparate processes and heterogeneous technologies. Two challenges for the development of contactless inter-tier communication are addressed, the design of energy efficient, heterogeneous inductive link transceivers and the impact of crosstalk noise due to the on-chip spiral inductors. Inter-tier communication between circuits fabricated with disparate technologies requires transceivers capable of operating at dissimilar voltages. A low power transceiver design methodology is proposed exploiting the diï¬erence in the core voltage between disparate manufacturing processes in a 3-D system in package. A transceiver is designed to provide inter-tier communication between a sensing layer, designed in a commercial 0.35 Âμm process and a processing layer, designed in an advanced 65 nm process. A significant gain in the power consumed by the transceiver is shown compared to equivalent state-of-the-art prototypes, profiting by the tradeoff between the core voltage and sensing ability of the transceiver circuit in each process. Due to their wireless nature, however the use of inductive links introduces crosstalk noise due to the coupling between the on-chip inductor and on-chip interconnects in the vicinity of the inductor. The noise caused by the inductor on the power distribution network of an integrated system is explored, analysed, and modelled through electromagnetic simulations. The spatial distribution of the noise is described for several power distribution topologies to determine the preferred placement solution for the power and ground network in the vicinity of the inductor, considering the impact on other sources of noise, such as the resistive drop. Depending upon the power distribution network topology, the induced noise can be reduced up to 70% when the additional noise caused by the inductive link is considered by the routing algorithm. Additionally, a methodology utilising an analytic model is proposed for the evaluation of the crosstalk noise without resorting to electromagnetic simulations. A closed-form magnetostatic model is developed to assess the mutual inductance between the on-chip inductor and the power distribution network. Utilising the mutual inductance model, the crosstalk noise is evaluated with SPICE simulations. A signifcant benefit in speedup is achieved, up to four orders of magnitude for determining the mutual inductance and up to 4.7Ã for the assessment of the crosstalk noise. The accuracy of the model is within 10% of the electromagnetic simulation.

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Qiu, Xiangbin. "A Publish-Subscribe System for Data Replication and Synchronization Among Integrated Person-Centric Information Systems". DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/620.

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Synchronization of data across an integrated system of heterogeneous databases is a difficult but important task, especially in the context of integrating health care information throughout a region, state, or nation. This thesis describes the design and implementation of a data replication and synchronization tool, called the Sync Engine, which allows users to define custom data-sharing patterns and transformations for an integrated system of heterogeneous person-centric databases. This thesis also discusses the relationship between the Sync Engine's contributions and several relevant issues in the area of data integration and replication. The Sync Engine's design and implementation was validated by adapting it to CHARM, a real world integrated system currently in use at the Utah Department of Health.

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Wen, Hao. "IMPROVING PERFORMANCE AND ENERGY EFFICIENCY FOR THE INTEGRATED CPU-GPU HETEROGENEOUS SYSTEMS". VCU Scholars Compass, 2018. https://scholarscompass.vcu.edu/etd/5664.

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Current heterogeneous CPU-GPU architectures integrate general purpose CPUs and highly thread-level parallelized GPUs (Graphic Processing Units) in the same die. This dissertation focuses on improving the energy efficiency and performance for the heterogeneous CPU-GPU system. Leakage energy has become an increasingly large fraction of total energy consumption, making it important to reduce leakage energy for improving the overall energy efficiency. Cache occupies a large on-chip area, which are good targets for leakage energy reduction. For the CPU cache, we study how to reduce the cache leakage energy efﬁciently in a hybrid SPM (Scratch-Pad Memory) and cache architecture. For the GPU cache, the access pattern of GPU cache is different from the CPU, which usually has little locality and high miss rate. In addition, GPU can hide memory latency more effectively due to multi-threading. Because of the above reasons, we find it is possible to place the cache lines of the GPU data caches into the low power mode more aggressively than traditional leakage management for CPU caches, which can reduce more leakage energy without significant performance degradation. The contention in shared resources between CPU and GPU, such as the last level cache (LLC), interconnection network and DRAM, may degrade both CPU and GPU performance. We propose a simple yet effective method based on probability to control the LLC replacement policy for reducing the CPU’s inter-core conﬂict misses caused by GPU without significantly impacting GPU performance. In addition, we develop two strategies to combine the probability based method for the LLC and an existing technique called virtual channel partition (VCP) for the interconnection network to further improve the CPU performance. For a specific graph application of Breadth first search (BFS), which is a basis for graph search and a core building block for many higher-level graph analysis applications, it is a typical example of parallel computation that is inefficient on GPU architectures. In a graph, a small portion of nodes may have a large number of neighbors, which leads to irregular tasks on GPUs. These irregularities limit the parallelism of BFS executing on GPUs. Unlike the previous works focusing on fine-grained task management to address the irregularity, we propose Virtual-BFS (VBFS) to virtually change the graph itself. By adding virtual vertices, the high-degree nodes in the graph are divided into groups that have an equal number of neighbors, which increases the parallelism such that more GPU threads can work concurrently. This approach ensures correctness and can significantly improve both the performance and energy efficiency on GPUs.

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Zhu, Cheng. "Resource Management Scheme and Network Selection Strategy for Integrated Multiple Traffic Heterogeneous Systems". University of Cincinnati / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1265988792.

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Robino, Francesco. "A model-based design approach for heterogeneous NoC-based MPSoCs on FPGA". Licentiate thesis, KTH, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-145521.

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Network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs) are promising candidates for future multi-processor embedded platforms, which are expected to be composed of hundreds of heterogeneous processing elements (PEs) to potentially provide high performances. However, together with the performances, the systems complexity will increase, and new high level design techniques will be needed to efficiently model, simulate, debug and synthesize them. System-level design (SLD) is considered to be the next frontier in electronic design automation (EDA). It enables the description of embedded systems in terms of abstract functions and interconnected blocks. A promising complementary approach to SLD is the use of models of computation (MoCs) to formally describe the execution semantics of functions and blocks through a set of rules. However, also when this formalization is used, there is no clear way to synthesize system-level models into software (SW) and hardware (HW) towards a NoC-based MPSoC implementation, i.e., there is a lack of system design automation (SDA) techniques to rapidly synthesize and prototype system-level models onto heterogeneous NoC-based MPSoCs. In addition, many of the proposed solutions require large overhead in terms of SW components and memory requirements, resulting in complex and customized multi-processor platforms. In order to tackle the problem, a novel model-based SDA flow has been developed as part of the thesis. It starts from a system-level specification, where functions execute according to the synchronous MoC, and then it can rapidly prototype the system onto an FPGA configured as an heterogeneous NoC-based MPSoC. In the first part of the thesis the HeartBeat model is proposed as a model-based technique which fills the abstraction gap between the abstract system-level representation and its implementation on the multiprocessor prototype. Then details are provided to describe how this technique is automated to rapidly prototype the modeled system on a flexible platform, permitting to adjust the system specification until the designer is satisfied with the results. Finally, the proposed SDA technique is improved defining a methodology to automatically explore possible design alternatives for the modeled system to be implemented on a heterogeneous NoC-based MPSoC. The goal of the exploration is to find an implementation satisfying the designer's requirements, which can be integrated in the proposed SDA flow. Through the proposed SDA flow, the designer is relieved from implementation details and the design time of systems targeting heterogeneous NoC-based MPSoCs on FPGA is significantly reduced. In addition, it reduces possible design errors proposing a completely automated technique for fast prototyping. Compared to other SDA flows, the proposed technique targets a bare-metal solution, avoiding the use of an operating system (OS). This reduces the memory requirements on the FPGA platform comparing to related work targeting MPSoC on FPGA. At the same time, the performance (throughput) of the modeled applications can be increased when the number of processors of the target platform is increased. This is shown through a wide set of case studies implemented on FPGA.

QC 20140609

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Radhakrishnan, Swarnalatha Computer Science &amp Engineering Faculty of Engineering UNSW. "Heterogeneous multi-pipeline application specific instruction-set processor design and implementation". Awarded by:University of New South Wales. Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/29161.

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Embedded systems are becoming ubiquitous, primarily due to the fast evolution of digital electronic devices. The design of modern embedded systems requires systems to exhibit, high performance and reliability, yet have short design time and low cost. Application Specific Instruction set processors (ASIPs) are widely used in embedded system since they are economical to use, flexible, and reusable (thus saves design time). During the last decade research work on ASIPs have been carried out in mainly for single pipelined processors. Improving performance in processors is possible by exploring the available parallelism in the program. Designing of multiple parallel execution paths for parallel execution of the processor naturally incurs additional cost. The methodology presented in this dissertation has addressed the problem of improving performance in ASIPs, at minimal additional cost. The devised methodology explores the available parallelism of an application to generate a multi-pipeline heterogeneous ASIP. The processor design is application specific. No pre-defined IPs are used in the design. The generated processor contains multiple standalone pipelined data paths, which are not necessarily identical, and are connected by the necessary bypass paths and control signals. Control unit are separate for each pipeline (though with the same clock) resulting in a simple and cost effective design. By using separate instruction and data memories (Harvard architecture) and by allowing memory access by two separate pipes, the complexity of the controller and buses are reduced. The impact of higher memory latencies is nullified by utilizing parallel pipes during memory access. Efficient bypass network selection and encoding techniques provide a better implementation. The initial design approach with only two pipelines without bypass paths show speed improvements of up to 36% and switching activity reductions of up to 11%. The additional area costs around 16%. An improved design with different number of pipelines (more than two) based on applications show on average of 77% performance improvement with overheads of: 49% on area; 51% on leakage power; 17% on switching activity; and 69% on code size. The design was further trimmed, with bypass path selection and encoding techniques, which show a saving of up to 32% of area and 34% of leakage power with 6% performance improvement and 69% of code size reduction compared to the design approach without these techniques in the multi pipeline design.

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Yulei, W. U. "Performance modelling and evaluation of heterogeneous wired / wireless networks under Bursty Traffic. Analytical models for performance analysis of communication networks in multi-computer systems, multi-cluster systems, and integrated wireless systems". Thesis, University of Bradford, 2010. http://hdl.handle.net/10454/4423.

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Computer networks can be classified into two broad categories: wired networks and wireless networks, according to the hardware and software technologies used to interconnect the individual devices. Wired interconnection networks are hardware fabrics supporting communications between individual processors in highperformance computing systems (e.g., multi-computer systems and cluster systems). On the other hand, due to the rapid development of wireless technologies, wireless networks have emerged and become an indispensable part for people's lives. The integration of different wireless technologies is an effective approach to accommodate the increasing demand of the users to communicate with each other and access the Internet. This thesis aims to investigate the performance of wired interconnection networks and integrated wireless networks under the realistic working conditions. Traffic patterns have a significant impact on network performance. A number of recent measurement studies have convincingly demonstrated that the traffic generated by many real-world applications in communication networks exhibits bursty arrival nature and the message destinations are non-uniformly distributed. Analytical models for the performance evaluation of wired interconnection networks and integrated wireless networks have been widely reported. However, most of these models are developed under the simplified assumption of non-bursty Poisson process with uniformly distributed message destinations. To fill this gap, this thesis first presents an analytical model to investigate the performance of wired interconnection networks in multi-computer systems. Secondly, the analytical models for wired interconnection networks in multi-cluster systems are developed. Finally, this thesis proposes analytical models to evaluate the end-to-end delay and throughput of integrated wireless local area networks and wireless mesh networks. These models are derived when the networks are subject to bursty traffic with non-uniformly distributed message destinations which can capture the burstiness of real-world network traffic in the both temporal domain and spatial domain. Extensive simulation experiments are conducted to validate the accuracy of the analytical models. The models are then used as practical and cost-effective tools to investigate the performance of heterogeneous wired or wireless networks under the traffic patterns exhibited by real-world applications.

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Wong, Chong Wan. "Using dynamically-generated account to integrate heterogeneous B2C e-payment systems". Thesis, University of Macau, 2010. http://umaclib3.umac.mo/record=b2148240.

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Lohse, Marco. "Network integrated multimedia middleware, services, and applications". Saarbrücken VDM Verlag Dr. Müller, 2005. http://d-nb.info/987144383/04.

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Attwater, Iain James Stuart. "Development of an expert system application combining heterogeneous software to form an integrated and concurrent pressure vessel design system". Thesis, University of the West of Scotland, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.259995.

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Goldin, Darina [Verfasser], Jörg [Akademischer Betreuer] Raisch, Robert [Akademischer Betreuer] Shorten i Slawomir [Akademischer Betreuer] Stanczak. "Stability and Controllability of Double Integrator Consensus Systems in Heterogeneous Networks / Darina Goldin. Gutachter: Jörg Raisch ; Robert Shorten ; Slawomir Stanczak". Berlin : Technische Universität Berlin, 2013. http://d-nb.info/1067384898/34.

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Luan, Lin. "Chip Scale Integrated Optical Sensing Systems with Digital Microfluidic Systems". Diss., 2010. http://hdl.handle.net/10161/3020.

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Data acquisition and diagnostics for chemical and biological analytes are critical to medicine, security, and the environment. Miniaturized and portable sensing systems are especially important for medical and environmental diagnostics and monitoring applications. Chip scale integrated planar photonic sensing systems that can combine optical, electrical and fluidic functions are especially attractive to address sensing applications, because of their high sensitivity, compactness, high surface specificity after surface customization, and easy patterning for reagents. The purpose of this dissertation research is to make progress toward a chip scale integrated sensing system that realizes a high functionality optical system integration with a digital microfluidics platform for medical diagnostics and environmental monitoring.

This thesis describes the details of the design, fabrication, experimental measurement, and theoretical modeling of chip scale optical sensing systems integrated with electrowetting-on-dielectric digital microfluidic systems. Heterogeneous integration, a technology that integrates multiple optical thin film semiconductor devices onto arbitrary host substrates, has been utilized for this thesis. Three different integrated sensing systems were explored and realized. First, an integrated optical sensor based upon the heterogeneous integration of an InGaAs thin film photodetector with a digital microfluidic system was demonstrated. This integrated sensing system detected the chemiluminescent signals generated by a pyrogallol droplet solution mixed with H2O2 delivered by the digital microfluidic system.

Second, polymer microresonator sensors were explored. Polymer microresonators are useful components for chip scale integrated sensing because they can be integrated in a planar format using standard semiconductor manufacturing technologies. Therefore, as a second step, chip scale optical microdisk/ring sensors integrated with digital microfluidic systems were fabricated and measured. . The response of the microdisk and microring sensing systems to the change index of refraction, due to the glucose solutions in different concentrations presented by the digital microfluidic to the resonator surface, were measured to be 95 nm/RIU and 87nm/RIU, respectively. This is a first step toward chip-scale, low power, fully portable integrated sensing systems.

Third, a chip scale sensing system, which is composed of a planar integrated optical microdisk resonator and a thin film InGaAs photodetector, integrated with a digital microfluidic system, was fabricated and experimentally characterized. The measured sensitivity of this sensing system was 69 nm/RIU. Estimates of the resonant spectrum for the fabricated systems show good agreement with the theoretical calculations. These three systems yielded results that have led to a better understanding of the design and operation of chip scale optical sensing systems integrated with microfluidics.

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Patil, Adarsh. "Heterogeneity Aware Shared DRAM Cache for Integrated Heterogeneous Architectures". Thesis, 2017. http://etd.iisc.ac.in/handle/2005/4124.

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Integrated Heterogeneous System (IHS) processors pack throughput-oriented GPGPUs along-side latency-oriented CPUs on the same die sharing certain resources, e.g., shared last level cache, network-on-chip (NoC), and the main memory. They also share virtual and physical address spaces and unify the memory hierarchy. The IHS architecture allows for easier programmability, data management and efficiency. However, the significant disparity in the demands for memory and other shared resources between the GPU cores and CPU cores poses significant problems in exploiting the full potential of this architecture. In this work, we propose adding a large capacity stacked DRAM, used as a shared last level cache, for the IHS processors. The reduced latency of access and large bandwidth provided by the DRAM cache can help improve performance respectively of CPU and GPGPU while the large capacity can help contain the working set of the IHS workloads. However, adding the DRAM cache naively leaves significant performance on the table due to the disparate demands from CPU and GPU cores for DRAM cache and memory accesses. In particular, the imbalance can significantly reduce the performance benefits that the CPU cores would have otherwise enjoyed with the introduction of the DRAM cache. This necessitates a heterogeneity-aware management of this shared resource for improved performance. To address this, in this thesis, we propose three simple techniques to enhance the performance of CPU application while ensuring very little or no performance impact to the GPU. Specifically, we propose (i) PrIS, a prioritization scheme for scheduling CPU requests at the DRAM cache controller, (ii) ByE, a selective and temporal bypassing scheme for CPU requests at the DRAM cache and (iii) Chaining, an occupancy controlling mechanism for GPU lines in the DRAM cache through pseudoassociativity. The resulting cache, HAShCache, is heterogeneity-aware and can adapt dynamically to address the inherent disparity of demands in an IHS architecture with simple light weight schemes. We enhance the gem5-gpu simulator to model an IHS architecture with stacked DRAM as a cache, coherent GPU L2 cache and CPU caches and a shared unified physical memory. Using this setup we perform detailed experimental evaluation of the proposed HAShCache and demonstrate an average system performance (combined performance of CPU and GPU cores) improvement of 41% over a naive DRAM cache and over 100% improvement over a baseline system with no stacked DRAM cache.

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Her, Chia-hsin, i 何佳欣. "A Study on integrated searching performance of heterogeneous systems---With Chinese Information Portal Site as an Example". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/90161904567862373205.

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碩士
國立臺灣師範大學
圖書資訊學研究所
92
In this thesis, a consensus model for a digital library to realize an integrated searching system is explored from technological aspects and furthermore, a collaborative model between Service Providers and Data Providers to obtain the best performance of the integrated searching mechanism is examined as well. To achieve the above goal, this thesis takes “華文知識入口網站 (Chinese Information Portal Site)” as a study. Three research methods — literature analysis, interview, and content analysis are exploited to investigate the following issue: an integrated searching model on the foundation of the Open Archives Initiative Protocol for Metadata Harvesting (OAI-PMH), the mapping between content and the Dublin Core Metadata Element Set (DC) and performance evaluations for the model. The conclusions are: 1.The Chinese Information Portal Site adopts a concentrated model for centralized union catalog and plans well in the agreements at three levels: technical, content and organizational; 2.Data Providers use DC to facilitate cross-domain resource discovery and digital library interoperability and the mapping of DC is essential; 3.The OAI-PMH protocol works well for integrated searching. To make it best there should be a well plan in communication. According to the collaborative model of the OAI-PMH protocol in the Chinese Information Portal Site, this thesis finally gives suggestions to service and database system providers for building an integrated searching system in a digital library.

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Jin, X. L., i Geyong Min. "Modelling and Analysis of an Integrated Scheduling Scheme with Heterogeneous LRD and SRD Traffic". Thesis, 2013. http://hdl.handle.net/10454/9671.

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no
Multimedia applications in wireless networks are usually categorized into various classes according to their traffic patterns and differentiated Quality-of-Service (QoS) requirements. The traffic of heterogeneous multimedia applications often exhibits the Long-Range Dependent (LRD) and Short-Range Dependent (SRD) properties, respectively. The integrated scheduling scheme that combines Priority Queuing (PQ) and Generalized Processor Sharing (GPS) within a hierarchical structure, referred to as PQ-GPS, has been identified as an efficient mechanism for QoS differentiation in wireless networks and attracted significant research efforts. However, due to the high complexity and interdependent relationship among traffic flows, modelling of the integrated scheduling scheme poses great challenges. To address this challenging and important research problem, we develop an original analytical model for PQ-GPS systems under heterogeneous LRD and SRD traffic. A cost-effective flow decomposition approach is proposed to equivalently divide the integrated scheduling system into a group of Single-Server Single-Queue (SSSQ) systems. The expressions for calculating the queue length distribution and loss probability of individual traffic flows are further derived. After validating its accuracy, the developed model is adopted as an efficient performance tool to investigate the important issues of resource allocation and call admission control in the integrated scheduling system under QoS constraints.

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Anderson, Kenneth M. "Pervasive hypermedia". 1997. http://books.google.com/books?id=9cHaAAAAMAAJ.

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Chiou, Pin-Chuan, i 邱品銓. "Integrated Heterogeneous Networks for Indoor Positioning System". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/54272734554329401642.

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碩士
國立臺灣科技大學
電機工程系
103
Applications and services for smart handheld devices have garnered considerable attention worldwide, as have applications for Indoor Location-based Services (Indoor LBS). Improving their indoor positioning accuracy is a significant challenge. In recent years, many indoor positioning studies have used radio frequency for positioning; however, a signal’s susceptibility to environmental interference can decrease positioning accuracy. Increasing positioning accuracy is a complex problem and remains to be solved. Indoor positioning systems typically use only a signal transmitter (Wi-Fi AP) and receiver to acquire reference point data. The systems then use the K-Nearest Neighbor algorithm (KNN) or a Multilateration algorithm for positioning. Consequently, positioning accuracy is limited by both the positioning algorithm and the use of a single source for acquisition of reference point data. This study utilizes the novel Integrated Heterogeneous Networks Indoor Positioning System (IHNIPS) with low-energy Bluetooth Beacon to obtain positioning data. A fingerprint algorithm is then applied to revise the multilateration algorithm and define the fuzzy area to improve the accuracy of subspace selection. Last, novel threshold mechanisms are used to choose the transmitter for positioning and thereby improve current positioning accuracy. Experimental results show that the average error distance is 1.29m for Wi-Fi AP and 1.33m for Beacon. And the average error distance is 1.21m in the proposed Integrated Heterogeneous Networks Indoor Positioning System. The IHNIPS outperforms both Wi-Fi AP and Beacon. Thus, positioning accuracy is improved.

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Liang, Yi-Ming, i 梁益銘. "The Performance Evaluation of An Integrated Heterogeneous Networks System". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/84410237674510003466.

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碩士
國立成功大學
工程科學系碩博士班
91
This paper’s main purpose is to find the best efficiency of the date transference with the mathematical theory. The performance model is included : real-time data transference model、non real-time data transference model、Local Handoff analysis model and Global Handoff analysis model. Respectively, we set up the different models for four transference path architecture, and discuss the influences that if the transferring data is passed through the computer for mobile management. This paper is used the M/M/1 and the M/M/1/K Queueing Network theory to set up our analysis models. The M/M/1/K Queueing Network theory is the main method of setting up data transference models, and the M/M/1 Queueing Network theory is the main method of setting up Handoff analysis models. When the Global Handoff is happened, the HNIC will be handled tree packet messages. Which are included the message from the IG for requesting this Global Handoff、the message which is sent to Home HNIC for Location Update and the message for Set-path. The three messages are separated into three priorities. It is shown that the Queueing Network model is compatible with the simulation model. 　　This paper’s main units of evaluation are delay time、flow raise rate and Queue length. These all are the popular units. Our contribution is that finding the best suited transference path architecture for the network user in the integrated heterogeneous networks system.

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Lin, Yuan-Hsi, i 林原熙. "Mobile Voice over Internet Protocol under Integrated Heterogeneous Networks System". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/44850686050442932198.

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碩士
國立成功大學
工程科學系碩博士班
91
In this paper，we build up a proposal of heterogeneous network integration，as internet be the backbone network integrating four available heterogeneous networks : Internet、PSTN、GSM and WLAN. To use the characteristic of mobility on parts of heterogeneous networks，we make the communication equipment having seamless roaming ability. On our integrating networks architecture，we develop a application named Mobile Voice over Internet Protocol (MVoIP)，and use the mobility of integrating networks to overcome nowadays VoIP drawbacks，and make the user in our system when moving can still run the MVoIP application. In this paper，on one hand the description is emphasized on the design of system，its design issues，and the operation model，and the other hand we will still discuss the design issues of MVoIP application，its operation model and related problems. Our major contribution is to build up a new network integrating environment for the new application.

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Kuo, Kuan-Chih, i 郭冠治. "Using Web Services Technology to Integrate Heterogeneous C4ISR Systems Research". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/87676344944391100997.

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碩士
國防大學中正理工學院
資訊科學研究所
95
In the past, each armed service solving a particular problem developed many C4ISR systems to satisfy their own needs. As a result of the change of warfare pattern, the independent service operation model has been transformed into joint operation. These developed systems then became a lot of stovepipe systems and can not interoperate and share information with the other systems. Therefore, the disadvantage had a negative impact on the joint operation. The early distributed computing technologies such as OMG CORBA, Microsoft COM/DCOM and JAVA RMI had the capability to solve the interoperability problem. However, these software developers had their own protocols, programming languages and operation systems and thus resulted in compatible problem in different platforms. Based on this reason, this paper uses Service Oriented Architecture to design a joint command and control prototype system and integrate the heterogeneous C4ISR systems with XML-based Web Services technology. The services or functions provided by each C4ISR system can be shared, accessed and integrated via network for their own requirements. Then, the common operation pictures, generated by these systems located in different places, can assist a commander to make a right operation decision at the right place at the right time. The derived implementation result demonstrates that the web services technology is a simple, flexible and inexpensive candidate to integrate different C4ISR systems.

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TSNEG, SHENG-YI, i 曾勝億. "PREDICTABLE SMART HOME SYSTEM INTEGRATED WITH HETEROGENEOUS NETWORK AND CLOUD COMPUTING". Thesis, 2016. http://ndltd.ncl.edu.tw/handle/caz7ar.

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碩士
國立聯合大學
資訊工程學系碩士班
104
This paper introduces a smart home system. This system consists of 3 parts：terminal, cloud computing and prediction system. The terminal uses ARM Cortex-A7 infrastructure embedded developer board - Raspberry PI 2, and combines with ancillary equipments such as wide-angle IR transmitter, IR receiver, ZigBee sensor module, smart plug, IP camera etc. Terminal then runs the E-Home application developed in this paper and communicates with cloud server in order to do remote control and monitor everywhere. Cloud server sets up Apache Tomcat Server and runs RESTful API service while web socket server accepts the connection from E-Home application. By using N-gram algorithm, prediction system can achieve prediction on smart plug operation behavior.

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Wang, Sheng-Hao, i 王聖豪. "An Integrated Development Platform for Heterogeneous Multicore Constructed on Windows CE Operating System". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/56178067830765857745.

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碩士
國立中山大學
電機工程學系研究所
101
Heterogeneous multicore systems with highly parallel computing are the significant trends for being used to improve the performances of processors in computing. They are provided with some modules for communications between different cores and with different instruction set architectures so that it is difficult to develop applications on such systems. Therefore, we present an integrated development platform for heterogeneous multicore to simplify the application development flow. The architecture of the platform is composed of application layer, abstraction layer and hardware layer. The hardware layer is the heterogeneous multicore system with a master processor and multiple slave coputational units; The abstraction layer is divided into two parts: one is the platform management core on a master processor; the other is the implementor for accelerated functions on each slave coputational unit. The former manages not only resources of accelerated functions and slave coputational units by using semaphore machanism but also shared memory by using dynamic storage management. In addition, it coordinates the communications between different cores by using interrupts and FIFOs; In the application layer, we consider the code to be accelerated on a coputational unit as function-like sub-program, called accelerated function. Therefore, we provide APIs not only on the master processor for caller but also on the slave coputational unit for the callee. Furthermore, we provide an integrator to make a single executable for simplifying implement manner. Finally, we apply the framework of the platform to Windows CE (WinCE) operating system, and we successfully realize it on TI DM3730 processor. Using the procedure of developing applications as examples, we verify that this platform doesn''t affect the total performance, and that it is feasible.

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Pearson, James Deon. "An integrated global-local system for the detection and monitoring of damage progression in heterogeneous materials". 2005. http://www.lib.ncsu.edu/theses/available/etd-11102005-212655/unrestricted/etd.pdf.

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