Artykuły w czasopismach na temat „Integrated circuits Very large scale integration”
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M, Thillai Rani, Rajkumar R, Sai Pradeep K.P, Jaishree M i Rahul S.G. "Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits". ITM Web of Conferences 56 (2023): 01005. http://dx.doi.org/10.1051/itmconf/20235601005.
Pełny tekst źródłaPatel, Ambresh, i Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits". SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, nr 01 (30.01.2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.
Pełny tekst źródłaIwai, Hiroshi, Kuniyuki Kakushima i Hei Wong. "CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING". International Journal of High Speed Electronics and Systems 16, nr 01 (marzec 2006): 43–81. http://dx.doi.org/10.1142/s0129156406003539.
Pełny tekst źródłaMadhura, S. "A Review on Low Power VLSI Design Models in Various Circuits". Journal of Electronics and Informatics 4, nr 2 (8.07.2022): 74–81. http://dx.doi.org/10.36548/jei.2022.2.002.
Pełny tekst źródłaIm, James S., i Robert S. Sposili. "Crystalline Si Films for Integrated Active-Matrix Liquid-Crystal Displays". MRS Bulletin 21, nr 3 (marzec 1996): 39–48. http://dx.doi.org/10.1557/s0883769400036125.
Pełny tekst źródłaBeck, Anthony, Franziska Obst, Mathias Busek, Stefan Grünzner, Philipp Mehner, Georgi Paschew, Dietmar Appelhans, Brigitte Voit i Andreas Richter. "Hydrogel Patterns in Microfluidic Devices by Do-It-Yourself UV-Photolithography Suitable for Very Large-Scale Integration". Micromachines 11, nr 5 (2.05.2020): 479. http://dx.doi.org/10.3390/mi11050479.
Pełny tekst źródłaLi, Jian, Robert Blewer i J. W. Mayer. "Copper-Based Metallization for ULSI Applications". MRS Bulletin 18, nr 6 (czerwiec 1993): 18–21. http://dx.doi.org/10.1557/s088376940004728x.
Pełny tekst źródłaDove, Lewis. "Multi-Layer Ceramic Packaging for High Frequency Mixed-Signal VLSI ASICS". Journal of Microelectronics and Electronic Packaging 6, nr 1 (1.01.2009): 38–41. http://dx.doi.org/10.4071/1551-4897-6.1.38.
Pełny tekst źródłaWong, C. P. "An Overview of Integrated Circuit Device Encapsulants". Journal of Electronic Packaging 111, nr 2 (1.06.1989): 97–107. http://dx.doi.org/10.1115/1.3226528.
Pełny tekst źródłaBoychenko, Dmitry, Oleg Kalashnikov, Alexander Nikiforov, Anastasija Ulanova, Dmitry Bobrovsky i Pavel Nekrasov. "Total ionizing dose effects and radiation testing of complex multifunctional VLSI devices". Facta universitatis - series: Electronics and Energetics 28, nr 1 (2015): 153–64. http://dx.doi.org/10.2298/fuee1501153b.
Pełny tekst źródłaIKEDA, SHOJI, HIDEO SATO, MICHIHIKO YAMANOUCHI, HUADONG GAN, KATSUYA MIURA, KOTARO MIZUNUMA, SHUN KANAI i in. "RECENT PROGRESS OF PERPENDICULAR ANISOTROPY MAGNETIC TUNNEL JUNCTIONS FOR NONVOLATILE VLSI". SPIN 02, nr 03 (wrzesień 2012): 1240003. http://dx.doi.org/10.1142/s2010324712400036.
Pełny tekst źródłaSun, Chongjun, i Chao Ding. "Study on Calibration Method for Testing During Burn In equipment of integrated circuits". Journal of Physics: Conference Series 2029, nr 1 (1.09.2021): 012035. http://dx.doi.org/10.1088/1742-6596/2029/1/012035.
Pełny tekst źródłaRajaei, Ramin. "A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics". Journal of Circuits, Systems and Computers 27, nr 13 (3.08.2018): 1850205. http://dx.doi.org/10.1142/s0218126618502055.
Pełny tekst źródłaMurarka, S. P., J. Steigerwald i R. J. Gutmann. "Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing". MRS Bulletin 18, nr 6 (czerwiec 1993): 46–51. http://dx.doi.org/10.1557/s0883769400047321.
Pełny tekst źródłaChen, Xiangyu, Takeaki Yajima, Isao H. Inoue i Tetsuya Iizuka. "An ultra-compact leaky integrate-and-fire neuron with long and tunable time constant utilizing pseudo resistors for spiking neural networks". Japanese Journal of Applied Physics 61, SC (18.02.2022): SC1051. http://dx.doi.org/10.35848/1347-4065/ac43e4.
Pełny tekst źródłaChowdary, M. Kalpana, Rajasekhar Turaka, Bayan Alabduallah, Mudassir Khan, J. Chinna Babu i Ajmeera Kiran. "Low-Power Very-Large-Scale Integration Implementation of Fault-Tolerant Parallel Real Fast Fourier Transform Architectures Using Error Correction Codes and Algorithm-Based Fault-Tolerant Techniques". Processes 11, nr 8 (8.08.2023): 2389. http://dx.doi.org/10.3390/pr11082389.
Pełny tekst źródłaZhang, Ai Rong. "The Integration on Electrical Control Systems Based on Optimized Method". Advanced Materials Research 490-495 (marzec 2012): 2604–8. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2604.
Pełny tekst źródłaLuo, Guozheng, Xiang Chen i Shanshan Nong. "Net Clusting Based Low Complexity Coarsening Algorithm In k-way Hypergraph Partitioning". Journal of Physics: Conference Series 2245, nr 1 (1.04.2022): 012019. http://dx.doi.org/10.1088/1742-6596/2245/1/012019.
Pełny tekst źródłaJayakumar, Ganesh, Per-Erik Hellström i Mikael Östling. "Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application". Micromachines 9, nr 11 (25.10.2018): 544. http://dx.doi.org/10.3390/mi9110544.
Pełny tekst źródłaLi, Peng, Shite Zhu, Wei Xi, Changbao Xu, Dandan Zheng i Kai Huang. "Triple-Threshold Path-Based Static Power-Optimization Methodology (TPSPOM) for Designing SOC Applications Using 28 nm MTCMOS Technology". Applied Sciences 13, nr 6 (8.03.2023): 3471. http://dx.doi.org/10.3390/app13063471.
Pełny tekst źródłaNagabushanam, M., Skandan Srikanth, Rushita Mupalla, Sushmitha S. Kumar i Swathi K. "Optimization of Power and Area Using VLSI Implementation of MAC Unit Based on Additive Multiply Module". International Journal of Electrical and Electronics Research 10, nr 4 (30.12.2022): 1099–106. http://dx.doi.org/10.37391/ijeer.100455.
Pełny tekst źródłaZhu, Ziran, Zhipeng Huang, Jianli Chen i Longkun Guo. "Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles". Complexity 2021 (14.04.2021): 1–12. http://dx.doi.org/10.1155/2021/8843271.
Pełny tekst źródłaMOHANA KANNAN, LOGANATHAN, i DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION". DYNA 96, nr 5 (1.09.2021): 505–11. http://dx.doi.org/10.6036/10214.
Pełny tekst źródłaN., Alivelu Manga. "Design of High-Speed Low Power Computational Blocks for DSP Processors". Revista Gestão Inovação e Tecnologias 11, nr 2 (5.06.2021): 1419–29. http://dx.doi.org/10.47059/revistageintec.v11i2.1768.
Pełny tekst źródłaCheng, Yi Lung, Yi Shiung Lu i Tai Jung Chiu. "Comparative Study of Low Dielectric Constant Material Deposited Using Different Precursors". Advanced Materials Research 233-235 (maj 2011): 2480–85. http://dx.doi.org/10.4028/www.scientific.net/amr.233-235.2480.
Pełny tekst źródłaAhmad, Afaq, Sabir Hussain, M. A. Raheem, Ahmed Al Maashri, Sayyid Samir Al Busaidi i Medhat Awadalla. "ASIC vs FPGA based Implementations of Built-In Self-Test". International Journal of Advanced Natural Sciences and Engineering Researches 7, nr 6 (13.07.2023): 14–20. http://dx.doi.org/10.59287/ijanser.942.
Pełny tekst źródłaRasheed, Israa Mohammed, i Hassan Jasim Motlak. "Performance parameters optimization of CMOS analog signal processing circuits based on smart algorithms". Bulletin of Electrical Engineering and Informatics 12, nr 1 (1.02.2023): 149–57. http://dx.doi.org/10.11591/eei.v12i1.4128.
Pełny tekst źródłaNIRANJAN, VANDANA, ASHWANI KUMAR i SHAIL BALA JAIN. "COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS". Journal of Circuits, Systems and Computers 23, nr 08 (18.06.2014): 1450108. http://dx.doi.org/10.1142/s0218126614501084.
Pełny tekst źródłaSun, Ben. "Interpretable machine learning in VLSI physical design". Applied and Computational Engineering 4, nr 1 (14.06.2023): 13–19. http://dx.doi.org/10.54254/2755-2721/4/20230338.
Pełny tekst źródłaEppili, Jaya, Sri B. Sai, Kumar P. Akshay, Kumar O. Hem, D. Sunil i R. Rajesh. "VLSI implementation of Kogge-Stone Adder for low-power applications". i-manager's Journal on Digital Signal Processing 11, nr 1 (2023): 9. http://dx.doi.org/10.26634/jdp.11.1.19372.
Pełny tekst źródłaSoref, Richard. "Applications of Silicon-Based Optoelectronics". MRS Bulletin 23, nr 4 (kwiecień 1998): 20–24. http://dx.doi.org/10.1557/s0883769400030220.
Pełny tekst źródłaNAKADA, KAZUKI, TETSUYA ASAI i HATSUO HAYASHI. "ANALOG VLSI IMPLEMENTATION OF RESONATE-AND-FIRE NEURON". International Journal of Neural Systems 16, nr 06 (grudzień 2006): 445–56. http://dx.doi.org/10.1142/s0129065706000846.
Pełny tekst źródłaShanavas, I. Hameem, i R. K. Gnanamurthy. "Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm". Mathematical Problems in Engineering 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/809642.
Pełny tekst źródłaSanadhya, Minakshi, Devendra Kumar Sharma i Alfilh Raed Hameed Chyad. "Adiabatic technique based low power synchronous counter design". International Journal of Electrical and Computer Engineering (IJECE) 13, nr 4 (1.08.2023): 3770. http://dx.doi.org/10.11591/ijece.v13i4.pp3770-3777.
Pełny tekst źródłaKumar, Umesh. "Vlsi Interconnection Modelling Using a Finite Element Approach". Active and Passive Electronic Components 18, nr 3 (1995): 179–202. http://dx.doi.org/10.1155/1995/97362.
Pełny tekst źródłaBalodi, Deepak, i Rahul Misra. "Low Power Differential and Ring Voltage Controlled Oscillator Architectures for High Frequency (L-Band) Phase Lock Loop Applications in 0.35 Complementary Metal Oxide Semi Conductor Process". SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 11, nr 01 (25.07.2019): 63–70. http://dx.doi.org/10.18090/samriddhi.v11i01.9.
Pełny tekst źródłaYeh, Chung-Huang, i Jwu-E. Chen. "Unbalanced-Tests to the Improvement of Yield and Quality". Electronics 10, nr 23 (4.12.2021): 3032. http://dx.doi.org/10.3390/electronics10233032.
Pełny tekst źródłaLaudis, Lalin L., i N. Ramadass. "A Lion’s Pride Inspired Algorithm for VLSI Floorplanning". Journal of Circuits, Systems and Computers 29, nr 01 (15.03.2019): 2050003. http://dx.doi.org/10.1142/s0218126620500036.
Pełny tekst źródłaSmy, T., S. K. Dew i M. J. Brett. "Simulation of Microstructure and Surface Profiles of Thin Films for VLSI Metallization". MRS Bulletin 20, nr 11 (listopad 1995): 65–69. http://dx.doi.org/10.1557/s0883769400045619.
Pełny tekst źródłaKrishna, T. Rama, T. Krishna Murthy, N. Vilasrao Sarode, P. Srilakshmi i V. Geetha Sri. "Verilog HDL using LTE Implementation MAP Algorithm". International Journal of Innovative Research in Computer Science and Technology 10, nr 2 (30.03.2022): 611–14. http://dx.doi.org/10.55524/ijircst.2022.10.2.115.
Pełny tekst źródłaQiao, Zhitong, Yan Han, Xiaoxia Han, Han Xu, Will X. Y. Li, Dong Song, Theodore W. Berger i Ray C. C. Cheung. "ASIC Implementation of a Nonlinear Dynamical Model for Hippocampal Prosthesis". Neural Computation 30, nr 9 (wrzesień 2018): 2472–99. http://dx.doi.org/10.1162/neco_a_01107.
Pełny tekst źródłaShacham-Diamand, Yosi. "The Reliability of Aluminum/Tungsten Technology for VLSI Applications". MRS Bulletin 20, nr 11 (listopad 1995): 78–82. http://dx.doi.org/10.1557/s0883769400045644.
Pełny tekst źródłaSidorenko, V. P., V. D. Zhora, O. I. Radkevich, V. P. Grunyanska, Yu V. Prokofiev, Yu V. Tayakin i T. M. Virozub. "Assembly technology and design features of microelectronic coordinate-sensitive detectors". Технология и конструирование в электронной аппаратуре, nr 1 (2018): 21–27. http://dx.doi.org/10.15222/tkea2018.1.21.
Pełny tekst źródłaSatria, Brama Yoga, Munawar Agus Riyadi i Muhammad Arfan. "PERANCANGAN MULTIPLIER SEKUENSIAL 8-BIT DENGAN TEKNOLOGI 180NM MENGGUNAKAN PERANGKAT LUNAK ELECTRIC". TRANSIENT 6, nr 3 (9.11.2017): 476. http://dx.doi.org/10.14710/transient.6.3.476-482.
Pełny tekst źródłaDong, Chen, Jinghui Chen, Wenzhong Guo i Jian Zou. "A machine-learning-based hardware-Trojan detection approach for chips in the Internet of Things". International Journal of Distributed Sensor Networks 15, nr 12 (grudzień 2019): 155014771988809. http://dx.doi.org/10.1177/1550147719888098.
Pełny tekst źródłaManjunath, T. C., Deekshitha P., Pavithra G., Sindhu Sree M., Suhasini V.K. i K. N. Vijaykumar. "A Survey of the Different Intelligent Algorithms for the VLSI-Based Design Flows for Various Embedded Applications in Electronics Engineering". Journal of Embedded Systems and Processing 7, nr 3 (3.11.2022): 14–17. http://dx.doi.org/10.46610/joesp.2022.v07i03.003.
Pełny tekst źródłaMai, Christian, Steffen Marschmeyer, Anna Peczek, Aleksandra Kroh, Josmy Jose, Sebastian Reiter, Inga Fischer, Christian Wenger i Andreas Mai. "Integration Aspects of Plasmonic TiN-based Nano-Hole-Arrays on Ge Photodetectorsin a 200mm Wafer CMOS Compatible Silicon Technology". ECS Meeting Abstracts MA2022-02, nr 32 (9.10.2022): 1174. http://dx.doi.org/10.1149/ma2022-02321174mtgabs.
Pełny tekst źródłaDeekshitha P, Pavithra G, Sindhu Sree M i T.C.Manjunath. "AI/ML/DL Algorithms and Applications in VLSI Design Technology Process Flow – A Brief Review". international journal of engineering technology and management sciences 6, nr 6 (28.11.2022): 329–32. http://dx.doi.org/10.46647/ijetms.2022.v06i06.057.
Pełny tekst źródłaFlemming, Jeb, Kyle McWethy, Tim Mezel, Luis Chenoweth i Carrie Schmidt. "Photosensitive Glass-Ceramics for Heterogeneous Integration". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (1.01.2019): 000880–907. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_036.
Pełny tekst źródłaSharma, Himanshu, i Karmjit Singh Sandha. "Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects". Journal of Circuits, Systems and Computers 29, nr 12 (5.02.2020): 2050185. http://dx.doi.org/10.1142/s0218126620501856.
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