Gotowe bibliografie tematyczne / In-memory compute

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  1. Artykuły w czasopismach
  2. Rozprawy doktorskie
  3. Książki
  4. Części książek
  5. Streszczenia konferencji
  6. Raporty organizacyjne

Gotowa bibliografia na temat „In-memory compute”

Autor: Grafiati
Data publikacji: 6 września 2023

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Artykuły w czasopismach na temat "In-memory compute"

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Varnava, Christiana. "Photonic devices compute in memory." Nature Electronics 2, no. 3 (2019): 91. http://dx.doi.org/10.1038/s41928-019-0226-1.

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John-Africa, Elijah, and Victor T. Emmah. "Performance Evaluation of LSTM and RNN Models in the Detection of Email Spam Messages." European Journal of Information Technologies and Computer Science 2, no. 6 (2022): 24–30. http://dx.doi.org/10.24018/compute.2022.2.6.80.

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Email spam is an unwanted bulk message that is sent to a recipient’s email address without explicit consent from the recipient. This is usually considered a means of advertising and maximizing profit, especially with the increase in the usage of the internet for social networking, but can also be very frustrating and annoying to the recipients of these messages. Recent research has shown that about 14.7 billion spam messages are sent out every single day of which more than 45% of these messages are promotional sales content that the recipient did not specifically opt-in. This has gotten the at
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Zhao, Dongyan, Yubo Wang, Jin Shao, et al. "Compute-in-Memory for Numerical Computations." Micromachines 13, no. 5 (2022): 731. http://dx.doi.org/10.3390/mi13050731.

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In recent years, compute-in-memory (CIM) has been extensively studied to improve the energy efficiency of computing by reducing data movement. At present, CIM is frequently used in data-intensive computing. Data-intensive computing applications, such as all kinds of neural networks (NNs) in machine learning (ML), are regarded as ‘soft’ computing tasks. The ‘soft’ computing tasks are computations that can tolerate low computing precision with little accuracy degradation. However, ‘hard’ tasks aimed at numerical computations require high-precision computing and are also accompanied by energy eff
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Handy, Jim, and Tom Coughlin. "Semiconductor Architectures Enable Compute in Memory." Computer 56, no. 5 (2023): 126–29. http://dx.doi.org/10.1109/mc.2023.3252099.

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Miller, Ethan, Achilles Benetopoulos, George Neville-Neil, Pankaj Mehra, and Daniel Bittman. "Pointers in Far Memory." Queue 21, no. 3 (2023): 75–93. http://dx.doi.org/10.1145/3606029.

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Effectively exploiting emerging far-memory technology requires consideration of operating on richly connected data outside the context of the parent process. Operating-system technology in development offers help by exposing abstractions such as memory objects and globally invariant pointers that can be traversed by devices and newly instantiated compute. Such ideas will allow applications running on future heterogeneous distributed systems with disaggregated memory nodes to exploit near-memory processing for higher performance and to independently scale their memory and compute resources for
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Wan, Weier, Rajkumar Kubendran, Clemens Schaefer, et al. "A compute-in-memory chip based on resistive random-access memory." Nature 608, no. 7923 (2022): 504–12. http://dx.doi.org/10.1038/s41586-022-04992-8.

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AbstractRealizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM)1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory2–5. Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM har
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Wang, Ruihong, Jianguo Wang, Stratos Idreos, M. Tamer Özsu, and Walid G. Aref. "The case for distributed shared-memory databases with RDMA-enabled memory disaggregation." Proceedings of the VLDB Endowment 16, no. 1 (2022): 15–22. http://dx.doi.org/10.14778/3561261.3561263.

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Memory disaggregation (MD) allows for scalable and elastic data center design by separating compute (CPU) from memory. With MD, compute and memory are no longer coupled into the same server box. Instead, they are connected to each other via ultra-fast networking such as RDMA. MD can bring many advantages, e.g., higher memory utilization, better independent scaling (of compute and memory), and lower cost of ownership. This paper makes the case that MD can fuel the next wave of innovation on database systems. We observe that MD revives the great debate of "shared what" in the database community.
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Yu, Shimeng, Wonbo Shim, Xiaochen Peng, and Yandong Luo. "RRAM for Compute-in-Memory: From Inference to Training." IEEE Transactions on Circuits and Systems I: Regular Papers 68, no. 7 (2021): 2753–65. http://dx.doi.org/10.1109/tcsi.2021.3072200.

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Alam, Shamiul, Md Mazharul Islam, Md Shafayat Hossain, Akhilesh Jaiswal, and Ahmedullah Aziz. "CryoCiM: Cryogenic compute-in-memory based on the quantum anomalous Hall effect." Applied Physics Letters 120, no. 14 (2022): 144102. http://dx.doi.org/10.1063/5.0092169.

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The scaling of the already matured complementary metal-oxide-semiconductor technology is steadily approaching its physical limit, motivating the quest for a suitable alternative. Cryogenic operation offers a promising pathway toward continued improvement in computing speed and energy efficiency without aggressive scaling. However, the memory wall bottleneck of the traditional von-Neumann architecture persists even at cryogenic temperature. That is where a compute-in-memory (CiM) architecture, which embeds computing within the memory unit, comes into play. Computations within the memory unit he
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Redwan, Sadi M., Md Rashed-Al-Mahfuz, and Md Ekramul Hamid. "Recognizing Command Words using Deep Recurrent Neural Network for Both Acoustic and Throat Speech." European Journal of Information Technologies and Computer Science 3, no. 2 (2023): 7–13. http://dx.doi.org/10.24018/compute.2023.3.2.88.

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The importance of speech command recognition in a human-machine interaction system is increased in recent years. In this study, we propose a deep neural network-based system for acoustic and throat command speech recognition. We apply a preprocessed pipeline to create the input of the deep learning model. Firstly, speech commands are decomposed into components using well-known signal decomposition techniques. The Mel-frequency cepstral coefficients (MFCC) feature extraction method is applied to each component of the speech commands to obtain the feature inputs for the recognition system. At th
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Rozprawy doktorskie na temat "In-memory compute"

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Scrbak, Marko. "Methodical Evaluation of Processing-in-Memory Alternatives." Thesis, University of North Texas, 2019. https://digital.library.unt.edu/ark:/67531/metadc1505199/.

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In this work, I characterized a series of potential application kernels using a set of architectural and non-architectural metrics, and performed a comparison of four different alternatives for processing-in-memory cores (PIMs): ARM cores, GPGPUs, coarse-grained reconfigurable dataflow (DF-PIM), and a domain specific architecture using SIMD PIM engine consisting of a series of multiply-accumulate circuits (MACs). For each PIM alternative I investigated how performance and energy efficiency changes with respect to a series of system parameters, such as memory bandwidth and latency, number of PI
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Thomas, Jonathan. "Asynchronous Validity Resolution in Sequentially Consistent Shared Virtual Memory." Fogler Library, University of Maine, 2001. http://www.library.umaine.edu/theses/pdf/Thomas.pdf.

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Jiang, Song. "Efficient caching algorithms for memory management in computer systems." W&M ScholarWorks, 2004. https://scholarworks.wm.edu/etd/1539623446.

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As disk performance continues to lag behind that of memory systems and processors, fully utilizing memory to reduce disk accesses is a highly effective effort to improve the entire system performance. Furthermore, to serve the applications running on a computer in distributed systems, not only the local memory but also the memory on remote servers must be effectively managed to minimize I/O operations. The critical challenges in an effective memory cache management include: (1) Insightfully understanding and quantifying the locality inherent in the memory access requests; (2) Effectively utili
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Squillante, Mark S. "Issues in shared-memory multiprocessor scheduling : a performance evaluation /." Thesis, Connect to this title online; UW restricted, 1990. http://hdl.handle.net/1773/6858.

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Sperens, Martin. "Dynamic Memory Managment in C++." Thesis, Luleå tekniska universitet, Datavetenskap, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-76611.

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Memory allocation is an important part of program optimization as well as of computer architecture. This thesis examines some of the concepts of memory allocation and tries to implement overrides for the standard new and delete functions in the c++ library using memory pools combined with other techniques. The overrides are tested against the standard new and delete as well as a custom memory pool with perfect size for the allocations. The study finds that the overrides are slightly faster on a single thread but not on multiple. The study also finds that the biggest gain on performance is to c
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Chan, Chun Keung. "A study on non-volatile memory scaling in the sub-100nm regime /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20CHAN.

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Zeffer, Håkan. "Hardware–Software Tradeoffs in Shared-Memory Implementations." Licentiate thesis, Uppsala universitet, Avdelningen för datorteknik, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-86369.

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Shared-memory architectures represent a class of parallel computer systems commonly used in the commercial and technical market. While shared-memory servers typically come in a large variety of configurations and sizes, the advance in semiconductor technology have set the trend towards multiple cores per die and multiple threads per core. Software-based distributed shared-memory proposals were given much attention in the 90s. But their promise of short time to market and low cost could not make up for their unstable performance. Hence, these systems seldom made it to the market. However, with
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McDonald, Ian Lindsay. "Memory management in a distributed system of single address space operating systems supporting quality of service." Thesis, University of Glasgow, 2001. http://theses.gla.ac.uk/5427/.

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The choices provided by an operating system to the application developer for managing memory came in two forms: no choice at all, with the operating system making all decisions about managing memory; or the choice to implement virtual memory management specific to the individual application. The second of these choices is, for all intents and purposes, the same as the first: no choice at all. For many application developers, the cost of implementing a customised virtual memory management system is just too high. The results is that, regardless of the level of flexibility available, the develop
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Bearpark, Keith. "Learning and memory in genetic programming." Thesis, University of Southampton, 2000. https://eprints.soton.ac.uk/45930/.

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Genetic Programming is a form of Evolutionary Computation in which computer programs are evolved by methods based on simulating the natural evolution of biological species. A new generation of a species acquires the characteristics of previous generations through the inheritance of genes by sexual reproduction and through random changes in alleles by random mutation. The new generation may enhance its ability to survive by the acquisition of cultural knowledge through learning processes. This thesis combines the transfer of knowledge by genetic means with the transfer of knowledge by cultural
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Olson, Julius, and Emma Södergren. "Long Term Memory in Conversational Robots." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-260316.

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This study discusses an implementation of a long term memory in the robot Furhat. The idea was to find a way to prevent identical and very similar questions from being asked several times and to store the information of which questions have already been asked in a document database. The project encompasses tf-idf, as well as a small-scale test with Word2Vec, to find a vector representation of all questions from Furhat’s database and then clustering these questions with the k-means method. The tests resulted in high scores on all the evaluation metrics used, which is promising for implementatio
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Książki na temat "In-memory compute"

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Memory storage patterns in parallel processing. Kluwer Academic, 1987.

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Miller, R. K. Neural networks: Implementing associative memory models in neurocomputers. Fairmont Press, 1990.

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Miller, Richard Kendall. Neural networks: Implementing associative memory models in neurocomputers. Fairmont Press, 1990.

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Kanerva, Pentti. Parallel structures in human and computer memory. Research Institute for Advanced Computer Science, 1986.

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Donovan, Kevin. Performance of shared memory in a parallel computer. Courant Institute of Mathematical Sciences, New York University, 1990.

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Mace, Mary E. Memory Storage Patterns in Parallel Processing. Springer US, 1987.

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David, Hutchison. Mathematical Methods in Computer Science: Essays in Memory of Thomas Beth. Springer Berlin Heidelberg, 2008.

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Dickey, Susan. Designing VLSI network nodes to reduce memory traffic in a shared memory parallel computer. Courant Institute of Mathematical Sciences, New York University, 1986.

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Cheriton, David R. The unified management of memory in the V distributed system. Dept. of Computer Science, Stanford University, 1988.

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Nikil, Dutt, and Nicolau Alexandru, eds. Memory issues in embedded systems-on-chip: Optimizations and exploration. Kluwer Academic, 1999.

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Części książek na temat "In-memory compute"

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Jiang, Hongwu, Shanshi Huang, and Shimeng Yu. "Compute-in-Memory Architecture." In Handbook of Computer Architecture. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-15-6401-7_62-1.

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Karam, Robert, Somnath Paul, and Swarup Bhunia. "Compute-in-Memory Architecture for Data-Intensive Kernels." In Emerging Technology and Architecture for Big-data Analytics. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-54840-1_4.

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Ristov, Sasko, Goran Velkoski, Marjan Gusev, and Kiril Kjiroski. "Compute and Memory Intensive Web Service Performance in the Cloud." In ICT Innovations 2012. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-37169-1_21.

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Crafton, Brian, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung-Kyu Lim, and Arijit Raychowdhury. "Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics." In VLSI-SoC: Design Trends. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-81641-4_15.

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Simner, Ben, Alasdair Armstrong, Jean Pichon-Pharabod, Christopher Pulte, Richard Grisenthwaite, and Peter Sewell. "Relaxed virtual memory in Armv8-A." In Programming Languages and Systems. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-99336-8_6.

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AbstractVirtual memory is an essential mechanism for enforcing security boundaries, but its relaxed-memory concurrency semantics has not previously been investigated in detail. The concurrent systems code managing virtual memory has been left on an entirely informal basis, and OS and hypervisor verification has had to make major simplifying assumptions.We explore the design space for relaxed virtual memory semantics in the Armv8-A architecture, to support future system-software verification. We identify many design questions, in discussion with Arm; develop a test suite, including use cases from the pKVM production hypervisor under development by Google; delimit the design space with axiomatic-style concurrency models; prove that under simple stable configurations our architectural model collapses to previous “user” models; develop tooling to compute allowed behaviours in the model integrated with the full Armv8-A ISA semantics; and develop a hardware test harness.This lays out some of the main issues in relaxed virtual memory bringing these security-critical systems phenomena into the domain of programming-language semantics and verification with foundational architecture semantics.
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Natale, Emanuele, and Iliad Ramezani. "On the Necessary Memory to Compute the Plurality in Multi-agent Systems." In Lecture Notes in Computer Science. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-17402-6_27.

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Liao, Xiangke, Canqun Yang, Zhe Quan, Tao Tang, and Cheng Chen. "An Efficient Clique-Based Algorithm of Compute Nodes Allocation for In-memory Checkpoint System." In Lecture Notes in Computer Science. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-20119-1_15.

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Finkel, Alain, Serge Haddad, and Igor Khmelnitsky. "Minimal Coverability Tree Construction Made Complete and Efficient." In Lecture Notes in Computer Science. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-45231-5_13.

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AbstractDownward closures of Petri net reachability sets can be finitely represented by their set of maximal elements called the minimal coverability set or Clover. Many properties (coverability, boundedness, ...) can be decided using Clover, in a time proportional to the size of Clover. So it is crucial to design algorithms that compute it efficiently. We present a simple modification of the original but incomplete Minimal Coverability Tree algorithm (MCT), computing Clover, which makes it complete: it memorizes accelerations and fires them as ordinary transitions. Contrary to the other alternative algorithms for which no bound on the size of the required additional memory is known, we establish that the additional space of our algorithm is at most doubly exponential. Furthermore we have implemented a prototype which is already very competitive: on benchmarks it uses less space than all the other tools and its execution time is close to the one of the fastest tool.
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Tsugane, Keisuke, Taisuke Boku, Hitoshi Murai, Mitsuhisa Sato, William Tang, and Bei Wang. "Hybrid-View Programming of Nuclear Fusion Simulation Code in XcalableMP." In XcalableMP PGAS Programming Language. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7683-6_7.

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AbstractXcalableMP(XMP) supports a global-view model that allows programmers to define global data and to map them to a set of processors, which execute the distributed global data as a single thread. In XMP, the concept of a coarray is also employed for local-view programming. In this study, we port Gyrokinetic Toroidal Code - Princeton (GTC-P), which is a three-dimensional gyrokinetic PIC code developed at Princeton University to study the microturbulence phenomenon in magnetically confined fusion plasmas, to XMP as an example of hybrid memory model coding with the global-view and local-view programming models. In local-view programming, the coarray notation is simple and intuitive compared with Message Passing Interface (MPI) programming, while the performance is comparable to that of the MPI version. Thus, because the global-view programming model is suitable for expressing the data parallelism for a field of grid space data, we implement a hybrid-view version using a global-view programming model to compute the field and a local-view programming model to compute the movement of particles. The performance is degraded by 20% compared with the original MPI version, but the hybrid-view version facilitates more natural data expression for static grid space data (in the global-view model) and dynamic particle data (in the local-view model), and it also increases the readability of the code for higher productivity.
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Beyer, Dirk. "Competition on Software Verification and Witness Validation: SV-COMP 2023." In Tools and Algorithms for the Construction and Analysis of Systems. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-30820-8_29.

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AbstractThe 12th edition of the Competition on Software Verification (SV-COMP 2023) is again the largest overview of tools for software verification, evaluating 52 verification systems from 34 teams from 10 countries. Besides providing an overview of the state of the art in automatic software verification, the goal of the competition is to establish standards, provide a platform for exchange to developers of such tools, educate PhD students on reproducibility approaches and benchmarking, and provide computing resources to developers that do not have access to compute clusters. The competition consisted of 23 805 verification tasks for C programs and 586 verification tasks for Java programs. The specifications include reachability, memory safety, overflows, and termination. This year, the competition introduced a new competition track on witness validation, where validators for verification witnesses are evaluated with respect to their quality.
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Streszczenia konferencji na temat "In-memory compute"

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Fick, Laura, and Dave Fick. "Introduction to Compute-in-Memory." In 2019 IEEE Custom Integrated Circuits Conference (CICC). IEEE, 2019. http://dx.doi.org/10.1109/cicc.2019.8780261.

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Salahuddin, Saveef, Ava Tan, Suraj Cheema, Nirmaan Shanker, Michael Hoffmann, and J. H. Bae. "FeFETs for Near-Memory and In-Memory Compute." In 2021 IEEE International Electron Devices Meeting (IEDM). IEEE, 2021. http://dx.doi.org/10.1109/iedm19574.2021.9720622.

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"Session 7 Overview: SRAM Compute-In-Memory: Memory Subcommittee." In 2023 IEEE International Solid- State Circuits Conference (ISSCC). IEEE, 2023. http://dx.doi.org/10.1109/isscc42615.2023.10067261.

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Wang, C. T., W. L. Chang, C. Y. Chen, and Douglas Yu. "Immersion in Memory Compute (ImMC) Technology." In 2020 IEEE Symposium on VLSI Technology. IEEE, 2020. http://dx.doi.org/10.1109/vlsitechnology18217.2020.9265019.

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"Session 15 Overview: SRAM & Compute-In-Memory: Memory Subcommittee." In 2020 IEEE International Solid- State Circuits Conference - (ISSCC). IEEE, 2020. http://dx.doi.org/10.1109/isscc19947.2020.9063041.

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Patricia, A. Trephena, S. Ewins Pon Pushpa, and A. Diana Andrushia. "Analysis of Cache Memory Circuit for Compute In Memory Applications." In 2023 4th International Conference on Signal Processing and Communication (ICSPC). IEEE, 2023. http://dx.doi.org/10.1109/icspc57692.2023.10125285.

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"Session 33 Overview: Non-Volatile Memory and Compute-In-Memory." In 2023 IEEE International Solid- State Circuits Conference (ISSCC). IEEE, 2023. http://dx.doi.org/10.1109/isscc42615.2023.10067750.

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Dutt, Shantanu. "Session details: Compute-in-Memory and Design of Structured Compute Arrays." In ICCAD '22: IEEE/ACM International Conference on Computer-Aided Design. ACM, 2022. http://dx.doi.org/10.1145/3582551.

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Jao, Nicholas, Akshay Krishna Ramanathan, Srivatsa Srinivasa, Sumitha George, John Sampson, and Vijaykrishnan Narayanan. "Harnessing Emerging Technology for Compute-in-Memory Support." In 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2018. http://dx.doi.org/10.1109/isvlsi.2018.00087.

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Fick, D. "Analog Compute-in-Memory For AI Edge Inference." In 2022 IEEE International Electron Devices Meeting (IEDM). IEEE, 2022. http://dx.doi.org/10.1109/iedm45625.2022.10019367.

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Raporty organizacyjne na temat "In-memory compute"

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Mayas, Magda. Creating with timbre. Norges Musikkhøgskole, 2018. http://dx.doi.org/10.22501/nmh-ar.686088.

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Unfolding processes of timbre and memory in improvisational piano performance This exposition is an introduction to my research and practice as a pianist, in which I unfold processes of timbre and memory in improvised music from a performer’s perspective. Timbre is often understood as a purely sonic perceptual phenomenon. However, this is not in accordance with a site-specific improvisational practice with changing spatial circumstances impacting the listening experience, nor does it take into account the agency of the instrument and objects used or the performer’s movements and gestures. In m
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Bartlett, Roscoe Ainsworth. Teuchos C++ memory management classes, idioms, and related topics, the complete reference : a comprehensive strategy for safe and efficient memory management in C++ for high performance computing. Office of Scientific and Technical Information (OSTI), 2010. http://dx.doi.org/10.2172/992335.

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Castro, Carolina Robledo, Piedad Rocio Lerma-Castaño, and Luis Gerardo Pachón-Ospina. Rehabilitation programs based on computational systems: effects in the executive functions in young and middle adulthood: A scoping review. INPLASY - International Platform of Registered Systematic Review and Meta-analysis Protocols, 2022. http://dx.doi.org/10.37766/inplasy2022.10.0052.

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Review question / Objective: To identify empirical studies that measured the feasibility and effect of computer-based executive function stimulation and rehabilitation programs in the young and middle adult population. Background: Reviews that evaluate the effectiveness of computerized cognitive training programs on executive functions in different population groups have shown contradictory results, to a certain extent associated with the methodological characteristics of said studies (Gates et al., 2019; 2020); most of them These reviews have focused on older adults (Ten Brinke et al., 2020;
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Amela, R., R. Badia, S. Böhm, R. Tosi, C. Soriano, and R. Rossi. D4.2 Profiling report of the partner’s tools, complete with performance suggestions. Scipedia, 2021. http://dx.doi.org/10.23967/exaqute.2021.2.023.

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This deliverable focuses on the proling activities developed in the project with the partner's applications. To perform this proling activities, a couple of benchmarks were dened in collaboration with WP5. The rst benchmark is an embarrassingly parallel benchmark that performs a read and then multiple writes of the same object, with the objective of stressing the memory and storage systems and evaluate the overhead when these reads and writes are performed in parallel. A second benchmark is dened based on the Continuation Multi Level Monte Carlo (C-MLMC) algorithm. While this algorithm is norm
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van der Mensbrugghe, Dominique. A Summary Guide to the Latin Hypercube Sampling (LHS) Utility. GTAP Working Paper, 2023. http://dx.doi.org/10.21642/gtap.wp94.

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Latin Hypercube Sampling (LHS) is one method of Monte Carlo-type sampling, which is useful for limiting sample size yet maximizing the range of sampling of the underlying distributions. The LHS utility, for which this document describes the usage, also allows for user-specified correlations between two or more of the sampled distributions. The LHS utility described herein is a full re-coding using C/C++ of the original LHS utility—developed at Sandia National Labs (Swiler and Wyss (2004)), written in FORTRAN and freely available. The re-coding hones close to the original FORTRAN code, but allo
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Tan, Peng, and Nicholas Sitar. Parallel Level-Set DEM (LS-DEM) Development and Application to the Study of Deformation and Flow of Granular Media. Pacific Earthquake Engineering Research Center, University of California, Berkeley, CA, 2023. http://dx.doi.org/10.55461/kmiz5819.

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We present a systematic investigation of computational approaches to the modeling of granular materials. Granular materials are ubiquitous in everyday life and in a variety of engineering and industrial applications. Despite the apparent simplicity of the laws governing particle-scale interactions, predicting the continuum mechanical response of granular materials still poses extraordinary challenges. This is largely due to the complex history dependence resulting from continuous rearrangement of the microstructure of granular material, as well as the mechanical interlocking due to grain morph
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Palmer, Guy, Varda Shkap, Wendy Brown, and Thea Molad. Control of bovine anaplasmosis: cytokine enhancement of vaccine efficacy. United States Department of Agriculture, 2007. http://dx.doi.org/10.32747/2007.7695879.bard.

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Anaplasmosis an arthropod-born disease of cattle caused by the rickettsia Anaplasma marginale and is an impediment to efficient production of healthy livestock in both Israel and the United States. Currently the only effective vaccines are derived from the blood of infected cattle. The risk of widespread transmission of both known and newly emergent pathogens has prevented licensure of live blood-based vaccines in the U.S. and is a major concern for their continued use in Israel. Consequently development of a safe, effective vaccine is a high priority. In this collaborative project we focused
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DESIGN OF THE DEPLOYABLE-FOLDABLE ACTUATOR AND VIBRATION CONTROL DEVICE BASED ON THE SHAPE MEMORY ALLOYS WITH A TWO-WAY EFFECT. The Hong Kong Institute of Steel Construction, 2022. http://dx.doi.org/10.18057/icass2020.p.306.

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The paper aims at the design method of the space deployable-foldable actuator and vibration control device, and the selected material is the shape memory alloy. These devices can repeatedly adjust the deploy and fold states by changing the temperature, and also present a large energy dissipation to keep the stability of the structures in the vibration control. It can be observed that the fabricated two-way shape memory alloy actuator can present steady fold-deploy procedures more than five times, in which the recoverable rate is higher than 95.83%, and the required time in the complete deployi
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