Artykuły w czasopismach na temat „Hardware-Aware Algorithm design”
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An, Jianjing, Dezheng Zhang, Ke Xu i Dong Wang. "An OpenCL-Based FPGA Accelerator for Faster R-CNN". Entropy 24, nr 10 (23.09.2022): 1346. http://dx.doi.org/10.3390/e24101346.
Pełny tekst źródłaVo, Quang Hieu, Faaiz Asim, Batyrbek Alimkhanuly, Seunghyun Lee i Lokwon Kim. "Hardware Platform-Aware Binarized Neural Network Model Optimization". Applied Sciences 12, nr 3 (26.01.2022): 1296. http://dx.doi.org/10.3390/app12031296.
Pełny tekst źródłaFung, Wing On, i Tughrul Arslan. "A power-aware algorithm for the design of reconfigurable hardware during high level placement". International Journal of Knowledge-based and Intelligent Engineering Systems 12, nr 3 (21.10.2008): 237–44. http://dx.doi.org/10.3233/kes-2008-12306.
Pełny tekst źródłaPetschenig, Horst, i Robert Legenstein. "Quantized rewiring: hardware-aware training of sparse deep neural networks". Neuromorphic Computing and Engineering 3, nr 2 (26.05.2023): 024006. http://dx.doi.org/10.1088/2634-4386/accd8f.
Pełny tekst źródłaSINHA, SHARAD, UDIT DHAWAN i THAMBIPILLAI SRIKANTHAN. "EXTENDED COMPATIBILITY PATH BASED HARDWARE BINDING: AN ADAPTIVE ALGORITHM FOR HIGH LEVEL SYNTHESIS OF AREA-TIME EFFICIENT DESIGNS". Journal of Circuits, Systems and Computers 23, nr 09 (25.08.2014): 1450131. http://dx.doi.org/10.1142/s021812661450131x.
Pełny tekst źródłaGan, Jiayan, Ang Hu, Ziyi Kang, Zhipeng Qu, Zhanxiang Yang, Rui Yang, Yibing Wang, Huaizong Shao i Jun Zhou. "SAS-SEINet: A SNR-Aware Adaptive Scalable SEI Neural Network Accelerator Using Algorithm–Hardware Co-Design for High-Accuracy and Power-Efficient UAV Surveillance". Sensors 22, nr 17 (30.08.2022): 6532. http://dx.doi.org/10.3390/s22176532.
Pełny tekst źródłaZhang, Yue, Shuai Jiang, Yue Cao, Jiarong Xiao, Chengkun Li, Xuan Zhou i Zhongjun Yu. "Hardware-Aware Design of Speed-Up Algorithms for Synthetic Aperture Radar Ship Target Detection Networks". Remote Sensing 15, nr 20 (17.10.2023): 4995. http://dx.doi.org/10.3390/rs15204995.
Pełny tekst źródłaPerleberg, Murilo, Vinicius Borges, Vladimir Afonso, Daniel Palomino, Luciano Agostini i Marcelo Porto. "6WR: A Hardware Friendly 3D-HEVC DMM-1 Algorithm and its Energy-Aware and High-Throughput Design". IEEE Transactions on Circuits and Systems II: Express Briefs 67, nr 5 (maj 2020): 836–40. http://dx.doi.org/10.1109/tcsii.2020.2983959.
Pełny tekst źródłaArif, Muhammad, Omar S. Sonbul, Muhammad Rashid, Mohsin Murad i Mohammed H. Sinky. "A Unified Point Multiplication Architecture of Weierstrass, Edward and Huff Elliptic Curves on FPGA". Applied Sciences 13, nr 7 (25.03.2023): 4194. http://dx.doi.org/10.3390/app13074194.
Pełny tekst źródłaHsu, Bay-Yuan, Chih-Ya Shen, Hao Shan Yuan, Wang-Chien Lee i De-Nian Yang. "Social-Aware Group Display Configuration in VR Conference". Proceedings of the AAAI Conference on Artificial Intelligence 38, nr 8 (24.03.2024): 8517–25. http://dx.doi.org/10.1609/aaai.v38i8.28695.
Pełny tekst źródłaPerleberg, Murilo Roschildt, Vladimir Afonso, Ruhan Conceição, Altamiro Susin, Luciano Agostini, Marcelo Porto i Bruno Zatt. "Energy and Rate-Aware Design for HEVC Motion Estimation Based on Pareto Efficiency". Journal of Integrated Circuits and Systems 13, nr 1 (24.08.2018): 1–12. http://dx.doi.org/10.29292/jics.v13i1.18.
Pełny tekst źródłaSulaiman, Muhammad Bintang Gemintang, Jin-Yu Lin, Jian-Bai Li, Cheng-Ming Shih, Kai-Cheung Juang i Chih-Cheng Lu. "SRAM-Based CIM Architecture Design for Event Detection". Sensors 22, nr 20 (16.10.2022): 7854. http://dx.doi.org/10.3390/s22207854.
Pełny tekst źródłaYang, Jiacheng, Xiaoming Wang i Jianwu Dang. "On the Algorithm of the Medical Diagnostic Decision Support System under the Mobile Platform". Open Electrical & Electronic Engineering Journal 8, nr 1 (31.12.2014): 589–93. http://dx.doi.org/10.2174/1874129001408010589.
Pełny tekst źródłaDiaz, Kristian, i Ying-Khai Teh. "Design and Power Management of a Secured Wireless Sensor System for Salton Sea Environmental Monitoring". Electronics 9, nr 4 (25.03.2020): 544. http://dx.doi.org/10.3390/electronics9040544.
Pełny tekst źródłaTrevithick, Alex, Matthew Chan, Michael Stengel, Eric Chan, Chao Liu, Zhiding Yu, Sameh Khamis, Manmohan Chandraker, Ravi Ramamoorthi i Koki Nagano. "Real-Time Radiance Fields for Single-Image Portrait View Synthesis". ACM Transactions on Graphics 42, nr 4 (26.07.2023): 1–15. http://dx.doi.org/10.1145/3592460.
Pełny tekst źródłaSekanina, Lukas. "Evolutionary Algorithms in Approximate Computing: A Survey". Journal of Integrated Circuits and Systems 16, nr 2 (16.08.2021): 1–12. http://dx.doi.org/10.29292/jics.v16i2.499.
Pełny tekst źródłaZhao, Zhongyuan, Weiguang Sheng, Jinchao Li, Pengfei Ye, Qin Wang i Zhigang Mao. "Similarity-Aware Architecture/Compiler Co-Designed Context-Reduction Framework for Modulo-Scheduled CGRA". Electronics 10, nr 18 (9.09.2021): 2210. http://dx.doi.org/10.3390/electronics10182210.
Pełny tekst źródłaGuo, Peng, Hong Ma, Ruizhi Chen i Donglin Wang. "A High-Efficiency FPGA-Based Accelerator for Binarized Neural Network". Journal of Circuits, Systems and Computers 28, supp01 (1.12.2019): 1940004. http://dx.doi.org/10.1142/s0218126619400048.
Pełny tekst źródłaGao, Han, Zhangqin Huang, Xiaobo Zhang i Huapeng Yang. "Research and Design of a Decentralized Edge-Computing-Assisted LoRa Gateway". Future Internet 15, nr 6 (27.05.2023): 194. http://dx.doi.org/10.3390/fi15060194.
Pełny tekst źródłaDi, Xinkai, Hai-Gang Yang, Yiping Jia, Zhihong Huang i Ning Mao. "Exploring Efficient Acceleration Architecture for Winograd-Transformed Transposed Convolution of GANs on FPGAs". Electronics 9, nr 2 (7.02.2020): 286. http://dx.doi.org/10.3390/electronics9020286.
Pełny tekst źródłaMeng, Yang. "Analysis of Performance Improvement of Real-time Internet of Things Application Data Processing in the Movie Industry Platform". Computational Intelligence and Neuroscience 2022 (10.10.2022): 1–9. http://dx.doi.org/10.1155/2022/5237252.
Pełny tekst źródłaLe-Tuan, Anh, Conor Hayes, Manfred Hauswirth i Danh Le-Phuoc. "Pushing the Scalability of RDF Engines on IoT Edge Devices". Sensors 20, nr 10 (14.05.2020): 2788. http://dx.doi.org/10.3390/s20102788.
Pełny tekst źródłaHajj, Hazem, Wassim El-Hajj, Mehiar Dabbagh i Tawfik R. Arabi. "An Algorithm-Centric Energy-Aware Design Methodology". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, nr 11 (listopad 2014): 2431–35. http://dx.doi.org/10.1109/tvlsi.2013.2289906.
Pełny tekst źródłaRamos, Sabela, i Torsten Hoefler. "Cache Line Aware Algorithm Design for Cache-Coherent Architectures". IEEE Transactions on Parallel and Distributed Systems 27, nr 10 (1.10.2016): 2824–37. http://dx.doi.org/10.1109/tpds.2016.2516540.
Pełny tekst źródłaGoncalves, Paulo, Candido Moraes, Marcelo Porto i Guilherme Correa. "Complexity-Aware TZS Algorithm for Mobile Video Encoders". Journal of Integrated Circuits and Systems 14, nr 3 (27.12.2019): 1–9. http://dx.doi.org/10.29292/jics.v14i3.60.
Pełny tekst źródłaChen, Yi-Jung, Chia-Lin Yang i Yen-Sheng Chang. "An architectural co-synthesis algorithm for energy-aware Network-on-Chip design". Journal of Systems Architecture 55, nr 5-6 (maj 2009): 299–309. http://dx.doi.org/10.1016/j.sysarc.2009.02.002.
Pełny tekst źródłaChatterjee, Subarna, Mark F. Pekala, Lev Kruglyak i Stratos Idreos. "Limousine: Blending Learned and Classical Indexes to Self-Design Larger-than-Memory Cloud Storage Engines". Proceedings of the ACM on Management of Data 2, nr 1 (12.03.2024): 1–28. http://dx.doi.org/10.1145/3639302.
Pełny tekst źródłaChatterjee, Subarna, Meena Jagadeesan, Wilson Qin i Stratos Idreos. "Cosine". Proceedings of the VLDB Endowment 15, nr 1 (wrzesień 2021): 112–26. http://dx.doi.org/10.14778/3485450.3485461.
Pełny tekst źródłaMirzaei, Shahnam, Ryan Kastner i Anup Hosangadi. "Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs". International Journal of Reconfigurable Computing 2010 (2010): 1–17. http://dx.doi.org/10.1155/2010/697625.
Pełny tekst źródłaSudarshan, Deeksha, Chirag Khandelwal, Linge Gowda B M, Kiran Kumar Bijjaragi i Rekha S S. "Resource Centric Analysis of RSA and ECC Algorithms on FPGA". ITM Web of Conferences 56 (2023): 01006. http://dx.doi.org/10.1051/itmconf/20235601006.
Pełny tekst źródłaLi, Yihang. "Sparse-Aware Deep Learning Accelerator". Highlights in Science, Engineering and Technology 39 (1.04.2023): 305–10. http://dx.doi.org/10.54097/hset.v39i.6544.
Pełny tekst źródłaYe, Wenbin, i Ya Jun Yu. "Power Oriented Design of Linear Phase FIR Filters". Journal of Circuits, Systems and Computers 25, nr 07 (22.04.2016): 1650075. http://dx.doi.org/10.1142/s0218126616500754.
Pełny tekst źródłaBelakaria, Syrine, Aryan Deshwal, Nitthilan Kannappan Jayakodi i Janardhan Rao Doppa. "Uncertainty-Aware Search Framework for Multi-Objective Bayesian Optimization". Proceedings of the AAAI Conference on Artificial Intelligence 34, nr 06 (3.04.2020): 10044–52. http://dx.doi.org/10.1609/aaai.v34i06.6561.
Pełny tekst źródłaChoudhury, Priyanka, Kanchan Manna, Vivek Rai i Sambhu Nath Pradhan. "Thermal-Aware Partitioning and Encoding of Power-Gated FSM". Journal of Circuits, Systems and Computers 28, nr 09 (sierpień 2019): 1950144. http://dx.doi.org/10.1142/s0218126619501445.
Pełny tekst źródłaWang, Rongrong, Rui Tan, Zhenyu Yan i Chris Xiaoxuan Lu. "Orientation-Aware 3D SLAM in Alternating Magnetic Field from Powerlines". Proceedings of the ACM on Interactive, Mobile, Wearable and Ubiquitous Technologies 7, nr 4 (19.12.2023): 1–25. http://dx.doi.org/10.1145/3631446.
Pełny tekst źródłaParane, Khyamling, B. M. Prabhu Prasad i Basavaraj Talawar. "YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs". Journal of Circuits, Systems and Computers 28, nr 12 (listopad 2019): 1950202. http://dx.doi.org/10.1142/s0218126619502025.
Pełny tekst źródłaDenoyelle, Nicolas, John Tramm, Kazutomo Yoshii, Swann Perarnau i Pete Beckman. "NUMA-AWARE DATA MANAGEMENT FOR NEUTRON CROSS SECTION DATA IN CONTINUOUS ENERGY MONTE CARLO NEUTRON TRANSPORT SIMULATION". EPJ Web of Conferences 247 (2021): 04020. http://dx.doi.org/10.1051/epjconf/202124704020.
Pełny tekst źródłaLandmann, Christoph, i Rolf Kall. "Graphical Hardware Description as a High-Level Design Entry Method for FPGA-Based Data Acquisition Systems". Key Engineering Materials 613 (maj 2014): 296–306. http://dx.doi.org/10.4028/www.scientific.net/kem.613.296.
Pełny tekst źródłaAnnaz, Fawaz. "UAV Testbed Training Platform development using Panda3d". Industrial Robot: An International Journal 42, nr 5 (17.08.2015): 450–56. http://dx.doi.org/10.1108/ir-01-2015-0017.
Pełny tekst źródłaSrinath, B., Rajesh Verma, Abdulwasa Bakr Barnawi, Ramkumar Raja, Mohammed Abdul Muqeet, Neeraj Kumar Shukla, A. Ananthi Christy, C. Bharatiraja i Josiah Lange Munda. "An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts". Electronics 10, nr 22 (15.11.2021): 2795. http://dx.doi.org/10.3390/electronics10222795.
Pełny tekst źródłaRen, Jiankang, Chunxiao Liu, Chi Lin, Ran Bi, Simeng Li, Zheng Wang, Yicheng Qian, Zhichao Zhao i Guozhen Tan. "Protection Window Based Security-Aware Scheduling against Schedule-Based Attacks". ACM Transactions on Embedded Computing Systems 22, nr 5s (9.09.2023): 1–22. http://dx.doi.org/10.1145/3609098.
Pełny tekst źródłaDas, Apangshu, Yallapragada C. Hareesh i Sambhu Nath Pradhan. "NSGA-II Based Thermal-Aware Mixed Polarity Dual Reed–Muller Network Synthesis Using Parallel Tabular Technique". Journal of Circuits, Systems and Computers 29, nr 15 (2.07.2020): 2020008. http://dx.doi.org/10.1142/s021812662020008x.
Pełny tekst źródłaYe, Yunfei, Ning Wu, Xiaoqiang Zhang, Liling Dong i Fang Zhou. "An Optimized Design for Compact Masked AES S-Box Based on Composite Field and Common Subexpression Elimination Algorithm". Journal of Circuits, Systems and Computers 27, nr 11 (6.06.2018): 1850171. http://dx.doi.org/10.1142/s0218126618501712.
Pełny tekst źródłaLee, Kyu-Bae, Jina Park, Eunjin Choi, Mingi Jeon i Woojoo Lee. "Developing a TEI-Aware PMIC for Ultra-Low-Power System-on-Chips". Energies 15, nr 18 (16.09.2022): 6780. http://dx.doi.org/10.3390/en15186780.
Pełny tekst źródłaLIM, PILOK, KI-SEOK CHUNG i TAEWHAN KIM. "THERMAL-AWARE HIGH-LEVEL SYNTHESIS BASED ON NETWORK FLOW METHOD". Journal of Circuits, Systems and Computers 18, nr 05 (sierpień 2009): 965–84. http://dx.doi.org/10.1142/s0218126609005472.
Pełny tekst źródłaChaudhry, M. A. R., Z. Asad, A. Sprintson i J. Hu. "Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies". VLSI Design 2011 (28.04.2011): 1–9. http://dx.doi.org/10.1155/2011/892310.
Pełny tekst źródłaG., Muneeswari, Ahilan A., Rajeshwari R, Kannan K. i John Clement Singh C. "Trust And Energy-Aware Routing Protocol for Wireless Sensor Networks Based on Secure Routing". International journal of electrical and computer engineering systems 14, nr 9 (14.11.2023): 1015–22. http://dx.doi.org/10.32985/ijeces.14.9.6.
Pełny tekst źródłaCiuffoletti, Augusto. "Power-Aware Synchronization of a Software Defined Clock". Journal of Sensor and Actuator Networks 8, nr 1 (18.01.2019): 11. http://dx.doi.org/10.3390/jsan8010011.
Pełny tekst źródłaTan, Junyan, i Chunhua Cai. "An Efficient Partitioning Algorithm Based on Hypergraph for 3D Network-On-Chip Architecture Floorplanning". Journal of Circuits, Systems and Computers 28, nr 05 (maj 2019): 1950075. http://dx.doi.org/10.1142/s0218126619500750.
Pełny tekst źródłaYoon, Hyejung, Kyungwoon Cho i Hyokyung Bahn. "Storage Type and Hot Partition Aware Page Reclamation for NVM Swap in Smartphones". Electronics 11, nr 3 (27.01.2022): 386. http://dx.doi.org/10.3390/electronics11030386.
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