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Artykuły w czasopismach na temat "Hardware-Aware Algorithm design"
An, Jianjing, Dezheng Zhang, Ke Xu i Dong Wang. "An OpenCL-Based FPGA Accelerator for Faster R-CNN". Entropy 24, nr 10 (23.09.2022): 1346. http://dx.doi.org/10.3390/e24101346.
Pełny tekst źródłaVo, Quang Hieu, Faaiz Asim, Batyrbek Alimkhanuly, Seunghyun Lee i Lokwon Kim. "Hardware Platform-Aware Binarized Neural Network Model Optimization". Applied Sciences 12, nr 3 (26.01.2022): 1296. http://dx.doi.org/10.3390/app12031296.
Pełny tekst źródłaFung, Wing On, i Tughrul Arslan. "A power-aware algorithm for the design of reconfigurable hardware during high level placement". International Journal of Knowledge-based and Intelligent Engineering Systems 12, nr 3 (21.10.2008): 237–44. http://dx.doi.org/10.3233/kes-2008-12306.
Pełny tekst źródłaPetschenig, Horst, i Robert Legenstein. "Quantized rewiring: hardware-aware training of sparse deep neural networks". Neuromorphic Computing and Engineering 3, nr 2 (26.05.2023): 024006. http://dx.doi.org/10.1088/2634-4386/accd8f.
Pełny tekst źródłaSINHA, SHARAD, UDIT DHAWAN i THAMBIPILLAI SRIKANTHAN. "EXTENDED COMPATIBILITY PATH BASED HARDWARE BINDING: AN ADAPTIVE ALGORITHM FOR HIGH LEVEL SYNTHESIS OF AREA-TIME EFFICIENT DESIGNS". Journal of Circuits, Systems and Computers 23, nr 09 (25.08.2014): 1450131. http://dx.doi.org/10.1142/s021812661450131x.
Pełny tekst źródłaGan, Jiayan, Ang Hu, Ziyi Kang, Zhipeng Qu, Zhanxiang Yang, Rui Yang, Yibing Wang, Huaizong Shao i Jun Zhou. "SAS-SEINet: A SNR-Aware Adaptive Scalable SEI Neural Network Accelerator Using Algorithm–Hardware Co-Design for High-Accuracy and Power-Efficient UAV Surveillance". Sensors 22, nr 17 (30.08.2022): 6532. http://dx.doi.org/10.3390/s22176532.
Pełny tekst źródłaZhang, Yue, Shuai Jiang, Yue Cao, Jiarong Xiao, Chengkun Li, Xuan Zhou i Zhongjun Yu. "Hardware-Aware Design of Speed-Up Algorithms for Synthetic Aperture Radar Ship Target Detection Networks". Remote Sensing 15, nr 20 (17.10.2023): 4995. http://dx.doi.org/10.3390/rs15204995.
Pełny tekst źródłaPerleberg, Murilo, Vinicius Borges, Vladimir Afonso, Daniel Palomino, Luciano Agostini i Marcelo Porto. "6WR: A Hardware Friendly 3D-HEVC DMM-1 Algorithm and its Energy-Aware and High-Throughput Design". IEEE Transactions on Circuits and Systems II: Express Briefs 67, nr 5 (maj 2020): 836–40. http://dx.doi.org/10.1109/tcsii.2020.2983959.
Pełny tekst źródłaArif, Muhammad, Omar S. Sonbul, Muhammad Rashid, Mohsin Murad i Mohammed H. Sinky. "A Unified Point Multiplication Architecture of Weierstrass, Edward and Huff Elliptic Curves on FPGA". Applied Sciences 13, nr 7 (25.03.2023): 4194. http://dx.doi.org/10.3390/app13074194.
Pełny tekst źródłaHsu, Bay-Yuan, Chih-Ya Shen, Hao Shan Yuan, Wang-Chien Lee i De-Nian Yang. "Social-Aware Group Display Configuration in VR Conference". Proceedings of the AAAI Conference on Artificial Intelligence 38, nr 8 (24.03.2024): 8517–25. http://dx.doi.org/10.1609/aaai.v38i8.28695.
Pełny tekst źródłaRozprawy doktorskie na temat "Hardware-Aware Algorithm design"
Seznec, Mickaël. "From the algorithm to the targets, optimization flow for high performance computing on embedded GPUs". Electronic Thesis or Diss., université Paris-Saclay, 2021. http://www.theses.fr/2021UPASG074.
Pełny tekst źródłaCurrent digital processing algorithms require more computing power to achieve more accurate results and process larger data. In the meantime, hardware architectures are becoming more specialized, with highly efficient accelerators designed for specific tasks. In this context, the path of deployment from the algorithm to the implementation becomes increasingly complex. It is, therefore, crucial to determine how algorithms can be modified to take advantage of new hardware capabilities. Our study focused on graphics processing units (GPUs), a massively parallel processor. Our algorithmic work was done in the context of radio-astronomy or optical flow estimation and consisted of finding the best adaptation of the software to the hardware. At the level of a mathematical operator, we modified the traditional image convolution algorithm to use the matrix units and showed that its performance doubles for large convolution kernels. At a broader method level, we evaluated linear solvers for the combined local-global optical flow to find the most suitable one on GPU. With additional optimizations, such as iteration fusion or memory buffer re-utilization, the method is twice as fast as the initial implementation, running at 60 frames per second on an embedded platform (30 W). Finally, we also pointed out the interest of this hardware-aware algorithm design method in the context of deep neural networks. For that, we showed the hybridization of a convolutional neural network for optical flow estimation with a pre-trained image classification network, MobileNet, that was initially designed for efficient image classification on low-power platforms
Wang, Ya-Ting, i 王雅婷. "Algorithm and Hardware Architecture Design of Perception-Aware Motion Compensated Frame Rate Up-Conversion". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/50999594566970652643.
Pełny tekst źródła臺灣大學
電子工程學研究所
98
Frame rate up-conversion (FRUC) is a technique converting video sequence from lower frame rate to a higher one, which is originally widely-used in the video compression system to reconstruct frames at the decoder side that skipped by the encoder, and also applied in the high frame rate LCD system nowadays to reduce motion artifacts. Among the motion blur reduction methods, motion-compensated frame interpolation (MCFI) yields the best interpolation results by taking the motion information into consideration and no decrease in the overall brightness. However, the cost is high, since the process to estimate and compensate motions in the MCFI algorithm is computationally expensive, and with high bandwidth and memory requirements. The target application of this work is the HDTV system using LCD with 120Hz refresh rate, where a cost-effective MCFI hardware is desirable for such system, and the frame rate that is much higher than the sampling rate of human eye motivated us to seek cost reduction solution with the perceptual characteristics of human eye. In this thesis, a psychophysical experiment has been conducted and the capability of human to distinct the difference between the motions displayed with 60fps and 120fps is studied. Where the difference of motions with velocity under 3 °/sec and with duration under 100 ms in 60fps and 120fps has proved to be hard-to-detective for human eyes. Base on the psychophysical experiment results, a novel hardware-oriented perception-aware motion-compensated frame interpolation algorithm is proposed. For the VLSI hardware design, the target specification is set to 1920x1080 frame size, with throughput of 60 interpolated frames per second. The hardware is implemented with Verilog-HDL and synthesized with SYNOPSYS Design Compiler. Faraday 90um cell library is adopted to design the hardware. The total gate count is 212K.
Pedram, Ardavan. "Algorithm/architecture codesign of low power and high performance linear algebra compute fabrics". 2013. http://hdl.handle.net/2152/21364.
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Części książek na temat "Hardware-Aware Algorithm design"
Lin, Ji, Wei-Ming Chen i Song Han. "Algorithm-System Co-design for Efficient and Hardware-Aware Embedded Machine Learning". W Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, 349–70. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-39932-9_14.
Pełny tekst źródłaChien, Been-Chian, i Shiang-Yi He. "A Generic Context Interpreter for Pervasive Context-Aware Systems". W Mobile and Handheld Computing Solutions for Organizations and End-Users, 308–21. IGI Global, 2013. http://dx.doi.org/10.4018/978-1-4666-2785-7.ch017.
Pełny tekst źródłaRöhm, Uwe. "OLAP with a Database Cluster". W Database Technologies, 829–46. IGI Global, 2009. http://dx.doi.org/10.4018/978-1-60566-058-5.ch047.
Pełny tekst źródłaStreszczenia konferencji na temat "Hardware-Aware Algorithm design"
Wells, Joshua W., Jayaram Natarajan, Abhijit Chatterjee i Irtaza Barlas. "Real-Time, Content Aware Camera -- Algorithm -- Hardware Co-Adaptation for Minimal Power Video Encoding". W 2012 25th International Conference on VLSI Design. IEEE, 2012. http://dx.doi.org/10.1109/vlsid.2012.78.
Pełny tekst źródłaWing On Fung i T. Arslan. "A Power-Aware Algorithm for the Design of Reconfigurable Hardware during High Level Placement". W 2007 2nd NASA/ESA Conference on Adaptive Hardware and Systems. IEEE, 2007. http://dx.doi.org/10.1109/ahs.2007.15.
Pełny tekst źródłaBandic, Medina, Sebastian Feld i Carmen G. Almudever. "Full-stack quantum computing systems in the NISQ era: algorithm-driven and hardware-aware compilation techniques". W 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2022. http://dx.doi.org/10.23919/date54114.2022.9774643.
Pełny tekst źródłaBenmeziane, Hadjer, Kaoutar El Maghraoui, Hamza Ouarnoughi, Smail Niar, Martin Wistuba i Naigang Wang. "Hardware-Aware Neural Architecture Search: Survey and Taxonomy". W Thirtieth International Joint Conference on Artificial Intelligence {IJCAI-21}. California: International Joint Conferences on Artificial Intelligence Organization, 2021. http://dx.doi.org/10.24963/ijcai.2021/592.
Pełny tekst źródłaVillegas-Pachon, C., R. Carmona-Galan, J. Fernandez-Berni i A. Rodriguez-Vazquez. "Hardware-aware performance evaluation for the co-design of image sensors and vision algorithms". W 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). IEEE, 2016. http://dx.doi.org/10.1109/smacd.2016.7520722.
Pełny tekst źródłaKothari, Aadi, Timothy Talty, Scott Huxtable i Haibo Zeng. "Energy-Efficient and Context-Aware Computing in Software-Defined Vehicles for Advanced Driver Assistance Systems (ADAS)". W WCX SAE World Congress Experience. 400 Commonwealth Drive, Warrendale, PA, United States: SAE International, 2024. http://dx.doi.org/10.4271/2024-01-2051.
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