Gotowe bibliografie tematyczne / GDI TECHNIQUE

Spis treści

Artykuły w czasopismach

Gotowa bibliografia na temat „GDI TECHNIQUE”

Autor: Grafiati

Data publikacji: 11 września 2023

Data aktualizacji: 13 czerwca 2025

Utwórz poprawne odniesienie w stylach APA, MLA, Chicago, Harvard i wielu innych

Wybierz rodzaj źródła:

Zobacz listy aktualnych artykułów, książek, rozpraw, streszczeń i innych źródeł naukowych na temat „GDI TECHNIQUE”.

Przycisk „Dodaj do bibliografii” jest dostępny obok każdej pracy w bibliografii. Użyj go – a my automatycznie utworzymy odniesienie bibliograficzne do wybranej pracy w stylu cytowania, którego potrzebujesz: APA, MLA, Harvard, Chicago, Vancouver itp.

Możesz również pobrać pełny tekst publikacji naukowej w formacie „.pdf” i przeczytać adnotację do pracy online, jeśli odpowiednie parametry są dostępne w metadanych.

Artykuły w czasopismach na temat "GDI TECHNIQUE"

Saxena, Rimjhim, and Kiran Sharma. "Delay Optimization and Power Optimization of 4-Bit ALU Designed in FS-GDI Technique." SMART MOVES JOURNAL IJOSCIENCE 6, no. 2 (2020): 1–12. http://dx.doi.org/10.24113/ijoscience.v6i2.264.

Pełny tekst źródła

Streszczenie:

In this thesis proposed a reduction of delay, leakage current, leakage power. First find out the leakage current and leakage power. This thesis uses a gate diffusion input technique. By using this no of transistor is reduced. If number of transistor is reduced, area is also reduced, leakage current also affected. To study all parameter in this thesis uses a 2x1 MUX, 4x1MUX,16x1 MUX and ALU. Applying a GDI technique and also implemented by using a CMOS technique. Then do comparisons on GDI and CMOS technique and do a capacitance calculation. To implement all those things use a microwind 3.1 and DSCH 2.0. It is an Electronic Design Automation (EDA) environment that allows implementing a integrating in a single framework different applications and tools, allowing supporting all the stages of IC design and verification from a single environment. The resulting layout must verify some geometric rules dependent on the technology (design rules). Now checked with a Design Rule Checker (DRC) to find any error in the layout diagram and them simulation is performed. In implementing and do a comparisons of GDI and CMOS technique we get a 75% advantage in 2x1 MUX in counting the number of transistor. In 4x1 MUX we get again a 75% gain in the number of transistor. In 8x1 MUX, give a 78% benefits in the number of transistor. In 16x1 MUX, give a 81% benefits in the number of transistor. In 1 bit ALU give a 54% benefits in the number of transistor. If related power consumption, get a 74% benefits in comparisons of GDI and CMOS technique in 2x1 MUX. In 4x1mux give the advantage of 79% in the power consumption in comparisons of GDI and CMOS technique. In 8x1mux give the advantage of 78% in the power consumption in comparisons of GDI and CMOS technique. In 16x1mux give the advantage of 79% in the power consumption comparisons of GDI and CMOS technique. In bit ALU give the advantage of 64% in the power consumption in comparisons of GDI and CMOS technique.

Style APA, Harvard, Vancouver, ISO itp.

A.S., Prabhu, Naveena B, Parimaladevi K, Samundeswari M, and Thilagavathy P. "Serial Divider Using Modified GDI Technique." IJIREEICE 3, no. 10 (2015): 73–76. http://dx.doi.org/10.17148/ijireeice.2015.31017.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Solomon, Merrin Mary, Neeraj Gupta, and Rashmi Gupta. "HIGH SPEED ADDER USING GDI TECHNIQUE." International Journal of Engineering Technologies and Management Research 5, no. 2 (2020): 130–36. http://dx.doi.org/10.29121/ijetmr.v5.i2.2018.634.

Pełny tekst źródła

Streszczenie:

Full adder is an important component for designing a processor. As the complexity of the circuit increases, the speed of operation becomes a major concern. Nowadays there are various architectures that exist for full adders. In this paper we will discuss about designing a low power and high speed full adder using Gate Diffusion Input technique. GDI is one of the present day methods through which one can design logical circuits. This technique will reduce power consumption, propagation delay, and area of digital circuits as well as maintain low complexity of logic design. The performance of the proposed design is compared with the contemporary full adder designs.

Style APA, Harvard, Vancouver, ISO itp.

Anitha, M., J. Princy Joice, and Rexlin Sheeba.I. "A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (2015): 173. http://dx.doi.org/10.11591/ijres.v4.i3.pp173-177.

Pełny tekst źródła

Streszczenie:

Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to reduce the number of transistors compared to conventional CSLA and made comparison with known conventional adders which gives that the usage of carry-strength signals allows high-speed adders to be realised at lower cost as well as consuming lower power than previous designs. Hence, this paper we are concentrating on the area level &amp;we are reducing the power using modified GDI logic.

Style APA, Harvard, Vancouver, ISO itp.

B Sangeeth Kumar,, Pyasa Dileep and A. Satyanarayana. "Design of Low Power & Area Efficient of 8-Bit Comparator using GDI Technique." International Journal for Modern Trends in Science and Technology, no. 8 (August 7, 2020): 62–65. http://dx.doi.org/10.46501/ijmtst060812.

Pełny tekst źródła

Streszczenie:

In this paper we are design a circuit based on data selector and distributor networks in which we will not realize the circuit based upon the expressions but off course the circuit which have designed will have internally some expression. In the recent trends the need for low power and less on-chip area is on high note for the portable devices. In this project we want to focus on the design constraints of VLSI. Innovative design of 8-Bit GDI based Comparator will be proposed and implemented. Optimization depends on selection of GDI Cell as well as selection of primary inputs to the terminals of GDI cell. 8-Bit GDI based Comparator will be designed and simulated using Tanner EDATool. Comparator has three main outputs where it can compare the weight of two words and generates three functions. GDI has the advantage of low power consumption because the total number of logic devices needed willbe less and it can also operate with high speed due to affective realization of logic using minimal hardware. Comparator circuits is designed using tanner tools and also observe the simulation results in H-SPICE attaining low power and less delay.

Style APA, Harvard, Vancouver, ISO itp.

Sehrawat, Arjun, Vandana Khanna, and Kushal Jindal. "Comparative Study of CMOS Logic and Modified GDI Technique for Basic Logic Gates and Code Convertor." International Journal of Advance Research and Innovation 9, no. 3 (2021): 70–85. http://dx.doi.org/10.51976/ijari.932111.

Pełny tekst źródła

Streszczenie:

For designing low power digital circuits with better reliability and performance along with less propagation delay, Gate Diffusion Input (GDI) is one such technique. It also significantly reduces the area and delay of a circuit. It is a low power technique which requires a smaller number of transistors to achieve desired outputs with lower design complexity as compared to CMOS logic or Pass Transistor Logic. In a basic GDI cell, 3 terminals namely Gate, Source and Drain are treated as inputs. In this work, circuits like logic gates, and Binary to Gray code convertor have been designed using CMOS logic and a Modified GDI technique. Also, the power dissipation of all these circuits have been calculated and compared for CMOS and Modified GDI. The designing and simulations have been done on Cadence Virtuoso tool in 90 nm technology and power supply voltage has been taken as 1 V.

Style APA, Harvard, Vancouver, ISO itp.

Tyagi, Priyanka, Sanjay Kumar Singh, and Piyush Dua. "Gate Diffusion Input Based 10-T CNTFET Power Efficient Full Adder." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 14, no. 4 (2021): 415–27. http://dx.doi.org/10.2174/2352096514666210106094136.

Pełny tekst źródła

Streszczenie:

Background: Full adder is the key element of digital electronics. The CNTFET is the most promising device in modern electronics. To enhance the performance of the full adder, CNTFET is used in place of the CMOS. Objective: To implement the high speed full adder circuit for advance applications of the digital world. Methods: Full adder circuit with a new Gate diffusion technique has been implemented in this work. This is a comparative study of the 10-T CNTFET full adder with GDI technique and the 10-T Finfet based full adder using GDI technique. Ultra-low-power feature is the additional advantage of the GDI technique. This technology provides the full swing voltage to the circuit. Moreover, it also reduces the number of transistors required. This technique has been used with CNTFET to upgrade the full adder in terms of the dissipated power and product of power consumed and delay introduced in the circuit. Results: The proposed design shows that the low power dissipation comes out to be approximately 4.3nW at 0.5volts. The power delay product is 4.7x10-20 J at the same voltage level. The FinFET design also shows the better performance with GDI. But GDI enhances CNTFET based design power consumption by about 32% from the FinFET. Conclusions: CNTFET showed a better response due to good current conductivity as compared to the FinFET. This work has been implemented and simulated on the 32nm node technology.

Style APA, Harvard, Vancouver, ISO itp.

R., Manjunath. "LOW POWER OPTIMIZATION OF FULL ADDER CIRCUIT BASED ON GDI LOGIC FOR BIOMEDICAL APPLICATIONS." International Journal of Advanced Research 10, no. 10 (2022): 457–67. http://dx.doi.org/10.21474/ijar01/15511.

Pełny tekst źródła

Streszczenie:

Advanced Electronic Devices have recently become more prevalent, designers have opted for low power, quick speed, and compact designs and processes. Even though there are numerous design methodologies currently in use for VLSI system design optimization, very few design techniques produce solutions that are optimally optimal. GDI-based circuits are becoming increasingly important since they use less space, power, and energy. The GDI technique ensures minimal propagation delay, power, and area in low-power design strategies. For 45nm technology, the Cadence Virtuoso EDA tool is utilised to determine delay and power. The proposed designs examination of delay and power performance at 1.0V voltage produced positive findings. The Gate Diffusion Input concept serves as the foundation for the proposed design in this work. In order to achieve a full voltage swing of the output, a 1-bit full adder circuit design using GDI is demonstrated in this work. The GDI with the Full Swing Technique is presented in this work. Applying the suggested way to a 45nm complete adder from 14 Transistors. It is evident from the obtained simulation results that the suggested design uses the least power and the least amount of delay when compared to other full adder circuits that are already in use. Consequently, compared to previous full adder GDI circuit designs, the output voltage swing is in full and the overall power-delay product is improved by 60 percent.

Style APA, Harvard, Vancouver, ISO itp.

Gupta, Shashank, and Subodh Wairya. "Hybrid Code Converters using Modified GDI Technique." International Journal of Computer Applications 143, no. 7 (2016): 12–19. http://dx.doi.org/10.5120/ijca2016910248.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Hari Kishore, K., K. DurgaKoteswara Rao, G. Manvith, K. Biswanth, and P. Alekhya. "Area, power and delay efficient 2-bit magnitude comparator using modified gdi technique in tanner 180nm technology." International Journal of Engineering & Technology 7, no. 2.8 (2018): 222. http://dx.doi.org/10.14419/ijet.v7i2.8.10413.

Pełny tekst źródła

Streszczenie:

Of late, low power configuration took shape into the mostimportant concentrations in designing the latest VLSI circuits. By considering the same at the maximum priority, another outline of two-bit GDI based Magnitude or Digital Comparator are recommended and actualized with the assistance of Modified GDI transistors. Comparators are building blocks in advanced VLSI configuration circuits. In the current patterns the necessity for occupying less area in chip and low power compact devices. In this paper we introduced another Magnitude Comparator which willutilize low power, and gives a quick results and occupying less chip area in Modified GDI technology. The modified GDI procedure dependent extent comparator has favorable position of less control utilization as for different outline parameters; few on-chip zones secured as small number of transistors are utilized in circuit configuration when related with traditional CMOS size comparator. Either of the circuits is outlined and executed utilizing Tanner EDA Tool version 16.0 at 180nm processing technologies.

Style APA, Harvard, Vancouver, ISO itp.

Więcej źródeł

Oferujemy zniżki na wszystkie plany premium dla autorów, których prace zostały uwzględnione w tematycznych zestawieniach literatury. Skontaktuj się z nami, aby uzyskać unikalny kod promocyjny!