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Artykuły w czasopismach na temat „Gate oxide reliability”

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Data publikacji: 25 maja 2024

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1

Wan, Caiping, Yuanhao Zhang, Wenhao Lu, Niannian Ge, Tianchun Ye i Hengyu Xu. "Improving the reliability of MOS capacitor on 4H-SiC (0001) with phosphorus diffused polysilicon gate". Semiconductor Science and Technology 37, nr 5 (7.04.2022): 055008. http://dx.doi.org/10.1088/1361-6641/ac606d.

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Abstract The interface states and reliability of 4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) with thermal gate oxides have been researched widely. Several reports have researched the gate oxide process itself, but the effects of subsequent processes should not be ignored. In this paper, the reliability of thermal gate oxide films followed by polysilicon gate (poly-gate) process, which are widely used in MOSFET manufacture, and Al gates were compared. The poly-gate samples markedly affected the performance measured by time-zero dielectric breakdown and time-dependent dielectric breakdown methods because the phosphorus content diffused during poly-gate formatting; this was especially advantageous in reducing leakage current and improving the charge-to-breakdown (Q BD). After electronic characteristics measurements, scanning electron microscopy cross-sections were also used to analyze the breakdown mechanism. We observed an intermediate layer between the Al gate and the oxide that may cause the barrier height to be smaller than that of the poly-gate. The Al work function and polysilicon Fermi level determine the gate leakage currents and the resultant gate oxide reliability, whereas the Al2O3 gate sample has a smaller work function offset (0.7 eV) than ideal Al gate and poly-gate samples. The results imply that the reliability of the Al gate samples may be an intrinsic problem.

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2

Monsieur, F., E. Vincent, D. Roy, S. Bruyère, G. Pananakakis i G. Ghibaudo. "Gate oxide Reliability assessment optimization". Microelectronics Reliability 42, nr 9-11 (wrzesień 2002): 1505–8. http://dx.doi.org/10.1016/s0026-2714(02)00179-8.

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Fronheiser, Jody, Aveek Chatterjee, Ulrike Grossner, Kevin Matocha, Vinayak Tilak i Liang Chun Yu. "Evaluation of 4H-SiC Carbon Face Gate Oxide Reliability". Materials Science Forum 679-680 (marzec 2011): 354–57. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.354.

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The gate oxide reliability and channel mobility of carbon face (000-1) 4H Silicon Carbide (SiC) MOSFETs are investigated. Several gate oxidation processes including dry oxygen, pyrogenic steam, and nitrided oxides were investigated utilizing MOS capacitors for time dependent dielectric breakdown (TDDB), dielectric field strength, and MOSFETs for inversion layer mobility measurements. The results show the C-face can achieve reliability similar to the Si-face, however this is highly dependent on the gate oxide process. The reliability is inversely related to the field effect mobility where other research groups report that pyrogenic steam yields the highest electron mobility while this work shows it has weakest oxide in terms of dielectric strength and shortest time to failure.

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4

Lee, Seok-Woo. "Novel Dual Gate Oxide Process with Improved Gate Oxide Integrity Reliability". Electrochemical and Solid-State Letters 3, nr 1 (1999): 56. http://dx.doi.org/10.1149/1.1390957.

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5

Moazzami, R., i C. Hu. "Projecting gate oxide reliability and optimizing reliability screens". IEEE Transactions on Electron Devices 37, nr 7 (lipiec 1990): 1643–50. http://dx.doi.org/10.1109/16.55751.

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6

Weir, B. E., M. A. Alam, P. J. Silverman, F. Baumann, D. Monroe, J. D. Bude, G. L. Timp i in. "Ultra-thin gate oxide reliability projections". Solid-State Electronics 46, nr 3 (marzec 2002): 321–28. http://dx.doi.org/10.1016/s0038-1101(01)00103-4.

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7

Deivasigamani, Ravi, Gene Sheu, Aanand, Shao Wei Lu, Syed Sarwar Imam, Chiu-Chung Lai i Shao-Ming Yang. "Study of HCI Reliability for PLDMOS". MATEC Web of Conferences 201 (2018): 02001. http://dx.doi.org/10.1051/matecconf/201820102001.

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In this paper, we demonstrate electrical degradation due to hot carrier injection (HCI) stress for PLDMOS device. The lower gate current and the IDsat degradation at low gate voltage (VGS) and high drain voltage (VDS) is investigated. Hot Electrons, generated by impact ionization during stress, are injected into the gate oxide, creating negative fixed oxide charges and interface-states above the accumulation region and the channel. Increase of the drain-source current is induced by the negative fixed oxide charges. The physical model of the degradation has been proven combining experimental data and TCAD simulations.

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8

Senzaki, Junji, Atsushi Shimozato, Kozutoshi Kajima, Keiko Aryoshi, Takahito Kojima, Shinsuke Harada, Yasunori Tanaka, Hiroaki Himi i Hajime Okumura. "Electrical Properties of MOS Structures on 4H-SiC (11-20) Face". Materials Science Forum 740-742 (styczeń 2013): 621–24. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.621.

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Threshold voltage (VTH) instability, channel mobility and oxide reliability have been investigated for meta-oxide-semiconductor (MOS) structures on 4H-SiC (11-20) face using various gate oxidation procedures. Channel mobility of n-channel MOSFET with a gate oxide by pyrogenic oxidation is higher than that by dilute-DRY oxidation followed by a nitrous oxide (N2O) post-oxidation annealing (POA). On the other hand, oxide reliability for the pyrogenic oxides is poor compared with the dilute-DRY/N2O oxides. A Hydrogen POA is effective in an improvement of channel mobility for both oxides, but causes a harmful effect on VTH stability. Temperature dependence of VTH instability indicates that MOS structure grown by dilute-DRY followed by N2O POA is suitable for a practical use of SiC MOS power devices.

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9

Yamada, Keiichi, Osamu Ishiyama, Kentaro Tamura, Tamotsu Yamashita, Atsushi Shimozato, Tomohisa Kato, Junji Senzaki, Hirohumi Matsuhata i Makoto Kitabatake. "Reliability of Gate Oxides on 4H-SiC Epitaxial Surface Planarized by CMP Treatment". Materials Science Forum 778-780 (luty 2014): 545–48. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.545.

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This work reports about effect of SiC epitaxial-wafer surface planarization by chemo-mechanical polishing (CMP) treatment on electrical properties of SiC-MOS capacitor. We have observed the surface morphology of 4H-SiC epitaxial layer planarized by CMP treatment using a confocal differential interference microscope, and evaluated the reliability of gate oxides on this surface using constant current time-dependent dielectric breakdown (CC-TDDB) and current-voltage (I-V) characteristics. Surface roughness such as step bunching deteriorates drastically the reliability of gate oxide, while the epitaxial-surface planarization by CMP treatment improved oxide reliability due to the high uniformity of the oxide film thickness.

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10

Liang, Xiaowen, Jiangwei Cui, Jing Sun, Haonan Feng, Dan Zhang, Xiaojuan Pu, Xuefeng Yu i Qi Guo. "The Influence of 10 MeV Proton Irradiation on Silicon Carbide Power Metal-Oxide-Semiconductor Field-Effect Transistor". Journal of Nanoelectronics and Optoelectronics 17, nr 5 (1.05.2022): 814–19. http://dx.doi.org/10.1166/jno.2022.3255.

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The effects of 10 MeV proton irradiation on the threshold voltage and gate oxide reliability of SiC MOSFET are investigated. The negative shift of the threshold voltage was observed after irradiation, and the magnitude of the shift is exclusively related to the fluence and not the drain voltage. Moreover, proton irradiation leads up to the degeneration of oxide reliability. Experiment and simulation results indicate that the shift of the threshold voltage is caused by the total ionizing dose effect. Due to the superior blocking capabilities of the SiC MOSFET, the electric field of gate oxide is almost unaffected by the voltage applied to the drain, so the drift of threshold voltage is only related to particle fluence. The single event effect is responsible for the degradation of gate oxide reliability. The single event effect induces a transient high electric field in the gate oxide, which generates defects and affects the reliability of the gate oxide.

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11

Lee, Kwangwon, Young Ho Seo, Taeseop Lee, Kyeong Seok Park, Martin Domeij, Fredrik Allerstam i Thomas Neyer. "Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET". Materials Science Forum 1004 (lipiec 2020): 554–58. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.554.

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We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

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12

Hatakeyama, Tetsuo, Takuma Suzuki, Junji Senzaki, Kenji Fukuda, Hirofumi Matsuhata, Takashi Shinohe i Kazuo Arai. "Impact of the Wafer Quality on the Reliability of MOS Structure on the C-Face of 4H-SiC". Materials Science Forum 600-603 (wrzesień 2008): 783–86. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.783.

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We report on the reliability of the gate oxide on C-face of 4H-SiC. Constant current stress TDDB measurement shows that QBD of the gate oxide of f200 [μm] on C-face is as much as 18 [C/ cm2], which is much larger than the typical value (0.1[C/ cm2]) of that on Si-face of 4H-SiC. The lifetimes of the gate oxide under the electric field of 3[MV/cm] are roughly evaluated from the leakage characteristics and obtained QBD. The estimated lifetimes of the gate oxide of f600 [μm] are about 900 years. TDDB measurements of MOSs on two wafers, which have different dislocation densities, show that reliability of gate oxide on C-face is insensitive to the dislocation density. Meanwhile, reliability of the gate oxide is sensitive to the surface defect density: it is significantly degraded on the wafer, which has 2000 surface defects in a whole 2-inch wafer.

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13

Suzuki, Takuma, Junji Senzaki, Tetsuo Hatakeyama, Kenji Fukuda, Takashi Shinohe i Kazuo Arai. "Effect of Gate Wet Reoxidation on Reliability and Channel Mobility of Metal-Oxide-Semiconductor Field-Effect Transistors Fabricated on 4H-SiC(000-1)". Materials Science Forum 600-603 (wrzesień 2008): 791–94. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.791.

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The channel mobility and oxide reliability of metal-oxide-semiconductor field-effect transistors (MOSFETs) on 4H-SiC (0001) carbon face were investigated. The gate oxide was fabricated by using dry-oxidized film followed by pyrogenic reoxidation annealing (ROA). Significant improvements in the oxide reliability were observed by time-dependent dielectric breakdown (TDDB) measurement. Furthermore, the field-effect inversion channel mobility (μFE) of MOSFETs fabricated by using pyrogenic ROA was as high as that of conventional 4H-SiC (0001) MOSFETs having the pyrogenic-oxidized gate oxide. It is suggested that the pyrogenic ROA of dry oxide as a method of gate oxide fabrication satisfies both channel mobility and oxide reliability on 4H-SiC (0001) carbon-face MOSFETs.

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14

Zhou, Yaohui, Song Zhang, Qun Liu, Dejin Wang, Yaling Ma i Mincheng Li. "Composite Gate Oxide Method for Improving the Reliability and Leakage Performance of Deep Submicron CMOS Processes". Journal of Physics: Conference Series 2645, nr 1 (1.11.2023): 012009. http://dx.doi.org/10.1088/1742-6596/2645/1/012009.

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Abstract This article aims to address the issues of gate oxide reliability failure and leakage loss in SRAM circuits caused by the introduction of additional high-voltage devices in the 90 nm standard process. It investigates the corner thinning phenomenon using different gate oxide scheme. It analyzes the corresponding relationship between composite gate oxide and reliability and tests the leakage of the SRAM circuit. Research has shown that the use of composite gate oxide can effectively improve corner thinning. The ratio of thermal oxide to HTO in composite gate oxide directly affects GOI/TDDB. At the same time, the use of composite gate oxide also decreases device leakage to a certain extent. The standby leakage of SRAM circuits(Isb) can be reduced from 200 nA to less than 10 nA.

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15

Nam, Kab-Jin, Kee-Won Kwon i Byoungdeog Choi. "Reliability Analysis on TiN Gated NMOS Transistors". Science of Advanced Materials 13, nr 6 (1.06.2021): 1178–85. http://dx.doi.org/10.1166/sam.2021.3986.

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Compared to poly Si gate, metal gate has no gate depletions and experiences inversion capacitance gain, which makes an advantage for devices scaling. In this paper, we investigated the gate oxide leakage current and Time Dependent Dielectric Breakdown (TDDB) characteristics of TiN and poly Si electrodes with a 3.5 to 5 nm SiO2 dielectric thickness range. According to the Transmission Electron Microscope (TEM) analysis there is difference in oxide thickness. The SiO2 thickness of TiN gate electrode has been reduced by ~0.25 nm, considerably because of a scavenging effect. We normalized the reduced SiO2 thickness with an electrical oxide field, and there were no differences between the two electrodes in gate leakage current, accumulation breakdown voltage (BV), and accumulation TDDB lifetime. Therefore, we found the scavenging effect of TiN electrodes seems to affect little the leakage current and TDDB reliability of SiO2 dielectric. On the other hand, the BV and TDDB lifetime of TiN electrode in the inversion region are little bit better than that of the poly electrode. We think this differences are originated from the difference between TiN/SiO2 and poly Si/SiO2 interfaces.

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16

Lee, J. C., Chen Ih-Chin i Hu Chenming. "Modeling and characterization of gate oxide reliability". IEEE Transactions on Electron Devices 35, nr 12 (1988): 2268–78. http://dx.doi.org/10.1109/16.8802.

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17

Senzaki, Junji, Atsushi Shimozato, Kazutoshi Kojima, Tomohisa Kato, Yasunori Tanaka, Kenji Fukuda i Hajime Okumura. "Challenges of High-Performance and High-Reliablity in SiC MOS Structures". Materials Science Forum 717-720 (maj 2012): 703–8. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.703.

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Influences of wafer-related defect and gate oxide fabrication process on MOS characteristics with gate oxides thermally grown on 4H-SiC (0001) wafer have been investigated for a realization of SiC MOS power devices. The SiC MOS characteristics depend on the gate oxide fabrication process, and are improved by the increase of DRY oxidation temperature and the applying of N2O and H2 POAs. In addition, it was clearly shown that predominant origins of SiC MOS reliability degradation are wafer-related defects such as dislocation and surface defects of epitaxial layer. Moreover, the planarization of SiC epitaxial layer surface using a CMP treatment is effective technique for the improvement of SiC MOS reliability.

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18

Mengotti, Elena, Enea Bianda, Stephan Wirths, David Baumann, Jason Bettega i Joni Jormanainen. "High Temperature Gate Voltage Step-by-Step Test to Assess Reliability Differences in 1200 V SiC MOSFETs". Materials Science Forum 1004 (lipiec 2020): 1033–44. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.1033.

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In this paper, robustness and reliability differences related to the performance of the gate oxide of commercially-available 1200 V-rated planar and trench SiC MOSFETs have been investigated. Due to a thin gate oxide in SiC MOSFETs and to a naturally imperfect interface of the oxide layer (SiO2) with the SiC material, its quality and reliability become very important and could be a limiting factor of the SiC technology when compared to the Si one. A dedicated gate oxide step-by-step (VG SbS) tester has been prepared during which the gate voltage is varied with different profiles. Results of Fowler-Nordheim (FN), Time Dependent Dielectric Breakdown (TDDB) and three test runs of the VG SbS are presented in this paper. Both technologies show good reliability figures to allow the use in the application. Trench technology shows higher robustness limits whereas the extrapolated reliability at the rated gate voltage is superior for the planar one.

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19

Schlichting, Holger, Minwho Lim, Tom Becker, Birgit Kallinger i Tobias Erlbacher. "The Influence of Extended Defects in 4H-SiC Epitaxial Layers on Gate Oxide Performance and Reliability". Materials Science Forum 1090 (31.05.2023): 127–33. http://dx.doi.org/10.4028/p-4i3rhf.

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For the ongoing commercialization of power devices based on 4H-SiC, increasing the yield and improving the reliability of these devices is becoming more and more important. In this investigation, gate oxide on 4H-SiC was examined by time-zero dielectric breakdown (TZDB) and constant current stress (CCS) time-dependent dielectric breakdown (TDDB) method in order to get insights into the influence of the epitaxial defects on the gate oxide performance and reliability. For that purpose, MOS capacitors with different gate oxides have been fabricated. Crystal defects in the epitaxial layers have been detected and mapped by ultraviolet photoluminescence (UVPL) and interference contrast (DIC) imaging. The results of the comparison of electrical data and surface mapping data indicate a negative influence on the leakage current behavior for some extended epitaxial defects. Results from TDDB measurement indicated numerous extrinsic defects, which can be traced back to gate oxide processing conditions and defect densities.

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20

Kojima, Takahito, Shinsuke Harada, Keiko Ariyoshi, Junji Senzaki, Manabu Takei, Yoshiyuki Yonezawa, Yasunori Tanaka i Hajime Okumura. "Reliability Improvement and Optimization of Trench Orientation of 4H-SiC Trench-Gate Oxide". Materials Science Forum 778-780 (luty 2014): 537–40. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.537.

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Reliability of gate oxide for trench-gate MOSFET was improved by deposited oxide film with uniform thickness and high-temperature annealing after trench etching. Optimum wafer orientation and trench direction for the trench gate was investigated, and the gate oxide on (11-20) plane of carbon face exhibited the longest lifetime. Influences by the roughness of sidewall and the radius of trench corner are discussed.

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21

Park, Jong T., Dae N. Ha, Chong G. Yu, Byung G. Park i Jong D. Lee. "Diagnostic technique for projecting gate oxide reliability and device reliability". Microelectronics Reliability 37, nr 10-11 (październik 1997): 1421–24. http://dx.doi.org/10.1016/s0026-2714(97)00077-2.

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Xu, Heng Yu, Cai Ping Wan i Jin Ping Ao. "Reliability of 4H-SiC (0001) MOS Gate Oxide by NO Post-Oxide-Annealing". Materials Science Forum 954 (maj 2019): 109–13. http://dx.doi.org/10.4028/www.scientific.net/msf.954.109.

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In this work, we investigated the oxide reliability of 4H-SiC (0001) MOS capacitors, the oxide was fabricated about 60 nm by thermal oxidation temperature at 1350°C, the oxides than annealed at different temperatures and times in diluted NO (10% in N2). The 4H-SiC MOS structure was analyzed by C-V and I-V measurement. Compared the J-E curves and Weibull distribution curves of charge-to-breakdown for fives samples under different annealing temperature and time, it shows that the high annealing temperature improves the electrical properties as the lifetime enhanced. The mode value of field-to-breakdown (EBD) for thermal oxides by post-oxide-annealing in NO for 30 min at 1350°C was 10.09 MV/cm, the charge-to-breakdown (QBD) of this sample was the highest in all samples, and the QBD value at 63.2% cumulative failure rate was 0.15 C/cm2. The QBD of the sample annealing at 1200°C for 120 min was 0.06 C/ cm2. The effects of NO annealing in high temperature enhance the lifetime of electrical properties and field-to-breakdown obviously. It can be demonstrated that the annealing temperature as high as 1300°C for 30 min can be used to accelerate TDDB of SiC MOS gate oxide.

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Das, Mrinal K., Sarah K. Haney, Jim Richmond, Anthony Olmedo, Q. Jon Zhang i Zoltan Ring. "SiC MOSFET Reliability Update". Materials Science Forum 717-720 (maj 2012): 1073–76. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1073.

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Significant advancement has been made in the gate oxide reliability of SiC MOS devices to enable the commercial release of Cree’s Z-FET™ product. This paper discusses the key reliability results from Time-Dependent-Dielectric-Breakdown (TDDB) and High Temperature Gate Bias (HTGB) measurements that indicate that the SiC MOSFETs can demonstrate excellent lifetime and stable operation in the field.

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24

Cheung, Kin P. "On the “intrinsic” breakdown of thick gate oxide". Journal of Applied Physics 132, nr 14 (14.10.2022): 144505. http://dx.doi.org/10.1063/5.0118081.

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The thick gate oxide breakdown mechanism has become an important topic again due to the rising demand for power electronics. The failure of the percolation model in explaining the observed Weibull shape factor, β, seriously hampers the establishment of thick gate oxide breakdown models and the ability to project reliability from measurement data. In this work, lifetime shortening by oxide defects is simulated to produce degraded breakdown distributions that match experimentally observed βs. The result shows that even a low density of defects with the right energy is enough to greatly degrade β for thick oxides. Strong area scaling for thin oxides counters this sensitivity to defects effectively and explains why the percolation model is successful in thin oxides but not in thick oxides. Only defects with the appropriate energy can degrade the breakdown distribution. The required energy is consistent with oxygen vacancy Eγ′ defect after capturing a hole and the concentration required is consistent with very high-quality oxide. This explains the consistent low β values for thick oxides universally reported in the literature.

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Tanimoto, Satoshi. "Impact of Dislocations on Gate Oxide in SiC MOS Devices and High Reliability ONO Dielectrics". Materials Science Forum 527-529 (październik 2006): 955–60. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.955.

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In this work, it was clarified that many dislocations present on the substrate surface markedly deteriorated the TDDB property of thermal gate oxide on commercially purchased 4H-SiC epitaxial substrates. However, it was also experimentally shown that even after removing all of the dislocations, there was still a significant difference in the charge-to-breakdown (QBD) value between thermal oxides on SiC and on Si. It was suggested that this difference might partly originate from the intrinsic physics. The ONO gate dielectric was shown to be a promising alternative to thermal oxide. Experimental results indicate that the ONO dielectric on 4H-SiC could achieve a higher QBD value than thermal oxide on Si. A value of QBD = 408 C/cm2 was achieved for an ONO gate dielectric, with a SiO2 equivalent thickness of 40 nm, on regular 4H-SiC.

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Yamada, Keiichi, Junji Senzaki, Kazutoshi Kojima i Hajime Okumura. "A Novel Approach to Analysis of F-N Tunneling Characteristics in MOS Capacitor Having Oxide Thickness Fluctuation". Materials Science Forum 858 (maj 2016): 433–36. http://dx.doi.org/10.4028/www.scientific.net/msf.858.433.

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The new indicators, effective gate oxide thickness tc and effective gate electrode area D, and their combination are applied for a new analysis method of Fowler-Nordheim (F-N) tunneling characteristics in MOS capacitor having oxide thickness fluctuation. This method considering the conduction properties of F-N tunneling characteristics correlates its characteristics to the oxide reliability. These indicators quantified with the influence of the oxide thickness fluctuation can provide the net values of the electric field and the current density on the gate oxide. This new analysis method will lead to reducing the evaluation time for the reliability assessment.

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Suzuki, Takuma, Junji Senzaki, Tetsuo Hatakeyama, Kenji Fukuda, Takashi Shinohe i Kazuo Arai. "Reliability of 4H-SiC(000-1) MOS Gate Oxide Using N₂O Nitridation". Materials Science Forum 615-617 (marzec 2009): 557–60. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.557.

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The oxide reliability of metal-oxide-semiconductor (MOS) capacitors on 4H-SiC(000-1) carbon face was investigated. The gate oxide was fabricated by using N2O nitridation. The effective conduction band offset (Ec) of MOS structure fabricated by N2O nitridation was increased to 2.2 eV compared with Ec = 1.7 eV for pyrogenic oxidation sample of. Furthermore, significant improvements in the oxide reliability were observed by time-dependent dielectric breakdown (TDDB) measurement. It is suggested that the N2O nitridation as a method of gate oxide fabrication satisfies oxide reliability on 4H-SiC(000-1) carbon face MOSFETs.

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Suzuki, Takuma, Hirotaka Yamaguchi, Tetsuo Hatakeyama, Hirofumi Matsuhata, Junji Senzaki, Kenji Fukuda, Takashi Shinohe i Hajime Okumura. "Effects of Surface Morphological Defects and Crystallographic Defects on Reliability of Thermal Oxides on C-Face". Materials Science Forum 717-720 (maj 2012): 789–92. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.789.

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The causes of extrinsic failures in time-dependent dielectric breakdown characteristics of gate oxide on C-face of 4H-SiC are examined by comparing breakdown points of tested gate oxides with the images of X-ray topography and those of differential interference contrast microscopy. We have concluded as follows: (1) surface morphological defects that originate from threading screw dislocations degrade reliability of gate oxides. (2) These surface defects are not necessarily found on every wafer. (3) Crystallographic defects are not killer defects of MOSFET per se.

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Yugami, Jiro. "Oxide reliability improvement controlling microstructures of substrate/oxide and oxide/gate interfaces". Superlattices and Microstructures 27, nr 5-6 (maj 2000): 395–404. http://dx.doi.org/10.1006/spmi.2000.0878.

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Ahn, J., W. Ting i D. L. Kwong. "Comparison of performance and reliability between MOSFETs with LPCVD gate oxide and thermal gate oxide". IEEE Transactions on Electron Devices 38, nr 12 (1991): 2709–10. http://dx.doi.org/10.1109/16.158737.

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Gabriel, Calvin T., i Subhash R. Nariani. "Correlation of antenna charging and gate oxide reliability". Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 14, nr 3 (maj 1996): 990–94. http://dx.doi.org/10.1116/1.580068.

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Wu, J., i E. Rosenbaum. "Gate Oxide Reliability Under ESD-Like Pulse Stress". IEEE Transactions on Electron Devices 51, nr 7 (lipiec 2004): 1192–96. http://dx.doi.org/10.1109/ted.2004.829894.

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Wu, J., i E. Rosenbaum. "Gate Oxide Reliability Under ESD-Like Pulse Stress". IEEE Transactions on Electron Devices 51, nr 9 (wrzesień 2004): 1528–32. http://dx.doi.org/10.1109/ted.2004.834683.

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Vollertsen, R. P., i W. W. Abadeer. "Comprehensive gate-oxide reliability evaluation for dram processes". Microelectronics Reliability 36, nr 11-12 (listopad 1996): 1631–38. http://dx.doi.org/10.1016/0026-2714(96)00162-x.

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Gonzalez, Jose Ortiz, Olayiwola Alatise i Philip A. Mawby. "Novel Method for Evaluation of Negative Bias Temperature Instability of SiC MOSFETs". Materials Science Forum 963 (lipiec 2019): 749–52. http://dx.doi.org/10.4028/www.scientific.net/msf.963.749.

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The material properties of SiC make SiC power devices a superior alternative to the conventional Si power devices. However, the reliability of the gate oxide has been a major concern, limiting the adoption of SiC power MOSFETs as the power semiconductor of choice in applications which demand a high reliability. The threshold voltage (VTH) shift caused by Bias Temperature Instability (BTI) has focused the attention of different researchers, with multiple publications on this topic. This paper presents a novel method for evaluating the threshold voltage shift due to negative gate bias and its recovery when the gate bias stress is removed. This method could enable gate oxide reliability assessment techniques and contribute to new qualification methods.

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36

Yeo, Yee-Chia, Qiang Lu i Chenming Hu. "MOSFET Gate Oxide Reliability: Anode Hole Injection Model and its Applications". International Journal of High Speed Electronics and Systems 11, nr 03 (wrzesień 2001): 849–86. http://dx.doi.org/10.1142/s0129156401001015.

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We review the development of the anode hole injection (AHI) model for reliability projection of the silicon dioxide gate dielectric. The experimental and theoretical foundation of the AHI model is presented. Recent development and implications for the reliability of ultra-thin oxides are discussed. AHI is used to illuminate the questions of E versus 1/E models and field-driven versus voltage-driven models. Building on the concept of effective thinning, the AHI model is applied for the interpretation of defect-induced breakdown data and for optimizing oxide screening conditions. Circuit level reliability projection as a function of operating time, temperature, and power supply voltage is also illustrated.

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37

Takeda, Mikako, Takeshi Ohwaki, Hideo Fujii, Eisuke Kusumoto, Yoshiyuki Kaihara, Yoshizo Takai i Ryuichi Shimizu. "Influence of Native Oxides on the Reliability of Ultrathin Gate Oxide". Japanese Journal of Applied Physics 37, Part 1, No. 2 (15.02.1998): 397–401. http://dx.doi.org/10.1143/jjap.37.397.

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Grella, K., S. Dreiner, H. Vogt i U. Paschen. "High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (1.01.2013): 000116–21. http://dx.doi.org/10.4071/hiten-ta13.

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Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

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Grella, K., S. Dreiner, H. Vogt i U. Paschen. "Reliability Investigations up to 350°C of Gate Oxide Capacitors Realized in a Silicon-on-Insulator CMOS Technology". Journal of Microelectronics and Electronic Packaging 10, nr 4 (1.10.2013): 150–54. http://dx.doi.org/10.4071/imaps.391.

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It is difficult to use standard bulk-CMOS-technology at temperatures higher than 175°C due to high pn-leakage currents. Silicon-on-insulator-technologies (SOI), on the other hand, are usable up to 250°C and even higher, because leakage currents can be reduced by two to three orders of magnitude. Nevertheless, performance and reliability of SOI devices are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350°C. The experiments were carried out on gate oxide capacitor structures realized in the Fraunhofer 1.0 μm SOI-CMOS process. The gate oxide thickness is 40 nm. Using the data of the TDDB measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350°C was evaluated. For a more detailed investigation, the evolution of the current in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250°C, and make it possible to quickly evaluate the reliability of high temperature CMOS technologies at operation temperature.

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40

Kamgar, A., H. M. Vaidya, F. H. Baumann i S. Nakahara. "Impact of gate-poly grain structure on the gate-oxide reliability [CMOS]". IEEE Electron Device Letters 23, nr 1 (styczeń 2002): 22–24. http://dx.doi.org/10.1109/55.974800.

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Ma, T. P. "Metal–oxide–semiconductor gate oxide reliability and the role of fluorine". Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 10, nr 4 (lipiec 1992): 705–12. http://dx.doi.org/10.1116/1.577714.

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Matocha, Kevin, Peter A. Losee, Arun Gowda, Eladio Delgado, Greg Dunne, Richard Beaupre i Ljubisa Stevanovic. "Performance and Reliability of SiC MOSFETs for High-Current Power Modules". Materials Science Forum 645-648 (kwiecień 2010): 1123–26. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1123.

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We address the two critical challenges that currently limit the applicability of SiC MOSFETs in commercial power conversion systems: high-temperature gate oxide reliability and high total current rating. We demonstrate SiC MOSFETs with predicted gate oxide reliability of >106 hours (100 years) operating at a gate oxide electric field of 4 MV/cm at 250°C. To scale to high total currents, we develop the Power Overlay planar packaging technique to demonstrate SiC MOSFET power modules with total on-resistance as low as 7.5 m. We scale single die SiC MOSFETs to high currents, demonstrating a large area SiC MOSFET (4.5mm x 4.5 mm) with a total on-resistance of 30 m, specific on-resistance of 5 m-cm2 and blocking voltage of 1400V.

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43

Hatakeyama, Tetsuo, Hiroshi Kono, Takuma Suzuki, Junji Senzaki, Kenji Fukuda, Takashi Shinohe i Kazuo Arai. "Reliability of Large-Area Gate Oxide on the C-Face of 4H-SiC". Materials Science Forum 615-617 (marzec 2009): 553–56. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.553.

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This paper discusses the issues regarding reliability of large-area (up to 9mm2) gate oxide on the C-face of 4H-SiC. We first show that the initial failure in TDDB characteristics of large area gate oxide is strongly correlated with the surface-defect density. Using wafers with low surface-defect density wafers, scaling analysis of the area-dependence of TDDB characteristics has been performed. It has shown that the reliability of a large area gate oxide is dominated by initial and random failures. Further, we have shown that, by optimizing the temperatures of post-oxidation anneal in hydrogen atmosphere, the random failures of TDDB characteristics are substantially reduced.

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44

Lichtenwalner, Daniel J., Shadi Sabri, Edward van Brunt, Brett Hull, Satyaki Ganguly, Donald A. Gajewski, Scott Allen i John W. Palmour. "Gate Oxide Reliability of SiC MOSFETs and Capacitors Fabricated on 150mm Wafers". Materials Science Forum 963 (lipiec 2019): 745–48. http://dx.doi.org/10.4028/www.scientific.net/msf.963.745.

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Gate oxide reliability on silicon carbide MOSFETs and large-area SiC N-type capacitors was studied for devices fabricated on 150mm SiC substrates. Oxide lifetime was measured under accelerated stress conditions using constant-voltage time-dependent dielectric breakdown (TDDB) testing, or ramped-voltage breakdown (RBD) testing. TDDB results from 1200V Gen3 MOSFETs reveal a field acceleration parameter of about 35 nm/V, similar to values reported for SiO2 on silicon. Temperature-dependent RBD tests of large capacitors from 25°C to 200°C reveal an apparent activation energy of 0.24eV, indicating that oxide lifetime increases as the temperature is decreased, as expected. Using this acceleration parameter and activation energy in the linear field model, the gate oxide lifetime from MOSFET TDDB testing extrapolates to greater than 108 hours at a gate voltage of 15 VGS at 175°C.

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45

Djoric-Veljkovic, Snezana, Ivica Manic, Vojkan Davidovic, Danijel Dankovic, Snezana Golubovic i Ninoslav Stojadinovic. "Annealing of radiation-induced defects in burn-in stressed power VDMOSFETs". Nuclear Technology and Radiation Protection 26, nr 1 (2011): 18–24. http://dx.doi.org/10.2298/ntrp1101018d.

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The annealing of radiation-induced defects in burn-in stressed n-channel power VDMOSFETs with thick gate oxides (100 and 120 nm) is analysed. In comparison with the previous spontaneous recovery, the changes of device electrical parameters observed during annealing are highlighted by the elevated temperature and voltage applied to the gate, and are more pronounced in devices with a 120 nm thick gate oxide. The threshold voltage of VDMOSFETs with a 100 nm thick gate oxide during annealing has an initially slow growth, but then increases rapidly and reaches the value higher than the pre-irradiation one (rebound effect). In the case of devices with a 120 nm thick gate oxide, the threshold voltage behaviour also consists of a slight initial increase followed by a rapid, but dilatory increase, with an obvious tendency to achieve the rebound. The changes of channel carrier mobility during annealing are similar in all samples: at first, it slowly and then rapidly declines, and after reaching the minimum it begins to increase. In the case of VDMOSFETs with a thicker gate oxide, these changes are much slower. The underlying changes in the densities of gate oxide-trapped charge and interface traps are also delayed in devices with a thicker gate oxide. All these phenomena occur with certain delay in burn-in stressed devices compared to unstressed ones. The leading role in the mechanisms responsible for the observed phenomena is attributed to hydrogen related species.

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46

Rajput, Renu, i Rakesh Vaid. "Flash memory devices with metal floating gate/metal nanocrystals as the charge storage layer: A status review". Facta universitatis - series: Electronics and Energetics 33, nr 2 (2020): 155–67. http://dx.doi.org/10.2298/fuee2002155r.

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Traditional flash memory devices consist of Polysilicon Control Gate (CG) - Oxide-Nitride-Oxide (ONO - Interpoly Dielectric) - Polysilicon Floating Gate (FG) - Silicon Oxide (Tunnel dielectric) - Substrate. The dielectrics have to be scaled down considerably in order to meet the escalating demand for lower write/erase voltages and higher density of cells. But as the floating gate dimensions are scaled down the charge stored in the floating gate leak out more easily via thin tunneling oxide below the floating gate which causes serious reliability issues and the whole amount of stored charge carrying information can be lost. The possible route to eliminate this problem is to use high-k based interpoly dielectric and to replace the polysilicon floating gate with a metal floating gate. At larger physical thickness, these materials have similar capacitance value hence avoiding tunneling effect. Discrete nanocrystal memory has also been proposed to solve this problem. Due to its high operation speed, excellent scalability and higher reliability it has been shown as a promising candidate for future non-volatile memory applications. This review paper focuses on the recent efforts and research activities related to the fabrication and characterization of non-volatile memory device with metal floating gate/metal nanocrystals as the charge storage layer.

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Kagawa, Yasuhiro, Nobuo Fujiwara, Katsutoshi Sugawara, Rina Tanaka, Yutaka Fukui, Yasuki Yamamoto, Naruhisa Miura, Masayuki Imaizumi, Shuhei Nakata i Satoshi Yamakawa. "4H-SiC Trench MOSFET with Bottom Oxide Protection". Materials Science Forum 778-780 (luty 2014): 919–22. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.919.

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Ensuring gate oxide reliability and low switching loss is required for a trench gate SiC-MOSFET. We developed a trench gate SiC-MOSFET with a p-type region, named Bottom P-Well (BPW), formed at the bottom of the trench gate for bottom oxide protection. We can see an effective reduction in the maximum bottom oxide electric field (Eox) and a significant improvement in dynamic characteristics with a grounded BPW, whose dV/dt is 76 % larger than that with a floating BPW due to reduction in gate-drain capacitance (Cgd). The grounded BPW is found to be an effective means of both suppressing Eox and reducing switching loss.

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Fujihira, Keiko, Shohei Yoshida, Naruhisa Miura, Yukiyasu Nakao, Masayuki Imaizumi, Tetsuya Takami i Tatsuo Oomori. "TDDB Measurement of Gate SiO₂ on 4H-SiC Formed by Chemical Vapor Deposition". Materials Science Forum 600-603 (wrzesień 2008): 799–802. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.799.

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The reliability of CVD gate oxide was investigated by CCS-TDDB measurement and compared with thermally grown gate oxide. Although the QBD of thermal oxide becomes smaller for the larger oxide area, the QBD of CVD oxide is almost independent of the investigated gate oxide area. The QBD at F = 50% of CVD oxide, 3 C/cm2, is two orders of magnitude larger for the area of 1.96×10-3 cm2 at 1 mA/cm2 compared to that of thermal oxide. More than 80% of the CVD oxide breakdown occurs at the field oxide edge and more than 70% of the thermal oxide breakdown in the inner gate area. These results suggest that the lifetime of CVD oxide is hardly influenced by the quality of SiC, while the defects and/or impurities in SiC affect the lifetime of thermally grown oxide.

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49

Hatakeyama, Tetsuo, Takuma Suzuki, Kyoichi Ichinoseki, Hirofumi Matsuhata, Kenji Fukuda, Takashi Shinohe i Kazuo Arai. "Impact of Oxidation Conditions and Surface Defects on the Reliability of Large-Area Gate Oxide on the C-Face of 4H-SiC". Materials Science Forum 645-648 (kwiecień 2010): 799–804. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.799.

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This paper discusses the issues regarding reliability of large-area (up to 25mm2) gate oxide on the C-face of 4H-SiC. We have shown that the TDDB characteristics of large-area gate oxide improved by separating gate oxidation processes into oxide growth by dry-oxidation and successive interface control by anneal in N2O ambient or that by wet-oxidation followed by anneal in H2 ambient. In particular, dry-oxidation followed by anneal in N2O ambient for interface treatment (dry+N2O process) is effective for the suppression of the random failure in TDDB characteristics. The estimated lifetime of gate oxide of less than 9mm2 by the dry+N2O process is six-digits larger than 30 years. In the case of the TDDB characteristics of 25mm2 gate oxide grown by the dry+N2O process, the initial and random failure in TDDB characteristics is dominant. However, even in this case, we have confirmed that the evaluated lifetime of 25mm2 gate oxide is more than 30 years. In order to clarify the mechanism of the degradation of the TDDB characteristics of large-area gate oxide, we examined the effect of the surface defect on the TDDB characteristics by observing the surface of each broken MOS capacitor after the TDDB test. We have found following results. (1) The initial failures in TDDB characteristics are mainly due to surface defects such as “down fall”, “comet”, and “triangular defect”. (2) The footprints of random failure do not correspond to the positions of smaller surface defects such as “bump”. Finally, we have found that the quality of the epitaxial layer affects random failure rate in the TDDB characteristics of large area gate oxide; the random failure in the TDDB characteristics of 25mm2 gate oxide on epitaxial layer grown by a certain epitaxial vendor is almost suppressed. However, the cause of the difference in TDDB characteristics is not identified.

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Harada, Shinsuke, Makoto Kato, Sachiko Ito, Kenji Suzuki, Takasumi Ohyanagi, Junji Senzaki, Kenji Fukuda, Hajime Okumura i Kazuo Arai. "Impact of Carbon Cap Annealing on Gate Oxide Reliability on 4H-SiC (000-1) C-Face". Materials Science Forum 615-617 (marzec 2009): 549–52. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.549.

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Reliability of the gate oxide is influenced by the device structure and the processes. In the SiC MOSFET, the surface morphology is degraded by the high temperature activation RTA, and the degradation is remarkable on the n+ source region. This study develops the method to suppress the degradation of the reliability of the gate oxide on the carbon face. By utilizing the carbon cap for the RTA and the high density O2 plasma etching to remove the carbon cap, the reliability is drastically improved both on the un-implanted and the implanted surfaces. Especially, the degradation of the reliability is perfectly suppressed on the un-implanted surface.

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