Gotowa bibliografia na temat „Gate oxide reliability”
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Artykuły w czasopismach na temat "Gate oxide reliability"
Wan, Caiping, Yuanhao Zhang, Wenhao Lu, Niannian Ge, Tianchun Ye i Hengyu Xu. "Improving the reliability of MOS capacitor on 4H-SiC (0001) with phosphorus diffused polysilicon gate". Semiconductor Science and Technology 37, nr 5 (7.04.2022): 055008. http://dx.doi.org/10.1088/1361-6641/ac606d.
Pełny tekst źródłaMonsieur, F., E. Vincent, D. Roy, S. Bruyère, G. Pananakakis i G. Ghibaudo. "Gate oxide Reliability assessment optimization". Microelectronics Reliability 42, nr 9-11 (wrzesień 2002): 1505–8. http://dx.doi.org/10.1016/s0026-2714(02)00179-8.
Pełny tekst źródłaFronheiser, Jody, Aveek Chatterjee, Ulrike Grossner, Kevin Matocha, Vinayak Tilak i Liang Chun Yu. "Evaluation of 4H-SiC Carbon Face Gate Oxide Reliability". Materials Science Forum 679-680 (marzec 2011): 354–57. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.354.
Pełny tekst źródłaLee, Seok-Woo. "Novel Dual Gate Oxide Process with Improved Gate Oxide Integrity Reliability". Electrochemical and Solid-State Letters 3, nr 1 (1999): 56. http://dx.doi.org/10.1149/1.1390957.
Pełny tekst źródłaMoazzami, R., i C. Hu. "Projecting gate oxide reliability and optimizing reliability screens". IEEE Transactions on Electron Devices 37, nr 7 (lipiec 1990): 1643–50. http://dx.doi.org/10.1109/16.55751.
Pełny tekst źródłaWeir, B. E., M. A. Alam, P. J. Silverman, F. Baumann, D. Monroe, J. D. Bude, G. L. Timp i in. "Ultra-thin gate oxide reliability projections". Solid-State Electronics 46, nr 3 (marzec 2002): 321–28. http://dx.doi.org/10.1016/s0038-1101(01)00103-4.
Pełny tekst źródłaDeivasigamani, Ravi, Gene Sheu, Aanand, Shao Wei Lu, Syed Sarwar Imam, Chiu-Chung Lai i Shao-Ming Yang. "Study of HCI Reliability for PLDMOS". MATEC Web of Conferences 201 (2018): 02001. http://dx.doi.org/10.1051/matecconf/201820102001.
Pełny tekst źródłaSenzaki, Junji, Atsushi Shimozato, Kozutoshi Kajima, Keiko Aryoshi, Takahito Kojima, Shinsuke Harada, Yasunori Tanaka, Hiroaki Himi i Hajime Okumura. "Electrical Properties of MOS Structures on 4H-SiC (11-20) Face". Materials Science Forum 740-742 (styczeń 2013): 621–24. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.621.
Pełny tekst źródłaYamada, Keiichi, Osamu Ishiyama, Kentaro Tamura, Tamotsu Yamashita, Atsushi Shimozato, Tomohisa Kato, Junji Senzaki, Hirohumi Matsuhata i Makoto Kitabatake. "Reliability of Gate Oxides on 4H-SiC Epitaxial Surface Planarized by CMP Treatment". Materials Science Forum 778-780 (luty 2014): 545–48. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.545.
Pełny tekst źródłaLiang, Xiaowen, Jiangwei Cui, Jing Sun, Haonan Feng, Dan Zhang, Xiaojuan Pu, Xuefeng Yu i Qi Guo. "The Influence of 10 MeV Proton Irradiation on Silicon Carbide Power Metal-Oxide-Semiconductor Field-Effect Transistor". Journal of Nanoelectronics and Optoelectronics 17, nr 5 (1.05.2022): 814–19. http://dx.doi.org/10.1166/jno.2022.3255.
Pełny tekst źródłaRozprawy doktorskie na temat "Gate oxide reliability"
Owens, Gethin Lloyd. "Design of a reliability methodology : modelling the influence of temperature on gate oxide reliability". Thesis, Durham University, 2007. http://etheses.dur.ac.uk/2695/.
Pełny tekst źródłaZeng, Xu, i 曾旭. "Electrical reliability of N-Mos devices with N2O-based oxides as gate dielectrics". Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1996. http://hub.hku.hk/bib/B31235475.
Pełny tekst źródłaZeng, Xu. "Electrical reliability of N-Mos devices with N2O-based oxides as gate dielectrics /". Hong Kong : University of Hong Kong, 1996. http://sunzi.lib.hku.hk/hkuto/record.jsp?B1966980X.
Pełny tekst źródłaJayaraman, Rajsekhar. "Reliability and 1/f noise properties of MOSFETs with nitrided oxide gate dielectrics". Thesis, Massachusetts Institute of Technology, 1988. http://hdl.handle.net/1721.1/41582.
Pełny tekst źródłaYan, Liang. "Characterisation of gate oxide and high-k dielectric reliability in strained si and sige cmos transistors". Thesis, University of Newcastle Upon Tyne, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.506541.
Pełny tekst źródłaKutty, Karan. "CLASS-E CASCODE POWER AMPLIFIER ANALYSIS AND DESIGN FOR LONG TERM RELIABILITY". Master's thesis, University of Central Florida, 2010. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2703.
Pełny tekst źródłaM.S.E.E.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering MSEE
MA, JUN. "STUDY OF GATE OXIDE BREAKDOWN AND HOT ELECTRON EFFECT ON CMOS CIRCUIT PERFORMANCES". Doctoral diss., University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3547.
Pełny tekst źródłaPh.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD
Matsumoto, Takashi. "Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits". 京都大学 (Kyoto University), 2015. http://hdl.handle.net/2433/199461.
Pełny tekst źródła松本, 高士. "バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響". Kyoto University, 2015. http://hdl.handle.net/2433/199558.
Pełny tekst źródłaBoyer, Ludovic. "Analyse des propriétés de l'oxyde de grille des composants semi-conducteurs de puissance soumis à des contraintes électro-thermiques cycliques : vers la définition de marqueurs de vieillissement". Thesis, Montpellier 2, 2010. http://www.theses.fr/2010MON20028/document.
Pełny tekst źródłaPower semi-conductor devices are increasingly used as key parts of embedded power conversion systems in critical applications such as aerospace industry and ground transport. In such critical applications, these devices are submitted to harsh electrical, thermal and mechanical environments stresses which may significantly alter their reliability. An embedded power conversion system failure due to a power semi-conductor device breakdown may induce catastrophic results in terms of human safety, as well as economical dimensions. There is, indeed, a continuous demand on an increasing knowledge concerning the failure modes and the ageing mechanisms of power semi-conductor devices, as well as for development of new characterization techniques for ageing monitoring. The greatest part of the present work is focused on the monitoring of gate oxide properties evolutions of samples structures using the Capacitance-Voltage method (C-V method) -mainly employed in microelectronics- and the Thermal Step Method (TSM) -developed in Energy and Materials Group of IES-, as well as applying them to power semi-conductor devices. Coupling TSM and C-V method has allowed to approximately locate injected charges in the gate oxide of sample devices when submitted to electrical stresses comparable to the ones submitted to power semi-conductor devices
Książki na temat "Gate oxide reliability"
Reiner, Joachim C. Latent gate oxide damage induced by ultra-fast electrostatic discharge. Konstanz: Hartung-Gorre, 1995.
Znajdź pełny tekst źródłaMeeting, Materials Research Society, i Symposium C, "CMOS Gate-Stack Scaling-- Materials, Interfaces and Reliability Implications" (2009 : San Francisco, Calif.), red. CMOS gate-stack scaling-- materials, interfaces and reliability implications: Symposium held April 14-16, 2009, San Francisco, california, U.S.A. Warrendale, Pa: Materials Research Society, 2009.
Znajdź pełny tekst źródłaC, Gupta D., Brown George A. 1937- i Conference on Gate Dielectric Integrity (1999 : San Jose, Calif.), red. Gate dielectric integrity: Material, process, and tool qualification. West Conshocken, Pa: ASTM, 2000.
Znajdź pełny tekst źródłaBill, Taylor, Alexander A. Demkov, H. Rusty Harris, Jeffery W. Butterbaugh i Willy Rachmady. CMOS Gate-Stack Scaling Vol. 1155: Materials, Interfaces and Reliability Implications. University of Cambridge ESOL Examinations, 2014.
Znajdź pełny tekst źródła(Editor), Dinesh C. Gupta, i George Albert Brown (Editor), red. Gate Dielectric Integrity: Material, Process, and Tool Qualification (Astm Special Technical Publication// Stp) (Astm Special Technical Publication// Stp). ASTM International, 2000.
Znajdź pełny tekst źródłaCzęści książek na temat "Gate oxide reliability"
Ghetti, A. "Gate Oxide Reliability: Physical and Computational Models". W Springer Series in MATERIALS SCIENCE, 201–58. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-662-09432-7_6.
Pełny tekst źródłaVoors, I. J., K. Osinski, F. H. A. Vollebregt i C. A. Seams. "Gate Oxide Reliability in a Sealed Interface Local Oxidation Scheme". W ESSDERC ’89, 361–65. Berlin, Heidelberg: Springer Berlin Heidelberg, 1989. http://dx.doi.org/10.1007/978-3-642-52314-4_73.
Pełny tekst źródłaTanimoto, Satoshi. "Impact of Dislocations on Gate Oxide in SiC MOS Devices and High Reliability ONO Dielectrics". W Silicon Carbide and Related Materials 2005, 955–60. Stafa: Trans Tech Publications Ltd., 2006. http://dx.doi.org/10.4028/0-87849-425-1.955.
Pełny tekst źródłaFujihira, Keiko, Yoichiro Tarui, Ken Ichi Ohtsuka, Masayuki Imaizumi i Tetsuya Takami. "Effects of N2O Anneal on Channel Mobility of 4H-SiC MOSFET and Gate Oxide Reliability". W Materials Science Forum, 697–700. Stafa: Trans Tech Publications Ltd., 2005. http://dx.doi.org/10.4028/0-87849-963-6.697.
Pełny tekst źródłaHirose, M., W. Mizubayashi, K. Morino, M. Fukuda i S. Miyazaki. "Tunneling Transport and Reliability Evaluation in Extremely Thin Gate Oxides". W Fundamental Aspects of Ultrathin Dielectrics on Si-based Devices, 315–24. Dordrecht: Springer Netherlands, 1998. http://dx.doi.org/10.1007/978-94-011-5008-8_22.
Pełny tekst źródłaSUÑE, JORDI, DAVID JIMENEZ i ENRIQUE MIRANDA. "BREAKDOWN MODES AND BREAKDOWN STATISTICS OF ULTRATHIN SiO2 GATE OXIDES". W Oxide Reliability, 173–232. WORLD SCIENTIFIC, 2002. http://dx.doi.org/10.1142/9789812778062_0004.
Pełny tekst źródłaYeo, Yee-Chia, Qiang Lu i Chenming Hu. "MOSFET Gate Oxide Reliability: Anode Hole Injection Model and its Applications". W Oxide Reliability, 233–70. WORLD SCIENTIFIC, 2002. http://dx.doi.org/10.1142/9789812778062_0005.
Pełny tekst źródłaKong, Moufu. "New Electronic Devices for Power Converters". W Power Electronics, Radio Frequency and Microwave Engineering [Working Title]. IntechOpen, 2023. http://dx.doi.org/10.5772/intechopen.108467.
Pełny tekst źródłaChander, Sweta, i Sanjeet Kumar Sinha. "Performance Analysis of Electrical Characteristics of Hetero-junction LTFET at Different Temperatures for IoT Applications". W Nanoelectronics Devices: Design, Materials, and Applications (Part I), 105–32. BENTHAM SCIENCE PUBLISHERS, 2023. http://dx.doi.org/10.2174/9789815136623123010007.
Pełny tekst źródłaSu, H. P., S. M. Lin i H. C. Cheng. "Effects of BF2+-Implanted Polysilicon Structures on the Reliability of Gate Oxides". W Ion Implantation Technology–92, 655–58. Elsevier, 1993. http://dx.doi.org/10.1016/b978-0-444-89994-1.50140-x.
Pełny tekst źródłaStreszczenia konferencji na temat "Gate oxide reliability"
Park, S., J. Kang, B. So i D. Baek. "Gate oxide integrity by initial gate current". W 2009 IEEE International Integrated Reliability Workshop (IRW). IEEE, 2009. http://dx.doi.org/10.1109/irws.2009.5383020.
Pełny tekst źródłaMcPherson, J. W., i D. A. Baglee. "Acceleration Factors for Thin Gate Oxide Stressing". W 23rd International Reliability Physics Symposium. IEEE, 1985. http://dx.doi.org/10.1109/irps.1985.362066.
Pełny tekst źródłaArabi, M., X. Federspiel, F. Cacho, M. Rafik, S. Blonkowski, X. Garros i G. Guibaudo. "Frequency dependant gate oxide TDDB model". W 2022 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2022. http://dx.doi.org/10.1109/irps48227.2022.9764503.
Pełny tekst źródłaGang Niu, Wei-Ting Kary Chien, Guan Zhang, Jianshu Yu, Xiaodong Zhao i Xiaobo Duan. "Gate oxide reliability improvement for UMOS technology". W 2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA). IEEE, 2015. http://dx.doi.org/10.1109/ipfa.2015.7224402.
Pełny tekst źródłaHu, Chenming. "Reliability and Scaling of Thin Gate Oxide". W 1997 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 1997. http://dx.doi.org/10.7567/ssdm.1997.a-1-1.
Pełny tekst źródłaYeoh, Teong-San, Nitin R. Kamat, Remesh S. Nair i Shze-Jer Hu. "Gate Oxide Breakdown Model in MOS Transistors". W 33rd IEEE International Reliability Physics Symposium. IEEE, 1995. http://dx.doi.org/10.1109/irps.1995.363349.
Pełny tekst źródłaRamey, S., i J. Hicks. "SILC and gate oxide breakdown characterization of 22nm tri-gate technology". W 2014 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2014. http://dx.doi.org/10.1109/irps.2014.6860621.
Pełny tekst źródłaJu, X., i D. S. Ang. "Gate-Oxide Trapping Enabled Synaptic Logic Transistor". W 2020 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2020. http://dx.doi.org/10.1109/irps45951.2020.9129338.
Pełny tekst źródłaTeong-San Yeoh, N. R. Kamat, R. S. Nair i Shze-Jer Hu. "Gate oxide breakdown model in MOS transistors". W Proceedings of 1995 IEEE International Reliability Physics Symposium. IEEE, 1995. http://dx.doi.org/10.1109/relphy.1995.513668.
Pełny tekst źródłaNishida, Toshikazu, i Scott E. Thompson. "Oxide Field and Temperature Dependences of Gate Oxide Degradation by Substrate Hot Electron Injection". W 29th International Reliability Physics Symposium. IEEE, 1991. http://dx.doi.org/10.1109/irps.1991.363250.
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