Artykuły w czasopismach: „GATE LEVEL SIMULATION”

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Chatterjee, Debapriya, Andrew Deorio i Valeria Bertacco. "Gate-Level Simulation with GPU Computing". ACM Transactions on Design Automation of Electronic Systems 16, nr 3 (czerwiec 2011): 1–26. http://dx.doi.org/10.1145/1970353.1970363.

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Viamontes, George F., Igor L. Markov i John P. Hayes. "Improving Gate-Level Simulation of Quantum Circuits". Quantum Information Processing 2, nr 5 (październik 2003): 347–80. http://dx.doi.org/10.1023/b:qinp.0000022725.70000.4a.

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Ubar, Raimund, Jaan Raik, Eero Ivask i Marina Brik. "Defect-oriented mixed-level fault simulation in digital systems". Facta universitatis - series: Electronics and Energetics 15, nr 1 (2002): 123–36. http://dx.doi.org/10.2298/fuee0201123u.

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A new method for mixed level defect-oriented fault simulation of Digital Systems represented with Decision Diagrams (DD) is proposed. We suppose that a register transfer level (RTL) information along with gate-level descriptions for RTL blocks are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits on both levels. The physical defects in the system are mapped to the logic level and are simulated on the mixed gate- and RT levels. The approach proposed allows to increase the accuracy of test quality estimation, and to reduce simulation cost in comparison to traditional gate-level fault simulation methods.

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Chih-Shun Ding, Chi-Ying Tsui i M. Pedram. "Gate-level power estimation using tagged probabilistic simulation". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17, nr 11 (1998): 1099–107. http://dx.doi.org/10.1109/43.736184.

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Svensson, C. M., i R. Tjarnstrom. "Switch-level simulation and the pass transistor EXOR gate". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7, nr 9 (1988): 994–97. http://dx.doi.org/10.1109/43.7797.

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Bagrodia, Rajive, Yu-an Chen, Vikas Jha i Nicki Sonpar. "Parallel gate-level circuit simulation on shared memory architectures". ACM SIGSIM Simulation Digest 25, nr 1 (lipiec 1995): 170–74. http://dx.doi.org/10.1145/214283.214336.

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Vandris, Evstratios, i Gerald Sobelman. "Switch-level Differential Fault Simulation of MOS VLSI Circuits". VLSI Design 4, nr 3 (1.01.1996): 217–29. http://dx.doi.org/10.1155/1996/34084.

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A new switch-level fault simulation method for MOS circuits is presented that combines compiled switch-level simulation techniques and functional fault modeling of transistor faults with the new fault simulation algorithm of differential fault simulation. The fault simulator models both node stuck-at-0, stuck-at-1 faults and transistor stuck-on, stuck-open faults. Prior to simulation, the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. Every compiled circuit component is assigned a dominance attribute, which abstracts relative strength information in the circuit. Dominance is used during simulation to resolve the X-state due to fighting pull-up and pull-down transistor paths and also to deduce transistor fault detectability and fault equivalencies prior to simulation. The differential fault simulation algorithm developed for gate-level circuits is adapted for use at the switch-level. Differential fault simulation provides excellent performance with minimum memory requirements, although it incurs a higher overhead at the switch-level than at the gate-level due to the dynamic memory properties of MOS circuits.

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CORNO, FULVIO, MATTEO SONZA REORDA i GIOVANNI SQUILLERO. "EVOLUTIONARY SIMULATION-BASED VALIDATION". International Journal on Artificial Intelligence Tools 13, nr 04 (grudzień 2004): 897–916. http://dx.doi.org/10.1142/s0218213004001880.

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This paper describes evolutionary simulation-based validation, a new point in the spectrum of design validation techniques, besides pseudo-random simulation, designer-generated patterns and formal verification. The proposed approach is based on coupling an evolutionary algorithm with a hardware simulator, and it is able to fit painlessly in an existing industrial flow. Prototypical tools were used to validate gate-level designs, comparing them against both their RT-level specifications and different gate-level implementations. Experimental results show that the proposed method is effectively able to deal with realistic designs, discovering potential problems, and, although approximate in nature, it is able to provide a high degree of confidence in the results and it exhibits a natural robustness even when used starting from incomplete information.

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Higami, Yoshinobu, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi i Yuzo Takamatsu. "An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation". IPSJ Transactions on System LSI Design Methodology 2 (2009): 250–62. http://dx.doi.org/10.2197/ipsjtsldm.2.250.

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Boliolo, A., L. Benini, G. de Micheli i B. Ricco. "Gate-level power and current simulation of CMOS integrated circuits". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5, nr 4 (grudzień 1997): 473–88. http://dx.doi.org/10.1109/92.645074.

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Wood, Kenneth R. "Distributing gate-level digital timing simulation over arrays of transputers". Concurrency: Practice and Experience 3, nr 4 (sierpień 1991): 367–79. http://dx.doi.org/10.1002/cpe.4330030413.

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Cheng, Rui, Lin-Zi Yin, Zhao-Hui Jiang i Xue-Mei Xu. "Gate-Level Circuit Partitioning Algorithm Based on Clustering and an Improved Genetic Algorithm". Entropy 25, nr 4 (31.03.2023): 597. http://dx.doi.org/10.3390/e25040597.

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Gate-level circuit partitioning is an important development trend for improving the efficiency of simulation in EDA software. In this paper, a gate-level circuit partitioning algorithm, based on clustering and an improved genetic algorithm, is proposed for the gate-level simulation task. First, a clustering algorithm based on betweenness centrality is proposed to quickly identify clusters in the original circuit and achieve the circuit coarse. Next, a constraint-based genetic algorithm is proposed which provides absolute and probabilistic genetic strategies for clustered circuits and other circuits, respectively. This new genetic strategy guarantees the integrity of clusters and is effective for realizing the fine partitioning of gate-level circuits. The experimental results using 12 ISCAS ‘89 and ISCAS ‘85 benchmark circuits show that the proposed algorithm is 5% better than Metis, 80% better than KL, and 61% better than traditional genetic algorithms for finding the minimum number of connections between subsets.

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Hungse Cha, E. M. Rudnick, J. H. Patel, R. K. Iyer i G. S. Choi. "A gate-level simulation environment for alpha-particle-induced transient faults". IEEE Transactions on Computers 45, nr 11 (1996): 1248–56. http://dx.doi.org/10.1109/12.544481.

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Fahmi, M. I., M. F. Mukmin, H. F. Liew, C. L. Wai, M. A. Aazmi i S. N. M. Arshad. "Design new voltage balancing control series connected for HV-IGBT`s". International Journal of Electrical and Computer Engineering (IJECE) 11, nr 4 (1.08.2021): 2899. http://dx.doi.org/10.11591/ijece.v11i4.pp2899-2906.

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The insulated gate bipolar transistors (IGBTs) are widely used in various applications as they require low gate drive power and gate voltage. This paper proposes an active gain circuit to maintain voltage stability of series-connected IGBTs for high voltage applications. The novel gate driver circuit with closed-loops control amplifies the gate signal while restricting the IGBT emitter voltage below a predetermined level. With the proposed circuit, serial-connected IGBTs can replace high-voltage IGBTs (HV-IGBTs) for high-voltage applications through the active control of the gate signal time delay. Closed-loop controls function is to charged current to the gate to restrict the IGBT emitter voltage to a predetermined level. This paper also presents the experiment on the gate driver capability based on a series-connected IGBTs with three IGBTs and a snubber circuit. The experimental results show a voltage offset with active control with a wide variation in load and imbalance conditions. Lastly, the experimental results are validated with the simulation results, where the simulation results agree with the experimental results.

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Alamin, Mochammad Machlul, Hendrawan Armanto i Indra Maryati. "Penerapan Teknologi Augmented Reality Untuk Pembelajaran Gerbang Logika Pada Mata Pelajaran Sistem Komputer". JURNAL MEDIA INFORMATIKA BUDIDARMA 4, nr 3 (20.07.2020): 503. http://dx.doi.org/10.30865/mib.v4i3.2128.

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Logic Gate is one of the materials in the subject of Computer Systems at the level of SMK in class X. However, until now the learning media only uses textbooks, power point slides and manual simulations using blackboards. While the material about logic gates is very difficult if it is not directly simulated because it is directly related to the interaction of inputs and outputs at each logic gate. During the use of textbooks and manual simulation media students find it difficult to understand the material about this logic gate. The advantage of learning that utilizes augmented reality is an attractive display and displays 3D logic gate objects and input buttons that can be used to interact directly and the output is also in the form of 3D lamp objects, with this augmented reality technology will be very helpful and useful for simulating the gate logic is directly and easily understood by students. 3D logic gate animations are created using the 3D Blender application and the Augmented Reality process is created using the Unity and Vuforia SDK Library. This logic gate learning application has been applied to two classes, namely the control class and the experimental class. From the results of the Pre Test and Post Test that have been done, the control class has a 22.0% increase in percentage, while the experimental class has a 33.4% increase in percentage. Thus the learning application that utilizes Augmented Reality technology can be applied as a medium for learning logic gates at the vocational level of class X

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Meraji, Sina, Wei Zhang i Carl Tropper. "On the Scalability and Dynamic Load-Balancing of Optimistic Gate Level Simulation". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, nr 9 (wrzesień 2010): 1368–80. http://dx.doi.org/10.1109/tcad.2010.2049044.

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Batagin Armelin, Fábio, Lírida Alves de Barros Naviner i Roberto d’Amore. "Soft-Error Vulnerability Estimation Approach Based on the SET Susceptibility of Each Gate". Electronics 8, nr 7 (2.07.2019): 749. http://dx.doi.org/10.3390/electronics8070749.

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Soft-Error Vulnerability (SEV) is a parameter used to evaluate the robustness of a circuit to the induced Soft Errors (SEs). There are many techniques for SEV estimation, including analytical, electrical and logic simulations, and emulation-based approaches. Each of them has advantages and disadvantages regarding estimation time, resources consumption, accuracy, and restrictions over the analysed circuit. Concerning the ionising radiation effects, some analytical and electrical simulation approaches take into account how the circuit topology and the applied input patterns affect their susceptibilities to Single Event Transient (SET) at the gate level. On the other hand, logic simulation and emulation techniques usually ignore these SET susceptibilities. In this context, we propose a logic simulation-based probability-aware approach for SEV estimation that takes into account the specific SET susceptibility of each circuit gate. For a given operational scenario, we extract the input patterns applied to each gate and calculate its specific SET susceptibility. For the 38 analysed benchmark circuits, we obtained a reduction from 15.27% to 0.68% in the average SEV estimation error, when comparing the estimated value to a reference obtained at the transistor level. The results point out an improvement of the SEV estimation process by considering the specific SET susceptibilities.

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Zhao, Weiguo, Shuo Li, Honggang Fan i Liying Wang. "Fluctuation in the Water Level of the Air Hole of the Gate Shaft in the Pumped Storage Power Station". Processes 11, nr 3 (16.03.2023): 905. http://dx.doi.org/10.3390/pr11030905.

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In some pumped storage stations, water spray from the air hole occurs during load rejection. In order to avoid this phenomenon, it is necessary to study the change of the air hole water level during the transient process of the power station. A transient simulation of a pumped storage power station was carried out to study the variation in the maximum water level of the air hole and gate shaft. The transition process of a power station with or without a surge tank was analyzed, and the changes in the water level of the gate shaft and air hole were compared based on different gate shaft areas, and the influence of the gate shaft location on the changes in the water level of the gate shaft and air hole was determined. The following results were obtained: when the power station has a surge tank, the maximum water levels of the gate shaft and air hole are basically consistent; when the station has no surge tank, the maximum water level difference between the gate shaft and air hole gradually increases as the gate shaft area increases; the greater the distance between the gate shaft and inlet, the larger the maximum water level difference between the air hole and gate shaft; overflow measures for the air hole are required if the maximum water level of the air hole exceeds the design value.

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Fehr, E. Scott, Stephen A. Szygenda i Granville E. Ott. "An Integrated Hardware Array for Very High Speed Logic Simulation". VLSI Design 4, nr 2 (1.01.1996): 107–18. http://dx.doi.org/10.1155/1996/13931.

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A hardware architecture is proposed which allows direct mapping of design simulation topology onto an acceleration platform. In order to clarify architectural principles, the simulation is confined to functional verification of unit delay, binary valued gate level logic designs. Under this approach, a rank ordered design description is executed on a massively parallel processor grid which implements an efficient and direct model of the design, similar to prototyping. Architectural innovation reduces logic complexity and execution time of boolean evaluation and fanout switching circuits, while large scale parallelism is integrated at die level to reduce cost and communication delays. The results of this research form the basis for a multiple order of magnitude improvement in reported state-of-the-art cost-performance merit for hardware gate level simulation accelerators.

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Kim, Hong K., i Jack Jean. "Concurrency Preserving Partitioning Algorithm for Parallel Logic Simulation". VLSI Design 9, nr 3 (1.01.1999): 253–70. http://dx.doi.org/10.1155/1999/18373.

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A partitioning algorithm for parallel discrete event gate-level logic simulations is proposed in this paper. Unlike most other partitioning algorithms, the proposed algorithm preserves computation concurrency by assigning to processors circuit gates that can be evaluated at about the same time. As a result, the improved concurrency preserving partitioning (iCPP) algorithm can provide better load balancing throughout the period of a parallel simulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to fewer rollbacks and better performance. The algorithm consists of three phases and three conflicting goals can be separately considered so to reduce computational complexity.To evaluate the quality of partitioning algorithms in terms of preserving concurrency, a concurrency metric that requires neither sequential nor parallel simulation is proposed. A levelization technique is used in computing the metric so to determine gates which can be evaluated at about the same time. A parallel gate-level logic simulator is implemented on an INTEL Paragon and an IBM SP2 to evaluate the performance of the iCPP algorithm. The results are compared with several other partitioning algorithms to show that the iCPP algorithm does preserve concurrency pretty well and reasonable speedup may be achieved with the algorithm.

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Prasad, G. Durga, i V. Jegathesan. "FPGA Based Symmetrical Multi Level Inverter with Reduced Gate Driver Circuits". International Journal of Reconfigurable and Embedded Systems (IJRES) 6, nr 1 (28.05.2018): 53. http://dx.doi.org/10.11591/ijres.v6.i1.pp53-68.

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Multilevel converters tender advantages in terms of the output waveform quality due to the increased number of levels used in the output voltage modulation and have been widely accepted for high-power high-voltage applications. This paper introduces topology in multilevel dc link inverter (MLDCLI), which can significantly reduce the switch count and improve the performance. The preferred topology provides a dc voltage with the shape of a staircase approximating the rectified shape of a commanded sinusoidal wave, to the bridge inverter, which in turn gives the required alternating waveform. This topology requires fewer components compared to traditional Multi level Inverters (MLI).Therefore, the overall cost and complexity are significantly reduced particularly for higher output voltage levels. Finally, Matlab/Simulink and XILINX are used as a simulation and compiler architecture of control circuit embedded in FPGA. Simulation and experimental results for fifteen-level inverter are presented for validation.

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Zamri, Muhammad Harith Bin, Yoshihiro Ujihara, Masanori Nakamura, Mohammad R. K. Mofrad i Shukei Sugita. "Decoding the Effect of Hydrostatic Pressure on TRPV1 Lower-Gate Conformation by Molecular-Dynamics Simulation". International Journal of Molecular Sciences 23, nr 13 (1.07.2022): 7366. http://dx.doi.org/10.3390/ijms23137366.

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In response to hydrostatic pressure, the cation channel transient receptor potential vanilloid 1 (TRPV1) is essential in signaling pathways linked to glaucoma. When activated, TRPV1 undergoes a gating transition from a closed to an open state that allows the influx of Ca2+ ions. However, the gating mechanism of TRPV1 in response to hydrostatic pressure at the molecular level is still lacking. To understand the effect of hydrostatic pressure on the activation of TRPV1, we conducted molecular-dynamics (MD) simulations on TRPV1 under different hydrostatic pressure configurations, with and without a cell membrane. The TRPV1 membrane-embedded model is more stable than the TPRV1-only model, indicating the importance of including the cell membrane in MD simulation. Under elevated pressure at 27.6 mmHg, we observed a more dynamic and outward motion of the TRPV1 domains in the lower-gate area than in the simulation under normal pressure at 12.6 mmHg. While a complete closed-to-open-gate transition was not evident in the limited course of our MD simulations, an increase in the channel radius at the lower gate was observed at 27.6 mmHg versus that at 12.6 mmHg. These findings provide novel information regarding the effect of hydrostatic pressure on TRPV1 channels.

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RAGUL, DURAISAMY, i VENKATRAMAN THIYAGARAJAN. "A NOVEL FAULT TOLERANT ASYMMETRICAL 21-LEVEL INVERTER TOPOLOGY WITH REDUCED COMPONENTS". REVUE ROUMAINE DES SCIENCES TECHNIQUES — SÉRIE ÉLECTROTECHNIQUE ET ÉNERGÉTIQUE 68, nr 2 (3.07.2023): 200–205. http://dx.doi.org/10.59277/rrst-ee.2023.68.2.14.

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The foremost objective of this work is to propose a fault-tolerant (FT) asymmetrical 21-level inverter with minimal power semiconductor switches and voltage sources. The topology of the proposed inverter is to produce high voltage levels with low harmonic content and minimize electromagnetic interference (EMI) in the system. Meanwhile, the novelty has been proved by a detailed comparison between the suggested multilevel inverter (MLI) and recently introduced topologies using several components such as switches, capacitors, sources, gate driving circuits, total standing voltage (TSV), component count per level and cost function. Additionally, the flexible circuit connection between sources, switches, and loads provides the alternative configuration for 21-level MLI to operate as a 9-level and 7-level MLI topology, ensuring FT capability during the failure of specific sources and switches. The nearest voltage level (NVL) algorithm technique produces gate driver signals for the switches, which generate high-quality waveform compared to other pulse width modulation (PWM) techniques. A simulation model is designed to support the simulation results using MATLAB/Simulink software and hardware implementation. The results are analyzed under different combinations of linear and nonlinear loads. In both simulation and experiment, the evaluated parameter values show good performance concerning other structures, and total harmonic distortion (THD) is less than 5 % as per IEE519 standards.

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Sarhan, Sarhan Abdulsatar, i Shaker Abdulatif Jalil. "Analysis of Simulation Outputs for the Mutual Effect of Flow in Weir and Gate System". Journal of University of Babylon for Engineering Sciences 26, nr 6 (10.04.2018): 48–59. http://dx.doi.org/10.29196/jubes.v26i6.1050.

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The problem of suspended material and its deposition can be reduced by the combined system of weir and gate flow. Simulating this system aims to understand and analyse the mutual effect of them. Experimental work has been carried out to validate models of the combined system. Vertical sharp edges of gate and weir are tested by changing four times gate opening. The simulations base on RNG k- ε turbulence model and a comparison between flow surface profile and discharge has been done and they showed acceptable reliability. The investigation indicats that two flow portions separate at different levels depending on upstream depth and this separation level falls to reach halve of the distance between system edges as the depth increases. The relative weir to gate discharge increases from 0.4 up to 1.8 as gate opening decreases 60%. As total depth of flow upstream (H) increases by 46%, the discharge of gate increase 5%, 7%, 12%, 26% for gate opening of 2, 3, 4, 5 cm respectively, while the weir dischage increase about 5 times. The Weir in combined system performs better by 5% to 20% as compared with the conventional one. Within the study limitations, two mathematical models are suggested to predict discharge of weir in a system and for the gate with acceptable coefficient of determination.

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Aamali, Kaoutar, Abdelhakim Alali, Mohamed Sadik i Zineb El Hariti. "A Review of the Different Levels of Abstraction for Systems-on-Chip (SoC)". E3S Web of Conferences 229 (2021): 01025. http://dx.doi.org/10.1051/e3sconf/202122901025.

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Simulating systems on a chip (SoC) even before starting its productivity makes it possible to validate the correct functioning of the systems, also avoiding the manufacture of defective chips. However, low-level design and system complexity makes verification and simulation more complicated and time consuming. The classification of the different levels of abstraction from lowest to highest generally depends on the estimation accuracy of the system performance and the speed of simulation. The RTL (Register Transfer Level) abstraction level allows efficient description at gate level with good precision. Therefore, RTL program are slowly simulated. Simulation speed usually depends on the size of the platform used, which is not the case for transaction level modeling (TLM) to achieve simulation speed based on the exchange of transactions between system modules. This work aims to give a detailed description of the different levels of abstraction with the main advantages, and disadvantages on the performances estimation side such as, energy consumption, precision, and speed. Furthermore, an overview of the most adequate memory architectures and interconnection networks, to aim the most suitable virtual platforms of simulation for SoC.

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Fang, Tianyu, Yu Gu, Xiangli He, Xiaodong Liu, Yu Han i Jian Chen. "Numerical Simulation of Gate Control for Unsteady Irrigation Flow to Improve Water Use Efficiency in Farming". Water 10, nr 9 (5.09.2018): 1196. http://dx.doi.org/10.3390/w10091196.

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In the case of irrigation, to implement the water distribution plan, the flow needs to be changed through the gate which leads to the occurrence of unavoidable unsteady flow. In order to improve the level of irrigation management, it is necessary to understand the changes taking place in the canal water flow during the process of water distribution. The de Saint-Venant equations were solved based on the method of characteristics and a model was built to simulate the unsteady flow in the channel of the Yintang irrigation district. Then, the obtained results were validated by the employed model. On the basis of simulation results, a model for the variations in the gate opening was established based on the theory of under-gate discharge. In this study, the simulation results, as established from the model, are very consistent with the simulation results of existing commercial software and a simple design for the operation was conducted from the adjustment of gate openings and multi-stage gate operation modes. Overall, the established gate control model built in this study is reliable, which provides a basis for the decision-making process for the relevant staff.

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Muroi, Hiromichi, Kensuke Mine i Yoshiki Eguchi. "Scenario Analysis of Sluice Gate Operations for Evaluating Inland Flood Damage". Journal of Disaster Research 16, nr 3 (1.04.2021): 429–36. http://dx.doi.org/10.20965/jdr.2021.p0429.

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Typhoon Hagibis, which hit Japan directly on October 12, 2019, caused great damage, including the flooding of rivers, across various parts of Japan. The Tama River, which flows north of Kawasaki City, also experienced flooding which exceeded the designed high water level; although it did not cause fluvial flooding, river water flowed into the urban areas through the sewerage system, causing unprecedented inundation damage. This damage was reproduced with the inland flood simulation model. Furthermore, we performed simulations in which the water level, precipitation, and sluice gate operation of the Tama River differed from actual conditions, and compared them with the actual damage. Based on these results, we examined methods for reducing inundation damage, such as improving the operation method of sluice gates, and confirmed their effects.

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Zhang, Meng, Baikui Li i Jin Wei. "Exploring SiC Planar IGBTs towards Enhanced Conductivity Modulation Comparable to SiC Trench IGBTs". Crystals 10, nr 5 (23.05.2020): 417. http://dx.doi.org/10.3390/cryst10050417.

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The state-of-the-art silicon insulated-gate bipolar transistor (IGBT) features a trench gate, since it enhances the conductivity modulation. The SiC trench IGBT, however, faces the critical challenge of a high electric field in the gate oxide, which is a crucial threat to the device’s reliability. In this work, we explore the possibility of using a SiC planar IGBT structure to approach high performance to the level of a SiC trench IGBT, without suffering the high gate oxide field. The proposed SiC planar IGBT features buried p-layers directly under the p-bodies, and thus can be formed using the same mask set. The region between the buried p-layer and the p-body is heavily doped with n-type dopants so that the conductivity modulation is improved. Comprehensive TCAD simulations have been carried out to verify this concept, and the simulation results show the new SiC planar IGBT exhibits a high performance comparable to the trench IGBT, and also exhibits a low gate oxide field.

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Qiu, Chun, i Cheng Lan Liu. "3D Dynamic Numerical Simulation of Water Flow in Stilling Basin with Flaring Gate Pier". Applied Mechanics and Materials 580-583 (lipiec 2014): 1971–74. http://dx.doi.org/10.4028/www.scientific.net/amm.580-583.1971.

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3D numerical simulation is carried out for the water flow in stilling basin with X shaped flaring gate pier when the radial gate uses four different opening velocities. The space-time change law of hydraulic characteristics is obtained. The water level in the stilling basin is relatively higher while using lower opening velocities during the processes. The negative pressure exists on weir surface while the relative opening degree is less than 0.55; the maximal pressure on the slab of ogee section and stilling basin increases and moves to downstream with the gate opening. The results can provide important basis for shape optimization of practical engineering.

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Bertrand-Krajewski, J. L., J. P. Bardin, C. Gibello i D. Laplace. "Hydraulics of a sewer flushing gate". Water Science and Technology 47, nr 4 (1.02.2003): 129–36. http://dx.doi.org/10.2166/wst.2003.0237.

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This paper presents field experiments carried out in a 1.8 m height egg-shaped sewer in Lyon, France in order to contribute to the knowledge and the simulation of Hydrass flushing gates. The main results are: i) definition of an empirical relationship giving the flow discharged by the gate as a function of the upstream water level and its use in modelling the gate behaviour, and ii)observation of the flush propagation along the sewer and evaluation of the potential cleansing efficiency.

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Li, Ran, Jie Zhang i Jianbo Xiao. "Operation State Evaluation of Miter Gate Based on On-Line Monitoring and Finite Element Analysis". Applied Sciences 13, nr 1 (28.12.2022): 381. http://dx.doi.org/10.3390/app13010381.

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As an essential part of the water conservancy hub, the miter gate undertakes the vital task of navigational operation and works in a complex basin with a high water level drop for a long time; therefore, it is necessary to ensure its safe operation. In this paper, taking the Gezhouba No. 2 ship lock miter gate as an example, the actual gate stress and crack signals are obtained using the online monitoring system. The stress distributions of the gate under different working conditions are studied using finite element simulation analysis. Combining simulation analysis with the collected signal analysis, the operation status of the actual gate under each working condition is evaluated. The results show that the stress analysis of the online monitoring is consistent with the finite element analysis results, which verifies the reasonableness of the sensor arrangement. The stress is more concentrated in the area of the gate shaft column, the middle door seam, and the rear flange plate during the operation of the miter gate, and the maximum stress appears on the central sector shaft column of the gate. The cracks of the miter gate mainly appeared in the lower layer of the gate body, and the cracks expand gradually during the long-term operation of the gate. The crack expansion speed corresponds to the miter gate’s stress magnitude.

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Ashenden, Peter J., Henry Detmold i Wayne S. McKeen. "Execution of VHDL Models Using Parallel Discrete Event Simulation Algorithms". VLSI Design 2, nr 1 (1.01.1994): 1–16. http://dx.doi.org/10.1155/1994/86178.

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In this paper, we discuss the use of parallel discrete event simulation (PDES) algorithms for execution of hardware models written in VHDL. We survey central event queue, conservative distributed and optimistic distributed PDES algorithms, and discuss aspects of the semantics of VHDL and VHDL-92 that affect the use of these algorithms in a VHDL simulator. Next, we describe an experiment performed as part of the Vsim Project at the University of Adelaide, in which a simulation kernel using the central event queue algorithm was developed. We present measurements taken from this kernel simulating some benchmark models. It appears that this technique, which is relatively simple to implement, is suitable for use on small scale multiprocessors (such as current desktop multiprocessor workstations), simulating behavioral and register transfer level models. However, the degree of useful parallelism achievable on gate level models with this technique appears to be limited.

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33

Jmai, Bassem, Vitor Silva i Paulo M. Mendes. "2D Electronics Based on Graphene Field Effect Transistors: Tutorial for Modelling and Simulation". Micromachines 12, nr 8 (18.08.2021): 979. http://dx.doi.org/10.3390/mi12080979.

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This paper provides modeling and simulation insights into field-effect transistors based on graphene (GFET), focusing on the devices’ architecture with regards to the position of the gate (top-gated graphene transistors, back-gated graphene transistors, and top-/back-gated graphene transistors), substrate (silicon, silicon carbide, and quartz/glass), and the graphene growth (CVD, CVD on SiC, and mechanical exfoliation). These aspects are explored and discussed in order to facilitate the selection of the appropriate topology for system-level design, based on the most common topologies. Since most of the GFET models reported in the literature are complex and hard to understand, a model of a GFET was implemented and made available in MATLAB, Verilog in Cadence, and VHDL-AMS in Simplorer—useful tools for circuit designers with different backgrounds. A tutorial is presented, enabling the researchers to easily implement the model to predict the performance of their devices. In short, this paper aims to provide the initial knowledge and tools for researchers willing to use GFETs in their designs at the system level, who are looking to implement an initial setup that allows the inclusion of the performance of GFETs.

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Vanijjirattikhan, Rangsarit, Chinoros Thongthamchart, Patsorn Rakcheep, Unpong Supakchukul i Jittiwut Suwatthikul. "Reservoir Flood Routing Simulation for Dam Safety Management in Thailand". Journal of Disaster Research 16, nr 4 (1.06.2021): 596–606. http://dx.doi.org/10.20965/jdr.2021.p0596.

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A reservoir flood routing simulation software with spillway operation rules that are readable and configurable by the spillway operator is developed in this study. The software is part of the Dam Safety Remote Monitoring System used by the Electricity Generating Authority of Thailand. The flood routing simulation is implemented using a storage-indication routing method, which is a hydrologic method. The spillway operation rules are exhibited in a tree-based structure, in which the spillway gate opening is derived from the current reservoir water level (RWL), spillway gate opening, and flood situation if the peak inflow has passed. The simulation results show that the simulated RWL is similar to the RWL data in the dam construction manual. This verifies the accuracy of the reservoir flood routing simulation, which is useful for planning the spillway operation.

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35

Chen, Haotian, Hongjun Lv, Zhang Zhang, Xin Cheng i Guangjun Xie. "Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata". Journal of Circuits, Systems and Computers 28, nr 08 (lipiec 2019): 1950141. http://dx.doi.org/10.1142/s021812661950141x.

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Recently reported quantum-dot cellular automata (QCA) exclusive-OR gate designs are usually made with the AND–OR–INVERTER method in which it is difficult to optimize the XOR gate. This paper presents a novel low-power exclusive-OR (XOR) gate which is mainly based on cell-level format. Compared with the previous XOR gates, the proposed XOR gate performs in a different manner. This XOR gate design is accomplished by the intercellular effects method. For better performance comparison with previous relevant works, 4-, 8-, 16- and 32-bit parity generators are implemented in this paper. The simulation results show that there is a reduction of 32.5% cell count and 21.5% area in comparison with the existing advanced 32-bit parity generator. Especially in the aspect of clock cycle, the proposed design reduces the delay by 50% compared to the previous design. For simulation analysis, QCADesigner tool is used to verify the correctness of the proposed design. QCApro tool is used to evaluate the power dissipation of this design.

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36

Chen, Jie Ren, i Shi Feng Xu. "The Numerical Simulation of Hydrodynamics in the Sancha River Mouth". Advanced Materials Research 1065-1069 (grudzień 2014): 2978–82. http://dx.doi.org/10.4028/www.scientific.net/amr.1065-1069.2978.

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The sancha river mouth is located at the intersection of qinhuai river and Yangtze river. The flow movement of sancha River mouth are affected by application of sancha river gate and Yangtze River. The flow characteristics of the river mouth is very complex. The numerical simulation is used to study the flow movement. The 2-D depth-averaged mathematical model has been established. The govering equations and numerical simulation of flow movement are given in the boundary-fitting orthogonal coordinate systems. The model verification has done by the field data. The flow movement are computed for different application mode of sancha river gate and Yangtze river level. The mainstream line variation and local inverse flow are analyzed for the sancha river mouth.

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37

Chen, Shi Gui, i Xi Zhang. "Optimized Simulation of Automatic Gate System of Beijing Tianjin Intercity Line on Beijing South Railway Station". Applied Mechanics and Materials 602-605 (sierpień 2014): 1391–94. http://dx.doi.org/10.4028/www.scientific.net/amm.602-605.1391.

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Railway stations automatic gate system is an important part of railway passenger transport management system. The scientific and reasonable configuration of railway station ticketing equipment and reasonable choice seized outlets is significant on effective passenger organization, give full play to the ability of the equipment, and improve the operation and management level and service quality. Based on the field investigation, the actual utilization of automatic gate system of Beijing Tianjin intercity line on Beijing South Railway Station is calculated and analyzed. Finally, based on the analysis results and the calculated data, simulation is conducted for automatic gate system of Beijing Tianjin intercity line on Beijing South Railway Station using WITNESS and then propose optimized scheme.

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38

Su, Ching-Lung, Tse-Min Chen i Kuo-Hsuan Wu. "A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation". VLSI Design 2013 (16.05.2013): 1–10. http://dx.doi.org/10.1155/2013/529150.

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A prototype-based SoC performance estimation methodology was proposed for consumer electronics design. Traditionally, prototypes are usually used in system verification before SoC tapeout, which is without accurate SoC performance exploration and estimation. This paper attempted to carefully model the SoC prototype as a performance estimator and explore the environment of SoC performance. The prototype met the gate-level cycle-accurate requirement, which covered the effect of embedded processor, on-chip bus structure, IP design, embedded OS, GUI systems, and application programs. The prototype configuration, chip post-layout simulation result, and the measured parameters of SoC prototypes were merged to model a target SoC design. The system performance was examined according to the proposed estimation models, the profiling result of the application programs ported on prototypes, and the timing parameters from the post-layout simulation of the target SoC. The experimental result showed that the proposed method was accompanied with only an average of 2.08% of error for an MPEG-4 decoder SoC at simple profile level 2 specifications.

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39

Johannesson, Daniel, i Muhammad Nawaz. "Development of a PSpice Model for SiC MOSFET Power Modules". Materials Science Forum 858 (maj 2016): 1074–77. http://dx.doi.org/10.4028/www.scientific.net/msf.858.1074.

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In this paper, the static and dynamic characteristics of a 1200 V and 120 A silicon carbide (SiC) MOSFET power module has been measured, simulated and verified in the PSpice circuit simulation platform. Experimental measurements and PSpice simulations are performed to extract the technology dependent modeling parameters. The model is implemented in the PSpice circuit simulation platform using both standard components and analog behavior modeling (ABM) blocks. The simulation results of the model is fairly accurate and correlates well with the measured results over a wide temperature range. The developed model is used to facilitate converter design at cell level and hence predict and optimize the cell performance (i.e., energy losses) with varying circuit parameters (e.g., stray inductances, temperatures, gate resistances etc.,).

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40

Al jewari, Maher Abd Ibrahim, Auzani Jidin, Siti Azura Ahmad Tarusan i Mohammed Rasheed. "Implementation of SVM for five-level cascaded H-Bridge multilevel inverters utilizing FPGA". International Journal of Power Electronics and Drive Systems (IJPEDS) 11, nr 3 (1.09.2020): 1132. http://dx.doi.org/10.11591/ijpeds.v11.i3.pp1132-1144.

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The Space Vector Modulation SVM technique has won large acceptance for AC drive applications. However the utilization of multilevel inverters connected with SVM by Digital signal processor (DSP) raise the intricacy of control algorithm or computational load, increases of the obtaining distortions output voltage. The development of SVM in multilevel inverters may offer higher numbers of switching vectors for acquiring further enhancements of output voltage performances and implement by using Field Programmer Gate Array (FPGA), investigate lower Total Hormonic Distortion (THD). This paper reports the performance evaluation of SVM for five-level of Cascaded H-Bridge Multilevel Inverter CHMI using MATLAB/Simulink, which is sampled at the minimum sampling time, i.e. DT = 5 μs. The switching signals for driving insulated gate bipolar transistor (IGBTs) which are stored in MATLAB workspaces, are then used to be programmed in FPGA using a Quartus II software. Which can be stated the lower THD of the simulation result is about 14.48% for five-level CHMI and experiment result is about 14.31% for five-level CHMI at modulation index M_i=0.9. The error percentage between the simulation results and experimental results of the fundamental output voltage in SVM is small which is approximately less than 1 %.

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41

Shah, M. J., K. S. Pandya i P. Chauhan. "Direct ADC Controlled Asymmetric Cascaded Multilevel Inverter". Engineering, Technology & Applied Science Research 12, nr 4 (1.08.2022): 9071–77. http://dx.doi.org/10.48084/etasr.5164.

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This paper presents an asymmetric multi-level inverter with a novel direct ADC control scheme. This scheme does not use a carrier wave or a reference sinusoidal wave to generate gate pulses for power switches, but an Analog to Digital Converter (ADC) to create gate pulses. For n sources, n bit ADC will generate 2n+1-1 levels at the output voltage of the inverter. This scheme uses the ADC output for the gate pulses for power switching devices. In this topology, the inverter comprises a series of connected half-bridges to generate a more significant level. The presented topology uses binary level supply voltages. Different topologies with different parameters are compared with the proposed inverter, and the operation of the proposed control scheme is verified with a simulation in Matlab. The prototype of a 31-level inverter is developed in hardware, and the hardware results are discussed.

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42

Ivancova, Olga, Vladimir Korenkov, Olga Tyatyushkina, Sergey Ulyanov i Toshio Fukuda. "Quantum supremacy in end-to-end intelligent IT. Pt. I:Quantum software engineering–quantum gate level applied models simulators". System Analysis in Science and Education, nr 1 (2020) (2020): 52–84. http://dx.doi.org/10.37005/2071-9612-2020-1-52-84.

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Principles and methodologies of quantum algorithmic gates design for master course and PhD students in computer science, control engineering and intelligent robotics described. The possibilities of quantum algorithmic gates simulation on classical computers discussed. Applications of quantum gate of nanotechnology in intelligent quantum control introduced. Anew approach to a circuit implementation design of quantum algorithm gates for fast quantum massive parallel computing presented. The main attention focused on the development of design method of fast quantum algorithm operators as superposition, entanglement and interference, which are in general time-consuming operations due to the number of products that have performed. SW & HW support sophisticated smart toolkit of supercomputing accelerator of quantum algorithm simulation on small quantum programmable computer algorithm gate (that can program in SW to implement arbitrary quantum algorithms by executing any sequence of universal quantum logic gates) described. As example, the method for performing Grover’s interference operator without product operations introduced. The background of developed information technology is the "Quantum / Soft Computing Optimizer" (QSCOptKBTM) SW based on soft and quantum computational intelligence toolkit.

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43

Guo, Huaixin, Tangsheng Chen i Shang Shi. "Transient Simulation for the Thermal Design Optimization of Pulse Operated AlGaN/GaN HEMTs". Micromachines 11, nr 1 (9.01.2020): 76. http://dx.doi.org/10.3390/mi11010076.

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The thermal management and channel temperature evaluation of GaN power amplifiers are indispensable issues in engineering field. The transient thermal characteristics of pulse operated AlGaN/GaN high electron mobility transistors (HEMT) used in high power amplifiers are systematically investigated by using three-dimensional simulation with the finite element method. To improve the calculation accuracy, the nonlinear thermal conductivities and near-junction region of GaN chip are considered and treated appropriately in our numerical analysis. The periodic transient pulses temperature and temperature distribution are analyzed to estimate thermal response when GaN amplifiers are operating in pulsed mode with kilowatt-level power, and the relationships between channel temperatures and pulse width, gate structures, and power density of GaN device are analyzed. Results indicate that the maximal channel temperature and thermal impedance of device are considerably influenced by pulse width and power density effects, but the changes of gate fingers and gate width have no effect on channel temperature when the total gate width and active area are kept constant. Finally, the transient thermal response of GaN amplifier is measured using IR thermal photogrammetry, and the correctness and validation of the simulation model is verified. The study of transient simulation is demonstrated necessary for optimal designs of pulse-operated AlGaN/GaN HEMTs.

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44

Yang, Seiyang. "Performance Improvement of Prediction-Based Parallel Gate-Level Timing Simulation Using Prediction Accuracy Enhancement Strategy". KIPS Transactions on Computer and Communication Systems 5, nr 12 (31.12.2016): 439–46. http://dx.doi.org/10.3745/ktccs.2016.5.12.439.

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45

Jiang, Yu, Linyan Zeng i Yuxiao Luo. "Multiobjective Gate Assignment Based on Passenger Walking Distance and Fairness". Mathematical Problems in Engineering 2013 (2013): 1–7. http://dx.doi.org/10.1155/2013/361031.

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Passenger walking distance is an important index of the airport service quality. How to shorten the walking distance and balance the airlines' service quality is the focus of much research on airport gate assignment problems. According to the problems of airport passenger service quality, an optimization gate assignment model is established. The gate assignment model is based on minimizing the total walking distance of all passengers and balancing the average walking distance of passengers among different airlines. Lingo is used in the simulation of a large airport gate assignment. Test results show that the optimization model can reduce the average walking distance of passenger effectively, improve the number of flights assigned to gate, balance airline service quality, and enhance the overall service level of airports and airlines. The model provides reference for the airport gate preassignment.

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46

Champac, Victor H., i Joan Figueras. "Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects". VLSI Design 5, nr 3 (1.01.1997): 273–84. http://dx.doi.org/10.1155/1997/97381.

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The behavior of basic CMOS combinational gates in the presence of a floating gate defect is characterized in order to investigate its detectability by IDDQ . The defect is modeled at the circuit level by the poly-bulk and metal-poly capacitances, which determine the quiescent power supply current consumption (IDDQ ) of the defective circuit. The testing implications on the type of defective gate are studied. Experimental measures have been made on basic CMOS combinational modules designed with intentional floating gate defects. A good agreement is observed between the simulation results and the experimental data. A conventional ATPG for stuck-at faults is used to obtain the required exciting vector to test the floating gate defects by IDDQ Testing.

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47

Raj, Sumit, Rajib Kumar Mandal, Mala De i Ashutosh Kumar Singh. "Nine-level inverter with lesser number of power semiconductor switches using dSPACE". International Journal of Power Electronics and Drive Systems (IJPEDS) 13, nr 1 (1.03.2022): 39. http://dx.doi.org/10.11591/ijpeds.v13.i1.pp39-46.

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In this paper, a single-phase nine-level multilevel inverter (MLI) topology is created in which reduced number of switches, diodes and gate driver circuits can be used so as to obtain higher output voltage levels. Due to this configuration, the blocking voltage value across the switches will also get reduced. In this proposed single-phase MLI topology, increase in output voltage levels can be observed whenever there is increment in the number of switches in the configuration. Proper mathematical modeling and analysis of the voltage waveform of the proposed inverter have been done for a 9-level MLI. MATLAB platform is used for modeling and simulation of the MLI. Modulation index is varied in order to observe various outcomes through simulation. The proposed nine-level inverter configuration is experimentally evaluated in the laboratory for various modulation indices so as to validate the simulation results. Comparison of this topology is done with the classical MLIs in order to illustrate its advantages.

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Deng, Chengfa, i Jincheng Du. "Numerical Simulation of Hydraulic Characteristics of Spillway Tunnel with Gradually Expanding Outlet and Lower outlet height". Journal of Physics: Conference Series 2271, nr 1 (1.05.2022): 012031. http://dx.doi.org/10.1088/1742-6596/2271/1/012031.

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Abstract Using a practical and efficient overall three-dimensional turbulent numerical model of the spillway tunnel, the numerical simulation of the hydraulic characteristics of the spillway tunnel with the gradually expanding outlet and lower outlet height is carried out. The calculation results show that when the gate is fully open, there is pressure flow in the whole tunnel of the spillway tunnel, and the flow state is stable; when the gate is not fully open and the water level is low, the flow state in the tunnel is unstable, and the free and pressure flow occur alternately. When the gate is at a small opening, the flip bucket raises the water level at the outlet, and the lower outlet height causes insufficient air supply in the cave, which is prone to cavitation. The lift distance is small, and it is easy to scour the slope of the hole. The lower outlet height at the outlet of the spillway tunnel further exacerbates the complexity of the hydraulic characteristics in the back arc section, which should be paid attention to during design and construction, and it is necessary to carry out hydraulic model test research.

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Kim, Dong-Wook, i Tae-Yong Choi. "Delay Time Estimation Model for Large Digital CMOS Circuits". VLSI Design 11, nr 2 (1.01.2000): 161–73. http://dx.doi.org/10.1155/2000/18189.

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Delay time estimation in simulation or design verification step during a design cycle has become more and more important as the meaning of performance prediction. This paper proposed a delay estimation model for digital CMOS circuits, which works in gate-level but the modeling process includes the characteristics of MOSFETs. This model can handle the variation according to the kind of gates, input transition time, output load(fan-out), and transistor sizes of a gate. The procedure to find the general model was that, a delay model for CMOS inverter was extracted first, then it was extended to other gate by converting it into an equivalent inverter. The resulting model was evaluated and compared with SPICE simulation, which showed that the proposed model has the accuracy of less than 5% relative error rate to the SPICE results for each case and the speed of about 70 times faster than SPICE.

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Sihombing, Fiktor, i Nova Juwita Siburian. "Perancangan Gerbang Otomatis Menggunakan Frekuensi Berbasis Arduino". Jurnal ELPOTECS 4, nr 2 (30.09.2021): 10–21. http://dx.doi.org/10.51622/elpotecs.v4i2.430.

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Automatic Gate design using Arduino Uno controller as the main component that regulates other components. This tool is designed for a higher level of security and makes it easier for humans to open/close the gate automatically. This tool is also a simulation tool and learning media. The data analysis method used is a needs analysis which includes software, namely Arduino software and gearbox hardware, Bluetooth module, and motor driver. From the results of the tests that have been carried out, it can be concluded that this design works well when the amarino application is turned on and then orders the gate to open/close. The conclusion that is designed is to make it easier to open / close the gate and accurate security.

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