Gotowe bibliografie tematyczne / GATE LEVEL SIMULATION

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Gotowa bibliografia na temat „GATE LEVEL SIMULATION”

Autor: Grafiati
Data publikacji: 11 września 2023

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Artykuły w czasopismach na temat "GATE LEVEL SIMULATION"

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Chatterjee, Debapriya, Andrew Deorio i Valeria Bertacco. "Gate-Level Simulation with GPU Computing". ACM Transactions on Design Automation of Electronic Systems 16, nr 3 (czerwiec 2011): 1–26. http://dx.doi.org/10.1145/1970353.1970363.

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Viamontes, George F., Igor L. Markov i John P. Hayes. "Improving Gate-Level Simulation of Quantum Circuits". Quantum Information Processing 2, nr 5 (październik 2003): 347–80. http://dx.doi.org/10.1023/b:qinp.0000022725.70000.4a.

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Ubar, Raimund, Jaan Raik, Eero Ivask i Marina Brik. "Defect-oriented mixed-level fault simulation in digital systems". Facta universitatis - series: Electronics and Energetics 15, nr 1 (2002): 123–36. http://dx.doi.org/10.2298/fuee0201123u.

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A new method for mixed level defect-oriented fault simulation of Digital Systems represented with Decision Diagrams (DD) is proposed. We suppose that a register transfer level (RTL) information along with gate-level descriptions for RTL blocks are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits on both levels. The physical defects in the system are mapped to the logic level and are simulated on the mixed gate- and RT levels. The approach proposed allows to increase the accuracy of test quality estimation, and to reduce simulation cost in comparison to traditional gate-level fault simulation methods.
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Chih-Shun Ding, Chi-Ying Tsui i M. Pedram. "Gate-level power estimation using tagged probabilistic simulation". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17, nr 11 (1998): 1099–107. http://dx.doi.org/10.1109/43.736184.

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Svensson, C. M., i R. Tjarnstrom. "Switch-level simulation and the pass transistor EXOR gate". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7, nr 9 (1988): 994–97. http://dx.doi.org/10.1109/43.7797.

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Bagrodia, Rajive, Yu-an Chen, Vikas Jha i Nicki Sonpar. "Parallel gate-level circuit simulation on shared memory architectures". ACM SIGSIM Simulation Digest 25, nr 1 (lipiec 1995): 170–74. http://dx.doi.org/10.1145/214283.214336.

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Vandris, Evstratios, i Gerald Sobelman. "Switch-level Differential Fault Simulation of MOS VLSI Circuits". VLSI Design 4, nr 3 (1.01.1996): 217–29. http://dx.doi.org/10.1155/1996/34084.

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A new switch-level fault simulation method for MOS circuits is presented that combines compiled switch-level simulation techniques and functional fault modeling of transistor faults with the new fault simulation algorithm of differential fault simulation. The fault simulator models both node stuck-at-0, stuck-at-1 faults and transistor stuck-on, stuck-open faults. Prior to simulation, the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. Every compiled circuit component is assigned a dominance attribute, which abstracts relative strength information in the circuit. Dominance is used during simulation to resolve the X-state due to fighting pull-up and pull-down transistor paths and also to deduce transistor fault detectability and fault equivalencies prior to simulation. The differential fault simulation algorithm developed for gate-level circuits is adapted for use at the switch-level. Differential fault simulation provides excellent performance with minimum memory requirements, although it incurs a higher overhead at the switch-level than at the gate-level due to the dynamic memory properties of MOS circuits.
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CORNO, FULVIO, MATTEO SONZA REORDA i GIOVANNI SQUILLERO. "EVOLUTIONARY SIMULATION-BASED VALIDATION". International Journal on Artificial Intelligence Tools 13, nr 04 (grudzień 2004): 897–916. http://dx.doi.org/10.1142/s0218213004001880.

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This paper describes evolutionary simulation-based validation, a new point in the spectrum of design validation techniques, besides pseudo-random simulation, designer-generated patterns and formal verification. The proposed approach is based on coupling an evolutionary algorithm with a hardware simulator, and it is able to fit painlessly in an existing industrial flow. Prototypical tools were used to validate gate-level designs, comparing them against both their RT-level specifications and different gate-level implementations. Experimental results show that the proposed method is effectively able to deal with realistic designs, discovering potential problems, and, although approximate in nature, it is able to provide a high degree of confidence in the results and it exhibits a natural robustness even when used starting from incomplete information.
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Higami, Yoshinobu, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi i Yuzo Takamatsu. "An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation". IPSJ Transactions on System LSI Design Methodology 2 (2009): 250–62. http://dx.doi.org/10.2197/ipsjtsldm.2.250.

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Boliolo, A., L. Benini, G. de Micheli i B. Ricco. "Gate-level power and current simulation of CMOS integrated circuits". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5, nr 4 (grudzień 1997): 473–88. http://dx.doi.org/10.1109/92.645074.

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Rozprawy doktorskie na temat "GATE LEVEL SIMULATION"

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Shelly, Jacinda R. (Jacinda Rene). "Concurrent gate-level circuit simulation". Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/61576.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 42).
In the last several years, parallel computing on multicore processors has transformed from a niche discipline relegated primarily to scientific computing into a standard component of highperformance personal computers. At the same time, simulating processors prior to manufacture has become increasingly time-consuming due to the increasing number of gates on a single chip. However, writing parallel programs in a way that significantly improves performance can be a difficult task. In this thesis, I outline principles that must be considered when running good gate-level circuit simulations in parallel. I also analyze a test circuit's performance in order to quantitatively demonstrate the benefit of considering these principles in advance of running simulations.
by Jacinda R. Shelly.
M.Eng.
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Meraji, Seyed Sina. "Towards optimazation techniques for dynamic load balancing of parallel gate level simulation". Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=104767.

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As a consequence of Moore's law, the size of integrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. Consequently, parallel simulation has emerged as an approach which can be both fast and cost effective. In this thesis, we examine the performance of a parallel Verilog simulator, VXTW, on four large, real designs using an optimistic synchronization scheme named Time Warp. As previous work has made use of either relatively small benchmarks or synthetic circuits, the use of these circuits is far more realistic. Because of the low computational granularity of a gate level simulation and because the computational and communication loads vary throughout the course of the simulation, the performance of Time Warp can be severely degraded or can even be unstable. Dynamic load balancing algorithms for balancing the computational and communication loads during the simulation are described in this thesis. Like all load balancing algorithms, the proposed algorithms have some tuning parameters which must be optimized. In addition, in order to avoid the simulation from being too optimistic, we make use of a time window. In the thesis, we make use of learning techniques from artificial intelligence (N-armed Bandit, Multi-state Q-learning) and heuristic searches (Genetic Algorithm, Simulated Annealing) to tune the parameters of the dynamic load balancing algorithms and to determine the size of the time window. we evaluated the performance of these algorithms on open source Sparc and Leon processor designs and on two Viterbi decoder designs and observed up to a 70% improvement in simulation time using these approaches.
Une des conséquences de la loi de Moore est la croissance significative de lataille des circuits intégrés; il en résulte que la simulation est devenue le goulot d'étranglement majeur dans le processus de conception de tels circuits. Conséquemment, la simulation parallèle se veut une approche qui a le potentiel d'être à la fois rapide etrentable. Dans cette thèse, nous examinerons la performance d'un simulateur Verilog parallèle appelé VXTW sur quatre conceptions de processeurs réelles de grande taille, en utilisant un algorithme de synchronisation optimiste appelé Time Warp. Puisque les travaux précédents ont utilisé des circuits synthétiques ou des tests de performance de taille relativement petite, l'utilisation de ces circuits est beaucoup plus réaliste. Puisque les simulations au niveau des portes logiques impliquent une granularité calculatoire peu élevée, et puisque les charges calculatoires et de communication varient au cours de la simulation, la performance de Time Warp peut se dégrader sévèrement ou devenir instable. Dans cette thèse, nous décrivons des algorithmes dynamiques d'équilibrage de charge visant à équilibrer les charges calculatoires et de communicationdurant la simulation. Comme tous les algorithmes d'équilibrage de charge, les algorithmes proposés comportent des paramètres de réglage qui doivent être optimisés. De plus, nous utilisons une fenêtre de temps pour éviter que la simulation ne soit trop optimiste. Dans cette thèse, nous utilisons des techniques d'apprentissage provenant du domaine de l'intelligence artificielle (machine à sous à leviers multiples, Q-learning avec plusieurs agents) et des recherches heuristiques (algorithmes génétiques, méthode du circuit simulé) pour régler les paramètres des algorithmes dynamiques d'équilibrage des charges, ainsi que pour déterminer la taille de la fenêtre de temps. Nous évaluons la performance de ces algorithmes sur des conceptions de processeurs Sparc et Leon libres de droits, ainsi que sur deux décodeurs Viterbi, et nous avons pu observer une amélioration du temps de simulation de 70% en utilisant ces approches.
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Mabry, Ryan. "Gate Level Dynamic Energy Estimation In Asynchronous Circuits Using Petri Nets". Scholar Commons, 2007. http://scholarcommons.usf.edu/etd/3826.

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This thesis introduces a new methodology for energy estimation in asynchronous circuits. Unlike existing probabilistic methods, this is the first simulative work for energy estimation in all types of asynchronous circuits. The new simulative methodology is based on Petri net modeling. A real delay model is incorporated to capture both gate delays and interconnect delays. The switching activity at each gate is captured to measure the average dynamic energy consumed per request/acknowledge handshaking pair. The new type of Petri net is called Hierarchical Colored Asynchronous Hardware Petri net (HCAHPN). The HCAHPN is able to capture the temporal and spatial correlations of signals within a circuit, while preserving gate logic behavior and timing information. While Petri nets have been previously used for simulating combinational and sequential circuits, this is the first work that uses Petri nets for simulating asynchronous circuits. While different asynchronous design styles make various assumptions on the gate and wire delays present with the circuit, the physical implementations of these circuits always have gate and interconnect delays. Unlike previous methods, the proposed methodology is independent of the asynchronous design style used and it can be adapted for all types of asynchronous circuits that use handshaking communication.
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Bai, Hao. "Device-level real-time modeling and simulation of power electronics converters". Thesis, Bourgogne Franche-Comté, 2019. http://www.theses.fr/2019UBFCA014.

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Pour le développement des convertisseurs d’électronique de puissance, la simulation en temps réel joue un rôle essentiel dans la validation des performances des convertisseurs et de leur contrôle avant leur réalisation. Cela permet de simuler et reproduire avec précision les formes d’ondes des courants et tensions des convertisseurs de puissance modélisés avec un pas de temps de simulation correspondant exactement au temps physique. Les circuits d’électronique de puissance sont caractérisés par le comportement non linéaire des interrupteurs. Par conséquent, les représentations des dispositifs de commutation sont cruciales dans la simulation en temps réel. Le modèle au niveau système est largement utilisé dans les simulateurs temps réel du commerce et les plates-formes expérimentales, qui modélisent les comportements des interrupteurspar deux états stationnaires distincts - passant et bloqué - et négligent tous les phénomènes transitoires. Ces dernières années, la simulation temps réel au niveau du composant est devenue populaire car elle permet de simuler les formes d'onde de commutation transitoires et de fournir des informations utiles concernant les contraintes sur les interrupteurs , les pertes, les effets parasites et les comportements électrothermiques. Néanmoins, la simulation temps réel au niveau du composant est contrainte par le pas de temps transitoire réalisable en raison des quantités de calcul accrues introduites par la non-linéarité du modèle de commutation.Afin d'intégrer le modèle au niveau du composant dans la simulation en temps réel, cette thèse porte sur l'exploration approfondie des techniques de modélisation et de simulation en temps réel au niveau composantdes convertisseurs d’électronique de puissance. Les techniques de simulation en temps réel les plus récentes sont d’abord examinées de manière exhaustive, tant au niveau du système que du composant. En outre, deux approches de modélisation au niveau du composant sont proposées, à savoir le modèle haute résolution quasi-transitoire (HRQT) et le modèle transitoire linéaire par morceaux (PLT). Dans le modèle HRQT, le modèle de réseau est implémenté par une simulation au niveau système tout en générant les formes d'onde de commutation transitoires avec une résolution de 5 ns, ce qui permet de simuler le convertisseur de puissance avec des transitoires rapides jusqu'à des dizaines de nanosecondes. Compte tenu des effets des transitoires sur l’ensemble du réseau, les modèles non linéaires des IGBT et diodes sont linéarisés par morceaux dans le modèle PLT. À l'aide de techniques efficaces de découplage de circuits, le modèle du convertisseur de puissance au niveau composant peut être simulé de manière stable avec un pas de temps de simulation global de 50 ns. Les deux modèles proposés sont testés et validés via différents cas sur une plate-forme temps réel de National Instruments basée sur un FPGA, comprenant un convertisseur boost boosté entrelacé (FIBC) pour le modèle HRQT, un convertisseur DC-DC-AC pour le modèle PLT et un convertisseur modulaire à plusieurs niveaux (MMC) pour les deux. Des résultats précis sont produits par rapport aux outils de simulation hors ligne. L'efficacité et les valeurs d'application sont également vérifiées par les résultats d’essais en temps réel
In the development cycles of the power electronics converters, the real-time simulation plays an essential role in validating the converters’ and the controllers’ performances before their implementations on real systems. It can simulate and reproduce the current and voltage waveforms of the modeled power electronics converters accurately with a simulation time-step exactly corresponding to the physical time. The power electronics circuits are characterized by nonlinear switching behaviors. Therefore, the representations of switching devices are crucial in real-time simulation. The system-level model is widely used in both commercial real-time simulators and the experimentally built real-time platforms, which models the switching behaviors by two separate steady states – turn-on and turn-off, and neglects all the switching transients. In recent years, the device-level real-time simulation has become popular since it can simulate the transient switching waveforms and provide useful information with regard to the device stresses, the power losses, the parasitic effects, and electro-thermal behaviors. Nevertheless, the device-level real-time simulation is constrained by the achievable transient time-step due to the increased computational amounts introduced by the nonlinearity of the switch model.In order to integrate the device-level model in the real-time simulation, in this thesis, the device-level real-time modeling and simulation techniques of the power electronics converters are deeply explored. The state-of-art real-time simulation techniques are firstly reviewed comprehensively with regard to both system-level and device-level. Moreover, two device-level modeling approaches are proposed, including high- resolution quasi-transient model (HRQT) and the piecewise linear transient (PLT) model. In HRQT model, the network model can be implemented by system-level simulation while generating the transient switching waveforms with a 5 ns resolution, which is good at simulating the power converter with fast switching transients down to tens of nanoseconds. Considering the effects of the transient behaviors on the entire network, the PLT model is proposed by piecewise linearizing the nonlinear IGBT and diode equivalent models. With the help of effective circuit decoupling techniques, the device-level power converter model can be simulated stably with a 50 ns global simulation time-step. The proposed two models are tested and validated via different case studies on National Instruments (NI) FPGA-based real-time platform, including floating interleaved boost converter (FIBC) for HRQT model, DC-DC-AC converter for PLT model, and modular multi-level converter (MMC) for the both. Accurate results are produced compared to offline simulation tools. The effectiveness and the application values are further verified by the results of the real-time experiments
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Gu, Pei. "Prototyping the simulation of a gate level logic application program interface (API) on an explicit-multi-threaded (XMT) computer". College Park, Md. : University of Maryland, 2005. http://hdl.handle.net/1903/2626.

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Thesis (M.S.) -- University of Maryland, College Park, 2005.
Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Ramani, Shiva Shankar. "Graphical Probabilistic Switching Model: Inference and Characterization for Power Dissipation in VLSI Circuits". [Tampa, Fla.] : University of South Florida, 2004. http://purl.fcla.edu/fcla/etd/SFE0000497.

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Arvidsson, Klas. "Simulering av miljoner grindar med Count Algoritmen". Thesis, Linköping University, Department of Computer and Information Science, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2476.

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A key part in the development and verification of digital systems is simulation. But hardware simulators are expensive, and software simulation is not fast enough for designs with a large number of gates. As today’s digital zesigns constantly grow in size (number of gates), and that trend shows no signs to end, faster simulators handling millions of gates are needed.

We investigate how to create a software gate-level simulator able to simulate a high number of gates fast. This involves a trade-off between memory requirement and speed. A compact netlist representation can utilize cache memories more efficient but requires more work to interpret, while high memory requirements can limit the performance to the speed of main memory.

We have selected the Counting Algorithm to implement the experimental simulator MICA. The main reasons for this choice is the compact way in which gates can be stored, but still be evaluated in a simple and standard way.

The report describes the issues and solutions encountered and evaluate the resulting simulator. MICA simulates a SPARC architecture processor called Leon. Larger netlists are achieved by simulating several instances of this processor. Simulation of 128 instances is done at a speed of 9 million gates per second using only 3.5MB memory. In MICA this design correspond to 2.5 million gates.

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Rundle, Wendy L. "The low-level radwaste siting simulation game : a case study of learning about negotiation". Thesis, Massachusetts Institute of Technology, 1985. http://hdl.handle.net/1721.1/77307.

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Thesis (M.C.P.)--Massachusetts Institute of Technology, Dept. of Urban Studies and Planning, 1985.
MICROFICHE COPY AVAILABLE IN ARCHIVES AND ROTCH.
Bibliography: leaves 74-75.
by Wendy L. Rundle.
M.C.P.
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Eisen, Philipp. "Simulating Human Game Play for Level Difficulty Estimation with Convolutional Neural Networks". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-215699.

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This thesis presents an approach to predict the difficulty of levels in a game by simulating game play following a policy learned from human game play. Using state-action pairs tracked from players of the game Candy Crush Saga, we train a Convolutional Neural Network to predict an action given a game state. The trained model then acts as a policy.Our goal is to predict the success rate (SR) of players, from the SR obtained by simulating game play. Previous state-ofthe-art was using Monte Carlo tree search (MCTS) or handcrafted heuristics for game play simulation. We benchmark our suggested approach against one using MCTS. The hypothesis is that, using our suggested approach, predicting the players’ SR from the SR obtained through the simulation, leads to better estimations of the players’ SR.Our results show that we could not only significantly improve the predictions of the players’ SR, but also decrease the time for game play simulation by at least 50 times.
Den här avhandlingen presenterar ett tillvägagångssätt för att förutse svårighetsgrad av spelbanor genom spelsimulering enligt en strategi lärd från mänskligt spelande. Med användning av tillstånd-handlings par insamlade från spelare av spelet Candy Crush Saga, tränar vi ett Convolutional Neural Network att förutse en handling från ett givet tillstånd. Den tränade modellen agerar sedan som strategi. Vårt mål är att förutse success rate (SR) av spelare, från SR erhållen från spelsimulering. Tidigare state-of-the-art använde Monte Carlo tree search (MCTS) eller handgjorda heuristiker för spelsimulering. Vi jämför vårt tillvägagångssätt med MCTS. Hypotesen är att vårt föreslagna tillvägagångssätt leder till bättre förutsägelser av mänsklig SR från SR erhållen från spelsimulering. Våra resultat visar att vi inte bara signifikant kunde förbättra förutsägelserna av mänsklig SR utan också kunde minska tidsåtgången för spelsimulering med åtminstone en faktor 50.
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Chevillon, Nicolas. "Etude et modélisation compacte du transistor FinFET ultime". Phd thesis, Université de Strasbourg, 2012. http://tel.archives-ouvertes.fr/tel-00750928.

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Une des principales solutions technologiques liées à la réduction d'échelle de la technologie CMOS est aujourd'hui clairement orientée vers les transistors MOSFET faiblement dopés à multiples grilles. Ceux-ci proposent une meilleure immunité contre les effets canaux courts comparés aux transistors MOSFET bulk planaires (cf. ITRS 2011). Parmi les MOSFETs à multiples grilles, le transistor FinFET SOI est un candidat intéressant de par la similarité de son processus de fabrication avec la technologie des transistors planaires. En parallèle, il existe une réelle attente de la part des concepteurs et des fonderies à disposer de modèles compacts efficaces numériquement, précis et proches de la physique, insérés dans les " design tools " permettant alors d'étudier et d'élaborer des circuits ambitieux en technologie FinFET. Cette thèse porte sur l'élaboration d'un modèle compact orienté conception du transistor FinFET valide aux dimensions nanométriques. Ce modèle prend en compte les effets canaux courts, la modulation de longueur de canal, la dégradation de la mobilité, leseffets de mécanique quantique et les transcapacités. Une validation de ce modèle est réalisée par des comparaisons avec des simulations TCAD 3D. Le modèle compact est implémenté en langage Verilog-A afin de simuler des circuits innovants à base de transistors FinFET. Une modélisation niveau-porte est développée pour la simulation de circuits numériques complexes. Cette thèse présente également un modèle compact générique de transistors MOSFET SOI canaux long faiblement dopés à multiple grilles. La dépendance à la température est prise en compte. Selon un concept de transformation géométrique, notre modèle compact du transistor MOSFET double grille planaire est étendu pour s'appliquer à tout autre type de transistor MOSFET à multiple grille (MuGFET). Une validation expérimentale du modèle MuGFET sur un transistor triple grille est proposée. Cette thèse apporte enfin des solutions pour la modélisation des transistors MOSFET double grille sans jonction.
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Książki na temat "GATE LEVEL SIMULATION"

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Norlén, Hassi. Quantum Computing in Practice with Qiskit® and IBM Quantum Experience®: Practical Recipes for Quantum Computer Coding at the Gate and Algorithm Level with Python. Packt Publishing, Limited, 2020.

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Gerard, Susan B. Gossamer Gardens: A writing game to enhance writing development at the elementary level. 1989.

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Bennett, D. Scott. Teaching the Scientific Study of International Processes. Oxford University Press, 2017. http://dx.doi.org/10.1093/acrefore/9780190846626.013.314.

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The Scientific Study of International Processes (SSIP) is an approach aimed at teaching of international politics scientifically. Teaching scientifically means teaching students how to use evidence to support or disprove some particular logical argument or hypothesis that reaches some level of generalization about relationships between concepts. Closely related to simply asking what evidence there is, is teaching students to address the breadth, depth, and quality of that evidence. The scientific approach may also draw attention to the logic of arguments and policies. Are policies, positions, and the arguments behind them logical? Or is some policy or position based on assumptions that are not logically related, or only true if certain auxiliary assumptions hold true? Teaching methods for SSIP include comparative case studies, experiments and surveys, data sets, and game theory and simulation. Instructors also face several challenges when seeking to teach scientifically, and in particular when they try to make time to teach methodology as part of an international politics course. Some problems are relatively easily overcome just by focusing on effective teaching. Other are unique to SSIP and cannot be dealt with quite so easily. Among these are the need to appeal to a broad audience, and dealing with students' negative reactions to the term “science” and the constraint of finite time in a course.
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Kasabov, Nikola. Foundations of Neural Networks, Fuzzy Systems, and Knowledge Engineering. The MIT Press, 1996. http://dx.doi.org/10.7551/mitpress/3071.001.0001.

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In a clear and accessible style, Kasabov describes rule-based and connectionist techniques and then their combinations, with fuzzy logic included, showing the application of the different techniques to a set of simple prototype problems, which makes comparisons possible. A particularly strong feature of the text is that it is filled with applications in engineering, business, and finance. AI problems that cover most of the application-oriented research in the field (pattern recognition, speech and image processing, classification, planning, optimization, prediction, control, decision making, and game simulations) are discussed and illustrated with concrete examples. Intended both as a text for advanced undergraduate and postgraduate students as well as a reference for researchers in the field of knowledge engineering, Foundations of Neural Networks, Fuzzy Systems, and Knowledge Engineering has chapters structured for various levels of teaching and includes original work by the author along with the classic material. Data sets for the examples in the book as well as an integrated software environment that can be used to solve the problems and do the exercises at the end of each chapter are available free through anonymous ftp. Bradford Books imprint
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Części książek na temat "GATE LEVEL SIMULATION"

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Saleh, Resve, Shyh-Jye Jou i A. Richard Newton. "Gate-Level Simulation". W Mixed-Mode Simulation and Analog Multilevel Simulation, 123–52. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4757-5854-2_5.

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Saleh, Resve A., i A. Richard Newton. "Gate-Level Simulation". W The Kluwer International Series in Engineering and Computer Science, 101–32. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-0695-5_5.

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Buard, Nadine, i Lorena Anghel. "Gate Level Modeling and Simulation". W Soft Errors in Modern Electronic Systems, 77–102. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6993-4_4.

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Maili, Alexander, Damian Dalton i Christian Steger. "A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment". W Lecture Notes in Computer Science, 799–808. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30205-6_82.

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Melikyan, Vazgen. "General Issues of Gate-Level Simulation and Optimization of Digital Circuits with Consideration of Destabilizing Factors". W Simulation and Optimization of Digital Circuits, 1–75. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-71637-4_1.

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Melikyan, Vazgen. "Algorithmic Implementation of the Automated System of Gate-Level Simulation of Digital Circuits with Consideration of DF". W Simulation and Optimization of Digital Circuits, 213–45. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-71637-4_4.

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Tang, Qin, Amir Zjajo, Michel Berkelaar i Nick van der Meijs. "Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations". W Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 190–99. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-17752-1_19.

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Melikyan, Vazgen. "Linguistic and Software Development of the Automated System of Gate-Level Simulation of Digital Circuits with Consideration of DF". W Simulation and Optimization of Digital Circuits, 301–41. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-71637-4_6.

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Tavakkoli, Alireza. "A Premier on Level Design in Unreal Technology". W Game Development and Simulation with Unreal Technology, 27–84. Title: Game development and simulation with Unreal technology/Alireza Tavakkoli. Description: Second edition. | Boca Raton : Taylor & Francis, CRC Press, 2018.| Includes bibliographical references.: A K Peters/CRC Press, 2018. http://dx.doi.org/10.1201/b22293-2.

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Kruse, L., D. Rabe i W. Nebel. "VHDL Power Simulator: Power Analysis at Gate-Level". W Hardware Description Languages and their Applications, 317–33. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-0-387-35064-6_26.

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Streszczenia konferencji na temat "GATE LEVEL SIMULATION"

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Kim, Dusung, Maciej Ciesielski, Kyuho Shim i Seiyang Yang. "Temporal parallel gate-level timing simulation". W 2008 IEEE International High Level Design Validation and Test Workshop (HLDVT). IEEE, 2008. http://dx.doi.org/10.1109/hldvt.2008.4695886.

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Viamontes, George F., Manoj Rajagopalan, Igor L. Markov i John P. Hayes. "Gate-level simulation of quantum circuits". W the 2003 conference. New York, New York, USA: ACM Press, 2003. http://dx.doi.org/10.1145/1119772.1119829.

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Jain, Alok, i Randal E. Bryant. "Mapping switch-level simulation onto gate-level hardware accelerators". W the 28th conference. New York, New York, USA: ACM Press, 1991. http://dx.doi.org/10.1145/127601.127668.

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Dusung Kim, M. Ciesielski, Kyuho Shim i Seiyang Yang. "Temporal parallel simulation: A fast gate-level HDL simulation using higher level models". W 2011 Design, Automation & Test in Europe. IEEE, 2011. http://dx.doi.org/10.1109/date.2011.5763251.

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Chatterjee, Debapriya, Andrew DeOrio i Valeria Bertacco. "Event-driven gate-level simulation with GP-GPUs". W the 46th Annual Design Automation Conference. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1629911.1630056.

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Simoglou, Stavros, Christos Sotiriou i Nikolaos Blias. "Timing Errors in STA-based Gate-Level Simulation". W 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE, 2020. http://dx.doi.org/10.1109/async49171.2020.00008.

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Chatterjee, D., A. DeOrio i V. Bertacco. "GCS: High-performance gate-level simulation with GPGPUs". W 2009 Design, Automation & Test in Europe Conference & Exhibition (DATE'09). IEEE, 2009. http://dx.doi.org/10.1109/date.2009.5090871.

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Chang, Kai-Hui, i Chris Browy. "Improving gate-level simulation accuracy when unknowns exist". W the 49th Annual Design Automation Conference. New York, New York, USA: ACM Press, 2012. http://dx.doi.org/10.1145/2228360.2228528.

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Ahmad, Tariq B., i Maciej J. Ciesielski. "Fast STA prediction-based gate-level timing simulation". W Design Automation and Test in Europe. New Jersey: IEEE Conference Publications, 2014. http://dx.doi.org/10.7873/date.2014.261.

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Ahmad, Tariq B., i Maciej J. Ciesielski. "Fast STA prediction-based gate-level timing simulation". W Design Automation and Test in Europe. New Jersey: IEEE Conference Publications, 2014. http://dx.doi.org/10.7873/date2014.261.

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Raporty organizacyjne na temat "GATE LEVEL SIMULATION"

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Vakaliuk, Tetiana A., Valerii V. Kontsedailo, Dmytro S. Antoniuk, Olha V. Korotun, Iryna S. Mintii i Andrey V. Pikilnyak. Using game simulator Software Inc in the Software Engineering education. [б. в.], luty 2020. http://dx.doi.org/10.31812/123456789/3762.

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The article presents the possibilities of using game simulator Sotware Inc in the training of future software engineer in higher education. Attention is drawn to some specific settings that need to be taken into account when training in the course of training future software engineers. More and more educational institutions are introducing new teaching methods, which result in the use of engineering students, in particular, future software engineers, to deal with real professional situations in the learning process. The use of modern ICT, including game simulators, in the educational process, allows to improve the quality of educational material and to enhance the educational effects from the use of innovative pedagogical programs and methods, as it gives teachers additional opportunities for constructing individual educational trajectories of students. The use of ICT allows for a differentiated approach to students with different levels of readiness to study. A feature of any software engineer is the need to understand the related subject area for which the software is being developed. An important condition for the preparation of a highly qualified specialist is the independent fulfillment by the student of scientific research, the generation, and implementation of his idea into a finished commercial product. In the process of research, students gain knowledge, skills of the future IT specialist and competences of the legal protection of the results of intellectual activity, technological audit, marketing, product realization in the market of innovations. Note that when the real-world practice is impossible for students, game simulators that simulate real software development processes are an alternative.
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