Rozprawy doktorskie: „Fully Integrated Voltage Regulators”

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Tong, Tao. "Improving SoC Power Delivery With Fully Integrated Switched-Capacitor Voltage Regulators". Thesis, Harvard University, 2015. http://nrs.harvard.edu/urn-3:HUL.InstRepos:23845472.

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Traditional power delivery solutions f or system-on-chip (SoC) applications rely on off-chip voltage regulators. The off-chip power delivery solution is becoming a bottleneck for SoCs, due to 1) coarse voltage domain management, 2) increased cost as well as complexity of the power delivery network, and 3) high I2R loss as supply voltages scale down with the fabrication technology. One promising solution is to integrate the voltage regulators in the SoC. While fully integrated voltage regulators (FIVRs) could resolve these problems, their performance is limited by low efficiency and high chip area overhead, especially if the conversion ratio of the converter is high (≥ 4 to-1). This thesis presents the design and implementation of two fully integrated switched-capacitor (SC) DC-DC voltage regulators. Both regulators are implemented in the SoC along with the microprocessors they deliver power to. I first present a two-stage 4-to-1 SC regulator in a flapping wing micro-robotic bee application. The regulator converts a 3.7V battery voltage down to two lower voltages (~1.8V and ~0.9V) for the rest of the circuits in the SoC. The two-stage topology and the proposed charge recycling technique improve conversion efficiency and provide very fast load regulation to handle the dynamic current fluctuation of the load circuitry. Next, I explore the power delivery architecture at the system level and propose a joint power delivery network that combines SC FIVRs with voltage stacking. Voltage stacking reduces the maximal power that the FIVRs have to provide and “hides” the FIVR conversion loss so that the latter only applies to a portion of the total power consumed by the load. The FIVRs reduce the voltage noise of the stacked voltage domains when the load in the stacked voltage domains consumes a different amount of power. To verify the benefits of this new power delivery system, a fully integrated reconfigurable SC regulator is implemented with 16 Intel microcontroller cores that are stacked in four voltage domains. The SC regulator simultaneously provides power to the four stacked voltage domains (~0.9V) from a single input voltage (~3.6V). The regulator can dynamically change its configuration to optimize its performance according to the current profiles of the stacked load. A hybrid feedback control scheme is implemented to simultaneously regulate the four stacked domains. The proposed power delivery system achieves an average efficiency of 87% and a peak efficiency of 99%. At the end of this thesis, I present my conclusion and discuss the technologies that could further improve FIVR-based power delivery systems in the future.
Engineering and Applied Sciences - Engineering Sciences

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Park, Yongwan. "Fully Integrated Hybrid Voltage Regulator for Low Voltage Applications". Thesis, State University of New York at Stony Brook, 2016. http://pqdtopen.proquest.com/#viewpdf?dispub=10132969.

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A novel hybrid regulator topology is proposed to alleviate the weaknesses of existing hybrid topologies. Contrary to the dominant existing practice, a switched-capacitor converter and a resistorless LDO operate in a parallel fashion to supply current and regulate the output voltage. The proposed topology targets a fully integrated regulator without using any inductors and resistors. The primary emphasis is on maximizing power efficiency while maintaining sufficient regulation capability (with ripple voltage less than 10% of the output voltage) and power density. The first implementation of the proposed topology operates in a single frequency mode. Simulation results in 45 nm technology demonstrate a power efficiency of approximately 85% at 100 mA load current with an input and output voltage of, respectively, 1.15 V and 0.5 V. The worst case transient response time is under 20ns when the load current varies from 65 mA to 130 mA. The worst case ripple is 22 mV while achieving a power density of 0.5 W/mm². This single-frequency hybrid voltage regulator is useful (due to its fast and continuous response and high power efficiency) when the output load current is relatively constant at a certain nominal value. However, the performance is degraded when the load current varies significantly beyond the nominal current since the current provided by switched-capacitor converter is constant. The second implementation of the proposed hybrid regulator topology partially alleviates this issue by employing two different frequencies depending on the load current. This design is also implemented in 45 nm technology. It is demonstrated that the power efficiency is maintained within 60% to 80% even though the load current varies by more than 100 mA. The power density remains the same (0.5 W/mm²). The simulation results of the proposed topology are highly competitive with recent work on integrated voltage regulators.

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Parker, Abdul Basit. "Design Approaches for Reliable Fully Integrated Voltage Regulators of High Performance Microprocessors for Highly Autonomous Systems". Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/23784/.

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High-performance multi-core processors are fully powered by Fully Integrated Voltage Regulators, which are fully integrated with the microprocessor die and provide power to various domains. The FIVR increases the efficiency of the device while also providing a boost to the available peak power. The FIVR is integrated on the die, and therefore it is also susceptible to faults and aging phenomena. These problems are not tolerable for high reliability applications, such as autonomous self-driving vehicles and in smart factories. The previously developed checker is susceptible to some faults which were not detected. These are called the critical faults and are intolerable. Therefore, two alternate schemes have been developed to detect these faults. In case of failure, the Checker is now able to give an error indication, which can be used to activate recovery procedures. Two solutions have been proposed. The first is a Built-In Self-Test Like scheme that is operated in two modes. The first mode is normal mode where the FIVR Checker operates as normal and detects most faults affecting the FIVR. The second mode is an offline testing mode that detects previously critical faults that are not detected in normal modes. The BIST Scheme was verified with respect to stuck-on transistor, stuck-open transistor and resistive bridging faults and was found to have a high fault coverage. The second scheme is a self-checking checker for the FIVR. This scheme is based on modification of the internal structure of a previously proposed monitor, thus making it completely self-checking. A new Error Indicator is also considered which is totally self-checking. Moreover, the self-checking ability of the scheme was verified with respect to stuck-on transistor, stuck-open transistor and resistive bridging faults, and this scheme was verified to be self-checking for the list of faults considered.

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Abdelfattah, Moataz. "Switched-Capacitor DC-DC Converters for Near-Threshold Design". The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1500631539574741.

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Lüders, Michael [Verfasser], Doris [Akademischer Betreuer] Schmitt-Landsiedel, Walter [Gutachter] Stechele i Doris [Gutachter] Schmitt-Landsiedel. "A Fully-Integrated, Digitally-Enhanced Low-Dropout Voltage Regulator for Energy-Constrained Microcontroller Systems / Michael Lüders ; Gutachter: Walter Stechele, Doris Schmitt-Landsiedel ; Betreuer: Doris Schmitt-Landsiedel". München : Universitätsbibliothek der TU München, 2016. http://d-nb.info/1182536123/34.

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Quintero, Francisco Javier 1955. "Analysis of an integrated voltage regulator amplifier and design alternatives". Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276753.

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This Thesis Research involves the analysis, simulation and design alternatives for an industrially-relevant voltage regulator. An initial prototype circuit, designed by Texas Instruments Inc., is simulated and analysed in detail. Then an alternative circuit is derived which improves the circuit performance by implementing different compensation techniques and some transistors modifications. The final circuit has excellent phase margin, transient response and load regulation.

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Zhang, Xin. "Fully Distributed Control and Its Analog IC Design For Scalable Multiphase Voltage Regulators". Diss., Virginia Tech, 2005. http://hdl.handle.net/10919/29576.

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Modern microprocessors require low supply voltage (about 1V), but very high current (maximum current is 300A in servers, 100A in desktop PCs and 70A in notebook PCs), and tighter voltage regulation. However, the size of a CPU Voltage Regulator (VR) needs to be reduced. To achieve much higher power density with decent efficiency in VR design is a major challenge. Moreover, the CPU current rating can vary from 40A to 300A for different kinds of computers, and CPU power supply specifications change quickly even for the same type of computers. Since the maximum power rating of one channel converter is limited, the VR channel number may vary over a large range to meet VR specifications. Traditionally, VR design with different channel numbers needs different types of VR controllers. To reduce the developing cost of different control ICs, and to maximize the market share of one design, scalable phase design based on the same type of IC is a new trend in VR design. To achieve higher power density and at the same time to achieve scalable phase design, the concept of Monolithic Voltage Regulator Channel (MVRC) is introduced in this dissertation. MVRC is a power IC with one channel converter's power MOSFETs, drivers and control circuitries monolithically integrated based on lateral device technology and working at high frequency. It can be used alone to supply a POL (Point of Load). And without the need for a separate master controller, multiple MVRC chips can be paralleled together to supply a higher current load such as a CPU. To make MVRC a reality, the key is to develop a fully distributed control scheme and its associated analog IC circuitry, so that it can provide control functions required by microprocessors and the performance must be equal or better than a traditional a centralized VRM controller. These functions includes: multiphase interleaving, Adaptive Voltage Position (AVP) and current sharing. To achieve interleaving, this dissertation introduces a novel distributed interleaving scheme that can easily achieve scalable phase interleaving without channel number limitation. Each channel's interleaving circuitry can be monolithically integrated without any external components. The proposed scheme is verified by a hardware prototype. The key building block is a self-adjusting saw-tooth generator, which can produce accurate saw-tooth waveforms without trimming. The interleaving circuit for each channel has two self-adjusting saw-tooth generators. One behaves as a Phase Lock Loop to produce accurate phase delay, and the other produces carrier signals. To achieve Adaptive Voltage Position and current sharing, a novel distributed control scheme adopting the active droop control for each channel is introduced. Verified by hardware testing and transient simulations, the proposed distributed AVP and current sharing control scheme meets the requirements of Intel's guidelines for today and future's VR design. Monte Carlo simulation and statistics analysis show that the proposed scheme has a better AVP tolerance band than the traditional centralized control if the same current sensing scheme is used, and its current sharing performance is as good as the traditional control. It is critical for the current sensing to achieve a tight AVP regulation window and good current sharing in both the traditional centralized control scheme and the proposed distributed control scheme. Inductor current sensing is widely adopted because of the acceptable accuracy and no extra power loss. However, the Signal-to-Noise Ratio (SNR) of the traditional inductor current sensing scheme may become too small to be acceptable in high frequency VR design where small inductor with small DCR is often adopted. To improve the SNR, a novel current sensing scheme with an accurate V/I converter is proposed. To reduce the complexity of building an accurate V/I converter with traditional Opamps, an accurate monolithic transconductance (Gm) amplifier with a large dynamic range is developed. The proposed Gm amplifier can achieve accurate V/I conversion without trimming. To obtain further verification, above proposed control schemes are monolithically integrated in a dual channel synchronous BUCK controller using TSMC BiCMOS 0.5um process. Testing results show that all the proposed novel analog circuits work as expected. System testing results show good interleaving, current sharing and AVP performance. The silicon size of each channel is 1800×1000um². With proposed current sensing, interleaving, AVP and current sharing, as well as their associated analog IC implementations, the technical barriers to develop a MVRC are overcome. MVRC has the potential to become a generic power IC solution for today and future POL and CPU power management. The proposed distributed interleaving, AVP and current sharing schemes can also be used in any cellular converter system. The proposed analog building blocks like the self-adjusting saw-tooth generator and the accurate transconductance amplifier can be used as basic building blocks in any DC-DC controller.
Ph. D.

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Banerjee, Saptarshi. "Power Supply Rejection (PSR) Enhancement Techniques for Fully Integrated Low-Dropout (LDO) Regulators". Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-171553.

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In this present world, there is a huge requirement of portable devices for that the analysis of low-dropout or LDO regulators have been on high priority. So, for every respective device, there is a power budget that acts as the main constraint to design an LDO. The LDO design aims to suppress the noise and supply noise-free or low noise output. This thesis paper illustrates several designs of output capacitor-less LDO architecture to enhance Power Supply Rejection (PSR) and optimization of the ideas from different literature to achieve the low quiescent current, stability with fast transient response while the input voltage is low over a wide range of load current. Differ-ent types of transistor schematic designs under definite specifications of the LDOs, which are mostly integrated by major components like Error Amplifier (EA) and pass transistor, feedback resistors, and relatively small output capacitor have mostly considered for the designs. However, some buffer attenuation techniques which can improve the PSR have also been shown with a proper diagram. The design of LDOwith the components and how to design the pass device and their trade off’s have been has been discussed. Different techniques of PSR enhancement among which some of the techniques have been implemented have been illustrated with respective diagrams. A study of executed techniques under the specifications with comparative results has been shown with their trade-off with the other architecture. The contribution is an LDO that has been simulated in Cadence specter and designed in CMOS FinFET process node atVdd= 0.95 V with a load current of 50 mA -75 mA and an output voltage of 0.75 V with a small output capacitor of 200 pF, a PSR of−25 dB at 100 MHz has been achieved whereas the current consumption at the load is 245μA, while meeting the targeted stability analysis of gain margin and phase margin of 47 dB and 63◦respectively. A small voltage droop of 36. 6mV for rising edge and−15.99 mV for falling edge over a 100μA to 75 mA step-change in10 ns has been observed.
I dagens värld finns det stora behov av bärbara enheter och krav på analys avregulatorer (LDO). För varje typ av enhet finns det en energibudget som fungerarsom huvudsaklig begränsning för att utforma en LDO. LDO-konstruktion syftar tillatt leverera brusfri eller lågbrusig utspänning. Detta examensarbete visar på flerakonstruktioner av utgångskondensatorfria LDO-arkitekturer för att förbättra PowerSupply Rejection (PSR). Optimering av idéer från olika litteraturkällor görs för attuppnå låg viloström och stabilitet med snabb respons med låg ingångsspänning överett brett intervall av lastström. Olika typer av konstruktioner schemanivå för precisa LDO-specifikationer, mestadelsintegrerade med de viktigaste komponenter såsom felförstärkare (Error Amplifier,EA) och passtransistor, återkopplingsmotstånd och relativt små utgångskonden-satorer, har studerats. Buffertdämpningstekniker som kan förbättra PSR har ocksåinkluderats. Konstruktion av LDO:er på komponentnivå och man utformar pass-enheten och dess kompromisser diskuteras också. Implementering av några olikatekniker för PSR-förbättring illustreras med schema. En studie av utförda teknikerenligt specifikationerna med jämförande resultat ingår också. Resultat är en LDO som har simulerats i Cadence Spectre i en CMOS FinFETprocess med en matningsspänning på 0,95 V, en belastningsström på 50 mA - 75mA, en utspänning på 0,75 V och med en liten utgångskondensator på 200 pF. PSRpå−25 dB vid 100 MHz har uppnåtts medan strömförbrukningen vid belastningenär 245μA, samtidigt som kraven på marginal för förstärkning på 47 dB och fas 63°har uppnåtts. Ett litet spänningsfall på 36,6 mV för stigande signal och−15,99 mV för fallande signal under en förändring från 100 μA till 75 mA på 10 ns harobserverats.

ISY

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Garcha, Preetinder (Preetinder Kaur). "Fully integrated ultra low voltage cold start system for thermal energy harvesting . ." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/105579.

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Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 93-96).
Wireless sensor networks used in various monitoring and sensing applications rely on energy harvesting for battery-less operation, as it minimizes the need for human intervention, and offers long term monitoring solutions. Typical energy harvesters use high efficiency boost converters, which are able to step-up voltages from as low as 10 mV. However, they often need > 200 mV in order to start up initially. Current solutions for achieving a low voltage start up require the use of bulky off-chip transformers, leading to undesired area overhead. This research work presents proof-of-concept for a fully integrated start-up system, which can cold-start from < 50 mV using on-chip magnetics, and also be used as an energy harvesting charger for ultra low power applications. The use of lossy on-chip transformers in a Meissner Oscillator compared to high-quality off-chip transformers pose new design and optimization challenges. Hence, we have derived intuitive analytical expressions that are well-suited for use with the on-chip magnetics, and used them to co-optimize the oscillator components. An optimized depletion mode MOS transistor was fabricated and tested with an off-chip transformer, to exhibit oscillations from <3 mV DC input voltage. An optimized on-chip transformer, 36x smaller in area than the off-chip transformers, is currently awaiting layout and fabrication. A switched capacitor DC-DC circuit has also been designed, which can rectify and boost up the oscillator's output voltage to 1.2 V, to have a complete start-up system for energy harvesting.
by Preetinder Garcha.
S.M.

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Shoukry, Ehab. "Design of a fully integrated array of high-voltage digital-to-analog converters". Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=83933.

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This thesis presents the first fully integrated array of high-voltage (HV) digital-to-analog converters (DACs). It was designed in DALSA Semiconductor's 0.8mum CMOS/DMOS HV process technology. The 6-bit 300V DACs are based on a current-steering, thermometer coded architecture. Two designs adapted to the HV technology are proposed for the current-to-high-voltage conversion as traditional output resistor or op-amp solutions are not optimum for the HV process: one uses a high-compliance current mirror, while the other uses a simple current mirror. The DACs show a DNL of 0.16LSB and 1LSB, respectively, while the INL profile is 0.16LSB and 13LSBs for the first and second designs. The array is suited for applications requiring a set of digitally-controlled high-voltage signals.

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Low, Aichen. "A floating-gate low dropout voltage regulator". Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/14886.

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Kim, Wonyoung. "Reducing Power Loss, Cost and Complexity of SoC Power Delivery Using Integrated 3-Level Voltage Regulators". Thesis, Harvard University, 2012. http://dissertations.umi.com/gsas.harvard:10721.

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Traditional methods of system-on-chip (SoC) power management based on dynamic voltage and frequency scaling (DVFS) is limited by 1) cores/IP blocks sharing a voltage domain provided by off-chip voltage regulators (VR) and 2) slow voltage scaling time \((<0.1V/\mu s)\). This global, slow DVFS cannot track the increasingly heterogeneous, fluctuating performance requirements of individual microprocessor cores and SoC components. Furthermore, traditional off-chip VRs add significant area overhead and component cost on the board. This thesis explores replacing a large portion of existing off-chip VRs with integrated voltage regulators (IVR) that can scale the voltage at a 50 mV/ns rate, which is 500 times faster than microsecond-scale voltage scaling with existing off-chip VRs. IVRs occupy 10 times smaller footprint than off-chip VRs, making it easy to duplicate them to provide per-core or per-IP-block voltage control. This thesis starts by summarizing the benefits of using IVRs to deliver power to SoCs. Based on a simulation study targeting a 1.6W, 4-core SoC, I show that greater than 20% energy savings is possible with fast, per-core DVFS enabled by IVRs. Next, I present two stand-alone IVR test-chips converting 1.8V and 2.4V to 0.4-1.4V while delivering maximum 1W to the output. Both test-chips incorporate a 3-level VR topology, which is suitable for integration because the topology allows for much smaller inductors (1nH) than existing inductor-based buck VRs. I also discuss reasons behind lower-than-simulated efficiencies in the test-chips and ways to improve. Finally, I conclude with future process technologies that can boost IVR conversion efficiencies and power densities.
Engineering and Applied Sciences

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Bunch, Ryan Lee. "A Fully Monolithic 2.5 GHz LC Voltage Controlled Oscillator in 0.35 um CMOS Technology". Thesis, Virginia Tech, 2001. http://hdl.handle.net/10919/32287.

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The explosive growth in wireless communications has led to an increased demand for wireless products that are cheaper, smaller, and lower power. Recently there has been an increased interest in using CMOS, a traditional digital and low frequency analog IC technology, to implement RF components such as mixers, voltage controlled oscillators (VCOs), and low noise amplifiers (LNAs). Future mass-market RF links, such as BlueTooth, will require the potentially low-cost single-chip solutions that CMOS can provide. In order for such single-chip solutions to be realized, RF circuits must be designed that can operate in the presence of noisy digital circuitry. The voltage controlled oscillator (VCO), an important building block for RF systems, is particularly sensitive when exposed to an electrically noisy environment. In addition, CMOS implementations of VCOs have been hampered by the lack of high-quality integrated inductors. This thesis focuses on the design of a fully integrated 2.5 GHz LC CMOS VCO. The circuit is intended as a vehicle for future mixed RF/digital noise characterization. The circuit was implemented in a 0.35 um single poly, 4 metal, 3.3 V, CMOS process available through MOSIS. The oscillator uses a complementary negative transconductance topology. This oscillator circuit is analyzed as a negative-resistance oscillator. Monolithic inductors are designed using full-wave electromagnetic field solver software. The design of an "inversion-mode" MOS (I-MOS) tuning varactor is presented, along with a discussion of the effects of varactor nonlinearity on VCO performance. I-MOS varactors are shown to have substantially improved tuning range (and tuning curve linearity) over conventional MOS varactors. Practical issues pertaining to CMOS VCO circuit design, layout, and testing are also discussed. The characterization of the VCO and the integrated passives is presented. The VCO achieves a best-case phase noise of -106.7 dBc/Hz at 100 kHz offset from a center frequency of 2.73 GHz. The tuning range is 425 MHz (17%). The circuit consumes 9 mA from a 3.3 V supply. This represents excellent performance for CMOS oscillator designs reported at this frequency. Finally, several recommendations for improvements in oscillator performance and characterization are discussed.
Master of Science

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Hardikar, Shyam. "Development of MOS-controlled devices and fully implanted processes for power and high voltage integrated microelectronics". Thesis, De Montfort University, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.271930.

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Bhavnagarwala, Azeez Jenúddin. "Voltage scaling constraints for static CMOS logic and memory cirucits". Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15401.

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Wipf, Christian [Verfasser], Dietmar [Akademischer Betreuer] Kissinger, Dietmar [Gutachter] Kissinger, Friedel [Gutachter] Gerfers i Peter [Gutachter] Weger. "Fully integrated BiCMOS high-voltage driver circuits for on-chip RF-MEMS switch matrices / Christian Wipf ; Gutachter: Dietmar Kissinger, Friedel Gerfers, Peter Weger ; Betreuer: Dietmar Kissinger". Berlin : Technische Universität Berlin, 2019. http://d-nb.info/1202071422/34.

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Mansano, Andre Luis Rodrigues. "Reguladores integrados charge-pump multiplicadores de tensão para aplicações de alta corrente". [s.n.], 2009. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259226.

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Orientadores: Jacobus Willibrordus Swart, Jader Alves de Lima Filho
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
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Resumo: Neste trabalho de Mestrado, foi projetado um conversor DC/DC charge-pump (CP) duplicador de tensão para corrente de carga máxima de 20mA, e que necessita de circuitos de controle para o apropriado acionamento das chaves, regulação de tensão e proteção do estágio duplicador de tensão. O sistema de controle projetado é composto por um circuito de regulação linear (CRL), um regulador Skip, um limitador de corrente (LC) e um circuito de bootstrapping (BOOT) que auxilia o acionamento do estágio duplicador. CP corresponde ao estágio de potência do sistema que faz interface direta com a carga, sendo sua tensão de entrada (PVIN) nominal no valor de 1,5V. O trabalho objetiva obter um conversor DC/DC funcional (demonstrado por resultados de Silício) atingindo resultados experimentais com o menor desvio possível comparados aos valores simulados durante o projeto. A tensão simulada de saída (VOUT), a vazio (sem carga), é 3V. Para carga máxima DC (20mA), o valor de VOUT simulado é de 2,4V. O circuito BOOT gera uma tensão na faixa de 4,5V - 5V, para uma carga DC de 1mA. A corrente limitada pelo bloco LC no circuito duplicador é 30mA. O CLR gera uma tensão inversamente proporcional a VOUT, tendo seus limites mínimo e máximo de 1,3V e 5,2V, respectivamente. Todo o sistema foi integrado no processo de fabricação AMS 0.35um HV, exceto os capacitores do estágio duplicador e do circuito de bootstrapping que são externos. Os resultados experimentais mostram desvio (comparados com simulação) de -12,5% em VOUT @ 20mA DC e -0,13% sem carga, -6% à saída de BOOT @ 1mA DC, +23% CLR mínimo, -3,85% em CRL máximo e +10% na corrente limitada. Durante o desenvolvimento deste trabalho, o Circuito de Regulação Linear (CRL) foi publicado no SBCCI 2009 apresentando sua rápida resposta à transientes de carga, o que é sua grande vantagem comparado a circuitos anteriormente propostos
Abstract: In this work, a DC/DC charge-pump voltage-doubler converter, for maximum load current of 20mA, was designed and fabricated. The Charge Pump (CP) needs control circuits for properly switching, voltage regulation and protection of voltage doubler stage. The control system designed comprises a linear regulation circuit (CRL), a Skip mode regulator, current limitation circuit (LC) and a bootstrapping circuit (BOOT), which provides the appropriate voltage to turn on CP power transistors. The voltage doubler is the power stage that interfaces directly to the load and its nominal input voltage PVIN is 1.5V. The objective of this work is to guarantee that the proposed DC/DC converter works properly (proved by Silicon results) and to achieve experimental results with the least deviation possible compared to simulation. The nominal output voltage (VOUT) with no load is 3V. For maximum DC load (20mA), simulated VOUT is 2.4V. BOOT circuit provides voltage within 4.5V - 5V for DC current load of 1mA. The LC limits the drawn current through the voltage-doubler at 30mA. The CRL provides a control voltage inversely proportional to VOUT and its minimum and maximum are 1.3V and 5.2V respectively. The whole system has been integrated in AMS 0.35um HV except the capacitors of CP and BOOT circuits. The experimental results show deviation (comparing to simulation) of -12,5% on VOUT @ 20mA DC and -0,13% @ no load , -6% on BOOT output @ 1mA DC, +23% CLR minimum, -3,85% CRL maximum and +10% on LC circuit. During the development of this work, the CRL circuit has been published in the SBCCI 2009 conference to present its fast-response to stringent load transient which is the biggest CRL advantage compared to previously proposed circuits
Mestrado
Mestre em Engenharia Elétrica

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Zampronho, Neto Fernando. "Analise, projeto e layout de uma topologia de circuito regulador de tensão para aplicação em microprocessadores". [s.n.], 2009. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259236.

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Orientadores: Jacobus Willibrordus Swart, Jader Alves de Lima Filho
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
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Resumo: Este trabalho tem como objetivo o estudo de uma arquitetura de regulador de tensão do tipo multi-fase para alimentação de microprocessadores, os quais demandam pequena variação em sua tensão, mesmo face aos seus agressivos transitórios de corrente. O estudo engloba a análise, que descreve as vantagens e desvantagens de topologias de reguladores chaveados, o projeto, a simulação, a fabricação e a caracterização experimental do regulador. Na etapa de projeto, uma nova abordagem no dimensionamento do filtro externo LC é apresentada, considerando-se seus respectivos elementos parasitas, a partir da introdução do parâmetro .fator de não idealidade., ou n, que é compreendido no intervalo [0, 1]. Quanto mais n se aproxima da unidade, menores serão os elementos parasitas do filtro, facilitando a escolha dos capacitores e indutores no mercado. Adicionalmente, é proposta uma técnica de projeto do compensador em freqüência, aplicada em topologias realimentadas por tensão. Esta consiste na soma de sua tensão de saída com a diferença de potencial entre dois de seus nós internos, que ocorre apenas durante o transitório de carga, reduzindo o tempo de resposta do regulador. Simulações mostraram uma queda de mais de 25% na ondulação da tensão de carga utilizando esta técnica, em comparação com a solução convencional. O processo, simulador e modelos utilizados neste trabalho são, respectivamente, o AMS H35, PSPICE e Bsim3v3. O layout do regulador foi feito via Mentor Graphics e possui área efetiva de 0,444mm2. A fabricação na foundry AMS foi viabilizada pelo programa multi-usuário da FAPESP. A caracterização experimental compara o tempo de resposta do regulador nas mesmas condições da etapa de simulação. Resultados experimentais indicaram uma redução de 96,1% na ondulação da tensão de carga durante seu transitório de corrente utilizando a técnica proposta, em comparação a solução convencional, validando a nova técnica de projeto do compensador em freqüência. O presente trabalho é concluído enfatizando-se os objetivos alcançados e principais resultados experimentais obtidos, dificuldades de projeto e limitações da arquitetura do regulador chaveado estudada
Abstract: This work aims to study the topology of multi-phase voltage regulators applied to microprocessors, where only tiny variations in the supply voltage are allowed, even when facing aggressive current transients. This study consists in the analysis, which describes the advantages and disadvantages of switched voltage regulator topologies, design, simulation, layout and experimental characterization of the proposed regulator. In the design phase, a new approach in sizing the external LC filter is herein described, considering their stray elements, through the introduction of the .non ideality. parameter, or n, which is valid within interval [0,1]. As more as n approaches unity, less parasitic elements the filter will have, easing the choice of the capacitors and inductors commercially available. In addition to this, a new technique applied to voltage feedback topologies is proposed, which consists in adding the output voltage of the frequency compensator to a voltage between two of its internal nodes. With such an approach, the response time of the regulator to load transients decreases. Simulation results show a reduction over 25% in the output voltage ripple using this new approach, when comparing to the traditional solution. The process, simulator and models used in this work are, respectively, AMS H35, PSPICE and Bsim 3v3. The layout of the regulator was edited through Mentor Graphics, and it has an effective area of 0.444mm2. The fabrication in foundry AMS was done by multi-user program of FAPESP. The experimental characterization compares the response time of the regulator in the same conditions of simulation phase. Experimental results indicated a 96,1% reduction in load voltage ripple during transient, when comparing the purposed technique with the traditional solution, validating the excellent performance of the regulator with the new design technique. This work is concluded by emphasizing the reached objectives and main experimental results reached, design difficulties and limitations of the switched-regulator architecture studied
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica

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"Wide Input Common-mode Range Fully Integrated Low-dropout Voltage Regulators". Master's thesis, 2016. http://hdl.handle.net/2286/R.I.38373.

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abstract: The modern era of consumer electronics is dominated by compact, portable, affordable smartphones and wearable computing devices. Power management integrated circuits (PMICs) play a crucial role in on-chip power management, extending battery life and efficiency of integrated analog, radio-frequency (RF), and mixed-signal cores. Low-dropout (LDO) regulators are commonly used to provide clean supply for low voltage integrated circuits, where point-of-load regulation is important. In System-On-Chip (SoC) applications, digital circuits can change their mode of operation regularly at a very high speed, imposing various load transient conditions for the regulator. These quick changes of load create a glitch in LDO output voltage, which hamper performance of the digital circuits unfavorably. For an LDO designer, minimizing output voltage variation and speeding up voltage glitch settling is an important task. The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.
Dissertation/Thesis
Masters Thesis Electrical Engineering 2016

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Kim, Doyun. "Fully Integrated Digital Low-Drop-Out Regulator Design based on Event-Driven PI Control". Thesis, 2019. https://doi.org/10.7916/d8-kfrq-qa27.

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A system-on-chip (SoC) with near-threshold supply voltage (NTV) operation has received a significant amount of attention. Its high energy-efficiency supports a number of low-power emerging applications such as wireless sensor networks and Internet-of-Thing edge devices. Integrating various digital, analog, mixed-signal, and power sub-systems, such SoC designs need to employ tens of voltage domains to push the envelope of energy-efficiency, performance, and robustness. A low-drop-out (LDO) regulator is a key building block for creating voltage domains on a chip thanks to its high power density. In particular, its digital implementation, i.e., digital LDO, recently has emerged as a popular topology since it can support a wide range of input voltage from super-threshold to near-threshold voltage regimes, while conventional analog LDOs become less effective. One of the critical overheads in existing digital LDO designs is a requirement of off-chip output capacitor for stabilizing the output voltage, due to inadequate latency in active control paths. It is possible to employ higher clock frequency in a digital LDO; however such solutions inevitably increase power dissipation. This off-chip capacitor overhead can significantly increase chip pin count and printed circuit board (PCB) space, thus limiting the number of power domains that an SoC can have. This thesis presents my research on fully-integrated digital LDO designs based on event-driven control architecture. My research focuses on scaling down the output capacitor size to the integrable level and improving transient performance such as maximum voltage change and settling time. To shrink the output capacitor size, we introduced the event-driven control and the binary digital PI controller in our first event-driven LDO design. Thanks to the event-driven control, we achieved control loop latency reduction without compromising power consumption, leading to output capacitor size reduction. The first design shows 2.7x improvement over the previous digital LDO designs in Figure-of-Merit with a 400pF of output capacitor. To further reduce output capacitor size and support larger load current, we implemented the second event-driven digital LDO designs with fine-grained parallelism. The parallel structure of its PI controller reduces the latency of the proportional part, which mainly regulates output voltage, so it achieves better transient performance with reduced size of capacitor. Also, the parallel-shift-register-based integration part lowers computation and area overheads. The second design outperforms the state of the arts by over 17x in Figure-of-Merits with only a 100pF of output capacitor. In the last design, we introduced initialization and self-triggering control. The initialization estimates load current change in the beginning of regulation process and sets the controller output close to the desired value. This leads to substantial reduction of settling time. Also, thanks to self-triggering control, the hardware overhead from counting the event interval is removed without the first response time degradation, achieving high current density. The last design with a 100pF of output capacitor improves settling time and current density by 3.8x and 6.7x, respectively, while achieving comparable transient performance in terms of Figure-of-Merit.

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Govindan, Srinivasan. "Fast Methods for Modelling and Simulation of Fully Integrated Voltage Regulators in Microprocessors". Thesis, 2022. https://etd.iisc.ac.in/handle/2005/5982.

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Fully Integrated Voltage Regulators (FIVR) have been introduced in the latest generation of high-performance server microprocessors to improve the performance and power efficiency of the processors. FIVR is a switched inductor DC-to-DC step-down converter with on-chip power bridges, control circuits and on-chip Metal-Insulator-Metal (MIM) capacitors. The inductors for FIVR are designed on the package using package traces and Plated Through Hole vias (PTH). Each FIVR module generates the voltage needed for the functional units such as the CPU cores locally, and a typical microprocessor package has more than 100 such FIVR modules. The switching frequency of FIVR is kept high (~100 MHz) to minimize the inductor size. The different components of FIVR are modelled and simulated using circuit simulators to predict the output voltage, input voltage noise, switching ripple, efficiency, etc., Due to the multiscale nature of FIVR, a lot of challenges are faced in the modelling and simulation of FIVRs by the circuit simulation approach. This thesis discusses the various challenges involved in the modelling and simulation of FIVRs and proposes fast methods to solve these challenges. At the high switching frequency of FIVR distributed effects dominate, and Full Wave Electromagnetic Extraction tools need to be used for extracting the models of the package inductors. Volume-based electromagnetic modelling tools such as the Finite Element Method (FEM) or the Finite Difference Time Domain (FDTD) method need more runtime to model the FIVR inductors as the entire volume needs to be meshed. The latest generation of FIVR inductors uses Magnetic materials for the magnetic cores with frequency-dependent permeability which further increases the runtime in volume-based methods. In this thesis, the fast surface integral equation method also known as the Method of Moments (MoM) is developed for modelling Perfect Electric Conductor (PEC) and PEC-dielectric/magnetic objects. The multiple FIVR modules in the chip share a common input supply (Vccin) for cost reduction. However, the sharing of the input supply also introduces the problem of noise coupling between the FIVRs. The load current transients at the output of one FIVR can couple to the output of other FIVRs through the input network. This noise is referred to as the Vccin feedthrough noise. The modelling of noise coupling between multi-domain FIVR is a challenge, and one normally runs into long run times or convergence issues in circuit simulation. In this thesis, two fast methods are developed to model and simulate the noise coupling in multi-domain FIVRs. The first method is a frequency-domain method and is based on the g-parameter transfer functions of FIVR. The second method is a time-domain method and is based on the state-space models of FIVR inductors and MIM capacitors determined from the Vector-Fitting technique. The proposed methods are demonstrated to improve the runtime and simplify the modelling of multi-domain FIVRs. The modelling of the input ripple noise due to the switching of the FIVR power trains is a challenge for multi-domain FIVR due to the need to include switching models of many FIVRs in circuit simulation. The input power supply (Vccin) is also a large, distributed network that prohibits the detailed switching simulation of multi-domain FIVRs. Convergence issues are faced in circuit simulations with such large models and the runtime is high. In this thesis, a Harmonic Domain (HD) method based on Linear Periodic Theory is developed to model the switching ripple voltage in multi-domain FIVRs. The various challenges faced in the circuit simulation approach can be avoided using the Harmonic Domain method. In FIVR domains with high load current, many FIVRs are ganged in parallel to supply the high load current. The modelling and simulation of ganged FIVR is a challenge due to the large scale of the problem with many FIVR modules ganged together with a large output power plane. The tuning of the FIVR control loop to attain the stability of ganged FIVRs remains a challenge with circuit simulation-based methods. Convergence issues are frequent in circuit simulations, and the runtime is high in circuit simulations. In this thesis, transfer functions are derived for ganged FIVRs from the extracted models of FIVR inductors and on-chip MIM capacitors. The transfer functions are used to model the stability of the ganged FIVR and can be used for the transient analysis also. The tuning of the FIVR control loop in a single domain FIVR is a challenge as there are a lot of Resistor-Capacitor (RC) combinations of the op-amp compensator circuit in the FIVR feedback control loop. The RC values need to be tuned to meet the control loop specifications such as the Unity Gain Bandwidth (UGB), Phase Margin (PM) and Gain Margin (GM). The practical op-amp compensator is non-ideal, and it is difficult to model its behaviour using analytical tuning methods such as the k-factor method. In this thesis, a machine learning method based on Bayesian Optimization is developed to tune the FIVR control loop and is demonstrated to reduce the number of circuit simulations significantly compared to traditional optimization methods. This method can be easily extended to post-Si measurements where the optimization is done on the fly and the next set of samples to be measured is selected based on the machine learning algorithm.
Intel Technology India Pvt Ltd

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McCue, Benjamin Matthew. "A Fully Integrated High-Temperature, High-Voltage, BCD-on-SOI Voltage Regulator". 2010. http://trace.tennessee.edu/utk_gradthes/646.

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Developments in automotive (particularly hybrid electric vehicles), aerospace, and energy production industries over the recent years have led to expanding research interest in integrated circuit (IC) design toward high-temperature applications. A high-voltage, high-temperature SOI process allows for circuit design to expand into these extreme environment applications. Nearly all electronic devices require a reliable supply voltage capable of operating under various input voltages and load currents. These input voltages and load currents can be either DC or time-varying signals. In this work, a stable supply voltage for embedded circuit functions is generated on chip via a voltage regulator circuit producing a stable 5-V output voltage. Although applications of this voltage regulator are not limited to gate driver circuits, this regulator was developed to meet the demands of a gate driver IC. The voltage regulator must provide reliable output voltage over an input range from 10 V to 30 V, a temperature range of −50 ºC to 200 ºC, and output loads from 0 mA to 200 mA. Additionally, low power stand-by operation is provided to help reduce heat generation and thus lower operating junction temperature. This regulator is based on the LM723 Zener reference voltage regulator which allows stable performance over temperature (provided proper design of the temperature compensation scheme). This circuit topology and the SOI silicon process allow for reliable operation under all application demands. The designed voltage regulator has been successfully tested from −50 ºC to 200 ºC while demonstrating an output voltage variation of less than 25 mV under the full range of input voltage. Line regulation tests from 10 V to 35 V show a 3.7-ppm/V supply sensitivity. With the use of a high-temperature ceramic output capacitor, a 5-nsec edge, 0 to 220 mA, 1-µsec pulse width load current induced only a 55 mV drop in regulator output voltage. In the targeted application, load current pulse widths will be much shorter, thereby improving the load transient performance. Full temperature and input voltage range tests reveal the no-load supply current draw is within 330 µA while still providing an excess of 200 mA of load current upon demand.

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"Time-Domain/Digital Frequency Synchronized Hysteresis Based Fully Integrated Voltage Regulator". Doctoral diss., 2019. http://hdl.handle.net/2286/R.I.55562.

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abstract: Power management integrated circuit (PMIC) design is a key module in almost all electronics around us such as Phones, Tablets, Computers, Laptop, Electric vehicles, etc. The on-chip loads such as microprocessors cores, memories, Analog/RF, etc. requires multiple supply voltage domains. Providing these supply voltages from off-chip voltage regulators will increase the overall system cost and limits the performance due to the board and package parasitics. Therefore, an on-chip fully integrated voltage regulator (FIVR) is required. The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking. The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.
Dissertation/Thesis
Doctoral Dissertation Electrical Engineering 2019

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Fletcher, Jay Brady. "Control and implementation of integrated voltage regulators". Thesis, 2013. http://hdl.handle.net/2152/23345.

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This dissertation describes the development of voltage regulators for the purpose of power reduction and further scaling in highly integrated system-on-chip products. Emphasis is placed on the architecture and implementation of integrated voltage regulation using commercially available components, standard CMOS technology, and a practical controller. The research spans the fundamental elements, architectural aspects, and detailed analog integrated circuit design.
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Aklimi, Eyal. "Magnetics and GaN for Integrated CMOS Voltage Regulators". Thesis, 2016. https://doi.org/10.7916/D87H1JQS.

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The increased use of DC-consuming electronics in many applications relevant to everyday life, necessitates significant improvements to power conversion and distribution methodologies. The surge in mobile electronics created a new power application space where high efficiency, size, and reduced complexity are critical, and at the same time, many computational tasks are relegated to centralized cloud computing centers, which consume significant amounts of energy. In both those application spaces, conversion and distribution efficiency improvements of even a few-% proves to be more and more challenging. A lot of research and development efforts target each source of loss, in an attempt to improve power electronics such that it serves the advances in other fields of electronics. Non-isolated DC-DC converters are essential in every electronics system, and improvements to efficiency, volume, weight and cost are of utmost interest. In particular, increasing the operation frequency and the conversion ratio of such converters serves the purposes of reducing the number or required conversion steps, reducing converter size, and increasing efficiency. The aforementioned improvements can be achieved by using superior technologies for the components of the converter, and by implementing higher level of integration than most present-day converters exhibit. In this work, Gallium Nitride (GaN) high electron mobility transistors (HEMT) are utilized as switches in a half-bridge buck converter topology, in conjunction with fine-line 180nm complementary metal oxide semiconductor (CMOS) driver circuitry. The circuits are integrated through a face-to-face bonding technique which results in significant reduction in interconnects parasitics and allows faster, more efficient operation. This work shows that the use of GaN transistors for the converter gives an efficiency headroom that allow pairing converters with state-of-the-art thin-film inductors with magnetic material, a task that is currently usually relegated to air-core inductors. In addition, a new "core-clad" structure for thin-film magnetic integrated inductors is presented for the use with fully integrated voltage regulators (IVRs). The core-clad topology combines aspects from the two popular inductor topologies (solenoid and cladded) to achieve higher inductance density and improved high frequency performance.

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Sturcken, Noah. "Integrated Voltage Regulators with Thin-Film Magnetic Power Inductors". Thesis, 2013. https://doi.org/10.7916/D8JW8N36.

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Integration of alternative materials and devices with CMOS will expand functionality and improve performance of established applications in the era of diminishing returns from Moore's Law scaling. In particular, integration of thin-film magnetic materials will enable improvements in energy efficiency of digital computing applications by enabling integrated power conversion and management with on-chip power inductors. Integrated voltage reg- ulators will also enable fine-grained power management, by providing dynamic scaling of the supply voltage in concert with the clock frequency of synchronous logic to throttle power consumption at periods of low computational demand. Implementation of integrated power conversion requires high capacity energy storage devices. This is best achieved with integration of thin-film magnetic materials for high quality on-chip power inductors. This thesis describes a body of work conducted to develop integrated switch-mode voltage regulators with thin-film magnetic power inductors. Soft-magnetic materials and inductor topologies are selected and optimized, with intent to maximize efficiency and current density of the integrated regulators. Custom integrated circuits are designed and fabricated in 45nm-SOI to provide the control system and power-train necessary to drive the power inductors. A silicon interposer is designed and fabricated in collaboration with IBM Research to integrate custom power inductors by 2.5D chip stacking, enabling power conversion with current density greater than 10A/mm2. The concepts and designs developed from this work will enable significant improvements in performance-per-watt of future microprocessors.

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JHAO, SYUAN-NENG, i 趙炫能. "Integrated Power Supply with Linear and Switching Voltage Regulators". Thesis, 2016. http://ndltd.ncl.edu.tw/handle/tmtv5d.

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碩士
南臺科技大學
電機工程系
104
The thesis proposed a hybrid power system with combined advantageous features of switching power supply and linear power amplifier. The switching power supply would provide the primary output voltage and power to the load, while the linear power amplifier would act as a correcting amplifying device to compensate for power ripple as a way to stabilize voltage output. Combination of these two components not only reduced the output voltage ripple but improved the overall efficiency simultaneously, as the power output level could be higher, in comparison with the low efficiency of a system with only the linear power amplifier. The thesis would explore two practical approaches of using alternating and direct current power supply. For alternating power supply, it combined the linear power amplifier and the full-bridge inverter to produce alternating voltage which had adjustable output frequency and voltage. The direct current power supply would use a linear power amplifier and a phase shift full-bridge converter to produce wide-ranged and low-rippled direct current which had adjustable output voltage. And, two prototypes of electric circuit with the maximum output power of 500W to produce final output of hybrid alternating power at 70 to 110 with the maximum frequency of 1 and a hybrid direct power at 5 to 50 would be modeled to prove the control method as practicable.

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Cheng, Gwong-Wai, i 鄭光偉. "A 5.25GHz Fully Integrated CMOS Quadrature Voltage-Controlled Oscillator". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/70224069224159570959.

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碩士
國立交通大學
電信工程系
90
A 5.25GHz fully integrated CMOS quadrature Voltage-Controlled Oscillator for IEEE 802.11a direct conversion receiver is presented. The quadrature VCO is fabricated by TSMC 0.25um CMOS process using accumulation mode MOS varactor to upgrade tuning range and lower phase noise. The architecture of VCO adopts both NMOS and PMOS cross-coupled pair to enhance negative conductance, and connects two differential LC-tank VCOs to generate four 0,90,180,270 degrees signals The measured result attain a oscillation frequency sweep from 5.260GHz ~ 5.525GHz, tuning range 265MHz, phase noise of -102.83dBc/Hz at 1MHz offset and 17.5mW power consumption at 2.5V DC supply.

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Hong, Yu-Bin, i 洪育彬. "A Fully Integrated DC-DC Converter for Dynamic Voltage Scaling". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/e7p3nq.

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碩士
國立中興大學
電機工程學系所
99
In this era of technology explosion, the idea of designing electronic products are tending to compact size much more than before, particularly the biomedical products, such as pacemakers, sensors etc., which products emphasize the size and energy consumption. The capacitors and inductors in the voltage converters which we used before were both external components, and it could occupy a large amount of volume in this way. In order to overcome this problem, if we can integrate those passive components on a single chip, then it can greatly reduce the size of the converter. The GIPD (tMt Glass Substrate Integrated Passive Device Process) can be used on a glass board to complete the production of the inductor and capacitor. The control circuit can be made on the Si board (CMOS18),and then use bump to connect two boards and utilize 3D technology to complete the micro-integration of the initiative control circuit and the passive components. The size of capacitors and inductors must be reduced to nano-scale so that they can be integrated in one chip, but it also brought some challenges. The voltage control Pulse Width Modulation (PWM) used in this thesis is to control circuit with fast transient response. And the converter can be used for dynamic voltage scaling (DVS) applications that it can change with the different voltage requirements from the loading and increase the life of the batteries and the whole system effectively. The circuit architecture is composed of error amplifier, comparator, triangle wave generator, non-overlap, digital-to-analog converter, buffer, power MOS. First, the feedback voltage and Vref are sent into the error amplifier for comparison. Then, the output voltage will be compared with a triangle wave to get a PWM control signal. To avoid energy consumption that caused by a large amount of current flowing from PMOS to NMOS while switch frequently, use the non-overlap circuit to reduce the leakage current directly from the battery to the ground and increase efficiency. The circuit uses TSMC_0.18um & GIPD process, which are combined with 3D technology. The voltage conversion is from 1.8V down to 1.3 ~ 0.6V. The maximum voltage conversion efficiency is 78.5% and the maximum load current is 150mA.

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Ramachandran, Vishwa. "Analysis of total dose effects in a low-dropout voltage regulator". Diss., 2006. http://etd.library.vanderbilt.edu/ETD-db/available/etd-12192006-190448/.

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Liang, Yu-An, i 梁佑安. "The Design of Fully-Integrated CMOS Multiple Low Dropout Regulators for Implantable Biomedical SoCs". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/36550372845105714735.

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碩士
國立交通大學
電子研究所
100
For epilepsy detection and stimulation application, the medical device should be fully implantable. In order to minimize the area consumption and eliminate the negative effect of parasitic inductance, the LDO regulators should be fully-integrated without any external component. Moreover, in an implantable medical SoC powered by inductive link power supply, a single LDO is difficult to satisfy different performance requirements of analog, digital, and reference circuits. Therefore, a topology of LDO is designed, fabricated, and tested to realize three fully-integrated LDOs with 2V to 1.8V output voltages for analog, digital, and reference circuits. The maximum driving current capabilities are 5mA, 20mA and 1.5mA, respectively. By connecting the input voltage of the LDOs to a full-wave CMOS active rectifier which is operated at 13.56MHz and powered by near-field coils with an inductive link structure. The measured ripple voltages of analog output, digital output, and reference output are 3mVp-p, 6.2mVp-p, and 0.7mVp-p, respectively.

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黃俊諺. "A Fully Integrated CMOS LC-VCO with Low Voltage and Low Power". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/92130496642238310362.

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碩士
國立交通大學
電信工程系所
96
Abstract As the advancement of wireless communication system growing rapidly. Development of radio frequency (RF) integrated circuits in low cost, high performance and low power consumption is more and more imminently. In the past, the RF front-end circuits are made by SiGe BiCMOS process technologies due to its high performance in high frequency. However, with the standard CMOS process technology getting proficient, RF front-end circuits made by CMOS process are more and more popular. As far as the actual applications are concerned, the RFICs are power-hungry devices which cause the battery life time could not be extended effectively. The problem of power consumption further restricts the applications in wireless electronic devices, especially in the demands of light, thin, short and small devices. Therefore, development of RFIC more efficient in cost and low power consumption is an emergent issue to solve. This thesis focuses on the design of low supply voltage and low power consumption and maintains comparable level of phase noise simultaneously. Using a conventional NMOS cross-coupled LC-VCO architecture which has the least stages stacked in vertical could be reduced the supply voltage. By adding a proposed NMOS pair which paralleled the LC-tank, the parasitic capacitances Cgs, Cgd of the proposed NMOS pair generate an additional negative conductance, as a result, the phase noise can be degrade effectively in low power, low supply voltage operation level. Besides, the bodies of proposed NMOS pair are biased, which generate an opposite voltage drop as compared with varactors. As a result, the common mode noise is reduced. Eventually, the goals of low power consumption and low supply voltage can be achieve due to most of the supply voltage feed the cross-couple NMOS and the added NMOS pair take no voltage drop. The proposed low voltage, low power LC-VCO is implemented by TSMC 0.18-μm 1P6M CMOS process. With only 0.51 V bias, the power consumption of the proposed LC-VCO is 1 mW. The phase noise is -112.24 dBc/Hz from 1 MHz offset frequency at 3.3GHz and the chip size of 0.61 (μm) × 0.76 (μm).

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"Design and implementation of fully integrated low-voltage low-noise CMOS VCO". 2002. http://library.cuhk.edu.hk/record=b5891102.

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Yip Kim-fung.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.
Includes bibliographical references (leaves 95-100).
Abstracts in English and Chinese.
Abstract --- p.I
Acknowledgement --- p.III
Table of Contents --- p.IV
Chapter Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Objective --- p.6
Chapter Chapter 2 --- Theory of Oscillators --- p.7
Chapter 2.1 --- Oscillator Design --- p.7
Chapter 2.1.1 --- Loop-Gain Method --- p.7
Chapter 2.1.2 --- Negative Resistance-Conductance Method --- p.8
Chapter 2.1.3 --- Crossed-Coupled Oscillator --- p.10
Chapter Chapter 3 --- Noise Analysis --- p.15
Chapter 3.1 --- Origin of Noise Sources --- p.16
Chapter 3.1.1 --- Flicker Noise --- p.16
Chapter 3.1.2 --- Thermal Noise --- p.17
Chapter 3.1.3 --- Noise Model of Varactor --- p.18
Chapter 3.1.4 --- Noise Model of Spiral Inductor --- p.19
Chapter 3.2 --- Derivation of Resonator --- p.19
Chapter 3.3 --- Phase Noise Model --- p.22
Chapter 3.3.1 --- Leeson's Model --- p.23
Chapter 3.3.2 --- Phase Noise Model defined by J. Cranincks and M Steyaert --- p.24
Chapter 3.3.3 --- Non-linear Analysis of Phase Noise --- p.26
Chapter 3.3.4 --- Flicker-Noise Upconversion Mechanism --- p.31
Chapter 3.4 --- Phase Noise Reduction Techniques --- p.33
Chapter 3.4.1 --- Conventional Tank Circuit Structure --- p.33
Chapter 3.4.2 --- Enhanced Q tank circuit Structure --- p.35
Chapter 3.4.3 --- Tank Circuit with parasitics --- p.37
Chapter 3.4.4 --- Reduction of Up-converted Noise --- p.39
Chapter Chapter 4 --- CMOS Technology and Device Modeling --- p.42
Chapter 4.1 --- Device Modeling --- p.42
Chapter 4.1.1 --- FET model --- p.42
Chapter 4.1.2 --- Layout of Interdigitated FET --- p.46
Chapter 4.1.3 --- Planar Inductor --- p.48
Chapter 4.1.4 --- Circuit Model of Planar Inductor --- p.50
Chapter 4.1.5 --- Inductor Layout Consideration --- p.54
Chapter 4.1.6 --- CMOS RF Varactor --- p.55
Chapter 4.1.7 --- Parasitics of PMOS-type varactor --- p.57
Chapter Chapter 5 --- Design of Integrated CMOS VCOs --- p.59
Chapter 5.1 --- 1.5GHz CMOS VCO Design --- p.59
Chapter 5.1.1 --- Equivalent circuit model of differential LC VCO --- p.59
Chapter 5.1.2 --- Reference Oscillator Circuit --- p.61
Chapter 5.1.3 --- Proposed Oscillator Circuit --- p.62
Chapter 5.1.4 --- Output buffer --- p.63
Chapter 5.1.5 --- Biasing Circuitry --- p.64
Chapter 5.2 --- Spiral Inductor Design --- p.65
Chapter 5.3 --- Determination of W/L ratio of FET --- p.67
Chapter 5.4 --- Varactor Design --- p.68
Chapter 5.5 --- Layout (Cadence) --- p.69
Chapter 5.6 --- Circuit Simulation (SpectreRF) --- p.74
Chapter Chapter 6 --- Experimental Results and Discussion --- p.76
Chapter 6.1 --- Measurement Setup --- p.76
Chapter 6.2 --- Measurement results: Reference Oscillator Circuit --- p.81
Chapter 6.2.1 --- Output Spectrum --- p.81
Chapter 6.2.2 --- Phase Noise Performance --- p.82
Chapter 6.2.3 --- Tuning Characteristic --- p.83
Chapter 6.2.4 --- Microphotograph --- p.84
Chapter 6.3 --- Measurement results: Proposed Oscillator Circuit --- p.85
Chapter 6.3.1 --- Output Spectrum --- p.85
Chapter 6.3.2 --- Phase Noise Performance --- p.86
Chapter 6.3.3 --- Tuning Characteristic --- p.87
Chapter 6.3.4 --- Microphotograph --- p.88
Chapter 6.4 --- Comparison of Measured Results --- p.89
Chapter 6.4.1 --- Phase Noise Performance --- p.89
Chapter 6.4.2 --- Tuning Characteristic --- p.90
Chapter Chapter 7 --- Conclusion and Future Work --- p.93
Chapter 7.1 --- Conclusion --- p.93
Chapter 7.2 --- Future Work --- p.94
References --- p.95
Author's Publication --- p.100
Appendix A --- p.101
Appendix B --- p.104
Appendix C --- p.106

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34

Jhe-JiaJhang i 張哲嘉. "Fully-Integrated Boost DC-DC Converter with Low-Startup Voltage for Thermoelectric Harvester". Thesis, 2018. http://ndltd.ncl.edu.tw/handle/2z847v.

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碩士
國立成功大學
電機工程學系
106
The most critical issue of using energy harvesters is their low output voltage, which makes it difficult to power up traditional electronic circuits. Therefore, this thesis proposes a fully-integrated inductor-based dc-dc boost converter with low startup voltage for thermoelectric harvester. In the initial state, low-voltage ring oscillator built by low supply voltage logic, charge pump and voltage-triggered pulse generator are used to charge the output capacitor and increase the output voltage (VOUT). When VOUT is high enough, the system will enter the open-loop state. When VOUT is increased to exceed another predefined voltage, the system will operate in the closed-loop state and VOUT will be regulated at 1.8V finally. It is worth mentioning that the startup technique in the proposed chip does not need to use any post-fabrication process, secondary energy source, or extra off-chip components. The proposed chip was fabricated by TSMC 0.18μm 1P6M mixed-signal standard CMOS process, and chip area is 720×735μm2. According to measurement results, the minimal startup voltage of the converter is as low as 82mV, and VOUT can be regulated between 1 V and 1.8 V. Moreover, the measured peak efficiency achieves 78.55%.

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Bull, Nora Dianne. "Design and Implementation of a High Temperature Fully-Integrated BCD-on-SOI Under Voltage Lock Out Circuit". 2009. http://trace.tennessee.edu/utk_gradthes/511.

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As concern about the environment has grown in recent years, alternatives in the automotive industry have become an important topic for researchers. One alternative being considered is electric vehicles, which utilize electric motors. DC/AC inverters and DC/DC power converters control these electric motors. A logic circuit is needed to power these converters; however, the logic generators inherently operate at a voltage too low to power the motors. A device known as the gate driver is the interface between the logic generators (or microcontroller) and the power devices (power converter). The gate driver provides the power needed to drive the power devices. Circuits are susceptible to voltage and temperature changes though. For this reason, protection circuits must be implemented as an integral part of the gate driver circuits. The Under Voltage Lock Out (UVLO) circuit provides important detection of under voltage conditions in the power supply thus preventing malfunctions. There are multiple power supplies in the gate driver circuit, and it is important to monitor all of these supplies for both surges and reductions in power. If the power supply should drop below the threshold (nominally 80%) there could be issues in the gate driver’s functionality. Since the gate driver will be located under the hood of a hybrid electric vehicles, operating temperatures can reach extremely high values. For this reason, circuit designs must provide reliable operation of the circuits in an extreme environment.

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36

Hsieh, Hsien-Cheng, i 謝先成. "The Design of Low Power Voltage Controlled Oscillator and Fully Integrated 2.4GHz CMOS Integer-N Frequency Synthesizer". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/35062195162625409055.

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碩士
國立交通大學
電信工程系
91
Through this thesis, we demonstrated a fully integrated frequency synthesizer for direct conversion receiver. The working frequency is at 2.45GHz. We begin from the design of voltage controlled oscillator (VCO), devising it at the purpose of low power consumption, and established a VCO consumes less than 1mW (It consumes only 53μA when biased at 1.5V VDD).In the design of frequency divider part, we adopt integer-N topology which provides a less power consumption for low current use consideration. The measurement results are listed as following: the oscillation frequency is tunable between 2351~2517MHz, locking time is approximately 25μs, phase noise is -88.4dBc/Hz@1MHz offset, spurious tones are less than carrier 14dB; the power consumption is 58.625mW using a 2.5V power supply.

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37

"Development of high-performance low-dropout regulators for SoC applications". 2010. http://library.cuhk.edu.hk/record=b5894389.

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Or, Pui Ying.
"July 2010."
Thesis (M.Phil.)--Chinese University of Hong Kong, 2010.
Includes bibliographical references.
Abstracts in English and Chinese.
Acknowledgments
Table of Content
List of Figures
List of Tables
List of Publications
Chapter Chapter 1 - --- Background of LDO Research
Chapter 1.1 --- Structure of a LDO --- p.1-1
Chapter 1.2 --- Principle of Operation of LDO --- p.1-2
Chapter 1.3 --- Steady-State Specification of LDO --- p.1-3
Chapter 1.4 --- High-Frequency Specification of LDO --- p.1-3
Chapter 1.5 --- Dynamic Specification of LDO --- p.1-4
Chapter 1.6 --- An Advanced LDO Structure --- p.1-4
Chapter 1.7 --- Contribution and Outline of the Thesis --- p.1-5
References --- p.1-6
Chapter Chapter 2 - --- PSRR Analysis
Chapter 2.1 --- Modeling of the PSRR of LDO --- p.2-3
Chapter 2.2 --- Analysis of LDO Circuit Using Proposed Modeling --- p.2-6
Chapter 2.3 --- Conclusion of Chapter --- p.2-12
References --- p.2-13
Chapter Chapter 3- --- An Output-Capacitorless LDO with Direct Voltage-Spike Detection
Chapter 3.1 --- Analysis of Output-Capacitorless LDO --- p.3-5
Chapter 3.2 --- LDO with Proposed Voltage-Spike Detection Circuit --- p.3-7
Chapter 3.3 --- Experimental Results --- p.3-15
Chapter 3.4 --- Conclusion of Chapter --- p.3-21
References --- p.3-22
Chapter Chapter 4 - --- A LDO with Impedance Adjustment and Loop-Gain Boosting Technique
Chapter 4.1 --- Proposed LDO --- p.4-3
Chapter 4.2 --- Experimental Results --- p.4-7
Chapter 4.3 --- Comparison --- p.4-11
Chapter 4.4 --- Conclusion of Chapter --- p.4-12
Reference --- p.4-13
Chapter Chapter 5 - --- Conclusion and Future Work

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38

Kim, Sung Justin. "Integrated and Distributed Digital Low-Drop-Out Regulators with Event-Driven Controls and Side-Channel Attack Resistance". Thesis, 2021. https://doi.org/10.7916/d8-mbs2-4z84.

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A modern system-on-chip (SoC) integrates a range of analog, digital, and mixed-signal building blocks, each with a dedicated voltage domain to maximize energy efficiency. On-chip low-drop-out regulators (LDOs) are widely used to implement these voltage domains due to their advantages of high power density and the ease of integration to a complementary metal-oxide-semiconductor (CMOS) process. Recently, digital LDOs have gained large attention for their low input voltage support for emerging sub-mW SoCs, portability across designs, and process scalability. However, some of the major drawbacks of a conventional digital LDO design are (i) the trade-off between control loop latency and power dissipation which demands a large output capacitor, (ii) failure to address the performance degradations caused by the parasitics in a practical power grid, and (iii) insufficient power-supply-rejection-ratio (PSRR) and large ripple in the output voltage. Chapters 2 through 4 of this thesis present my research on the design and circuit techniques for improving the aforementioned challenges in fully-integrated digital LDOs. The first work implements a hybrid event- and time-driven control in the digital LDO architecture to improve the response and settling time-related metrics over the existing designs. The second work presents a power delivery system consisting of 9 distributed event-driven digital LDOs for supporting a spatially large digital load. The proposed distributed LDO design achieves large improvements in the steady-state and non-steady-state performances compared to a single LDO design. In the third work, we prototype a digital LDO based on new current-source power-FETs to achieve a high PSRR and low output voltage ripple. Lastly, on-chip voltage regulators have recently found usefulness in hardware security applications. An on-chip LDO can be used to improve the side-channel attack (SCA) resistance of a cryptographic core with design modifications to the classical LDO architecture. However, the existing designs incur non-negligible overheads in performance, power, and silicon area due to the conventional active-for-all-encryption-rounds architecture. In the last chapter, we propose a detection-driven activation technique to achieve a near-zero energy-delay-product (EDP) overhead in a SCA resilient digital LDO. In this architecture, the LDO can detect an attack attempt and enable SCA protection only if an attack is detected.

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39

"Fast transient LDO using digital detection". 2012. http://library.cuhk.edu.hk/record=b5549104.

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電源管理集成電路被廣泛應用於便攜式電子應用。在同一芯片需要不同的電源電壓水平。由於芯片尺寸，工作速度和所需功耗的要求，低壓差穩壓器（LDO）在快遞瞬態響應，低噪聲，以及高精度的電子產品中具有廣泛的應用。
LDO的負載瞬間變化取決於功率金氧半場效電晶體的大小、偏置電流和誤差放大器的增益。檢測輸出電壓，並使用大電容和電阻通過電容耦合，增加偏置電流是一個簡單的方法來改善負載瞬間變化。然而，電阻電容佔據較大的芯片面積。
權衡功耗和芯片尺寸，本論文中提出用數字檢測電路取代用於瞬態耦合的大電容和電阻。所提出的電路是讓功率金氧半場效電晶體的栅極電容電流增加充電或放電，以提高LDO的負載瞬間響應速度。產生這種電流通過檢測內部的變化，並產生一個電壓脈衝控制迴轉電流，然後通過使用一組數字電路去改變充電或放電的電量。
擬議的設計已在UMC0.18微米 CMOS制程技術實現。LDO的輸入電壓為0.9伏至1.3伏和穩壓0.7伏。最大輸出電流為50豪安。經過測量，負載瞬間變化得到改善。負載瞬間的響應時間可以從75微秒（傳統）減少到75納秒。
Power-management IC is widely used in portable electronic applications. Different supply voltage levels are required in the same chip. Due to the size, speed and power requirements, low-dropout regulator (LDO) is generally adopted for applications which need fast transient response, low noise and high accuracy.
Transient response of a LDO is limited by the size of power MOSFET, biasing current and gain of error amplifier. Detecting the output voltage and using large RC components for capacitive coupling to increase the biasing current is a straightforward method to improve the transient response. However, this requires a large chip size for the RC components.
By considering power consumption and size, digital detection circuit is proposed to replace the large capacitors and resistors used for transient coupling. The proposed circuit is to increase the charging or discharging current to the gate of the power MOSFET to increase the transient speed of LDO. This current is generated by detecting the internal changes and generating a voltage pulse to control the slewing current by using a set of digital circuit.
The proposed design has been realized in UMC 0.18μm CMOS technology. The input voltage of the LDO is 0.9 to 1.3V and the regulated voltage is 0.7V. The maximum output current is 50mA. From the measurement, the transient response is improved. The response time due to load transient changes can be reduced from 75s (conventional) to 75ns.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Kwong, Ka Yee.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2012.
Includes bibliographical references.
Abstracts also in Chinese.
Abstract
Acknowledgments
Table of Content
List of Figures
List of Tables
Chapter Chapter 1 --- LDO regulator research background
Introduction
Chapter Section 1.1 --- Generic LDO regulator structure
Chapter Section 1.2 --- Principle of LDO regulator operation
Chapter Section 1.3 --- Specifications
Chapter References
Chapter Chapter 2 --- Review of state-of-the-art transient-improvement techniques for LDO regulators
Introduction
Chapter Section 2.1 --- Slew rate improvement at power transistor gate
Chapter Section 2.2 --- Frequency compensation
Chapter Section 2.3 --- Short summary
References
Chapter Chapter 3 --- A proposed output-capacitorless LDO regulator with digital voltage spike detection
Chapter Introduction
Chapter Section 3.1 --- LDO regulator core structure
Chapter Section 3.2 --- Digital switches based LDO regulator
Chapter Section 3.3 --- LDO regulator with proposed digital voltage spike detection circuit
Chapter Section 3.4 --- Simulation result
Chapter Section 3.5 --- Short summary
References
Chapter Chapter 4 --- Measurement results
Introduction
Chapter Chapter 5 --- Conclusion and Future Work

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40

Gatavi, Ehsan. "Voltage regulation and reactive power compensation to improve low voltage ride-through capability for doubly fed induction generator-based wind turbine". Thesis, 2019. http://hdl.handle.net/1959.7/uws:54766.

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Of all the renewable energies, wind power is proliferating and it now plays a significant part in the power supply. The system known as Doubly Fed Induction Generator (DFIG) is the most popular wind turbine, because it plays a very significant role in enhancing low voltage ride through (LVRT) capability. Ancillary services such as voltage control and reactive power capability are the main concerns in wind power control systems and need to be managed in detail and with great care. The lack of reactive power during a fault period can result in instability in generators and/or disconnection of a wind turbine from the power system. The main aim of this study is to explain and describe the most effective and efficient approaches for improving the stability and reliability of wind power plants. This theme is closely associated with LVRT capability enhancement. Wind farms are regarded as large-scale power plants with interconnected systems, where all systems interact with each other to improve the efficiency of the plant and thus the quality of the output power. However, the conventional centralized controller is inappropriate for such plants. Also, not many studies have paid attention to this fact due to strong nonlinear behavior of such plants. Accordingly, a new control strategy is presented in Chapter 3 based on employing MPC and incorporating the voltage and current constraints. LVRT capability is extended by adding a series of dynamic breaking resistors to deal with severe faults and to short circuit the RSC. In Chapter 4, an asymptotic model of a wind farm equipped with DFIG is given with a description of the outcomes of interconnections. The LVRT capability is improved by introducing a class of plant-wise controller for a decentralized system. This is done by taking care of voltage at an individual point of common coupling (PCC) and controlling the DFIG active and reactive power, separately. Further, a new reactive power control strategy for voltage stability and improvement of LVRT capability is presented in Chapter 5. Both RSC and GSC are taken into account for the purpose of voltage stability and improvement of systems robustness. In the algorithm developed, the required reactive power is optimally managed at an individual point of common coupling (PCC) by using linear matrix inequality (LMI) technique. JR has also been employed to have better accuracy and realize the required bound of injected reactive power. To minimize the systems conservative nature, dynamic couplings of the system are considered, unlike the existing methods. This research aims to address these shortcomings using novel methodologies. By identifying the drawbacks of existing LVRT solutions, the study specifically focuses on addressing three problems to regulate the voltage at individual points of common coupling. The objective is to maximize the DFIG output reactive power concerning the stability of the entire large- scale wind power plant by designing multiple local controllers. To sum up, the key contribution of the study is to design a control strategy that gives DFIG the ability to full the two main grid code requirements in one inclusive approach, while other existing proposals treat each requirement as a separated issue. To demonstrate the effectiveness of all approaches presented in this the- sis, MATLAB software is used for simulation. After all, the results have been demonstrated the flexibility of model predictive control technology and motivated numerous novel works and researches to address practical problems in the field of the wind power industry.

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Chang, Pei-Ke, i 張培格. "The Integrated Circuit Design of Reconfigurable Low-Power High-Performance Low-Drop-Out Voltage Regulators for Biomedical And IoT Applications". Thesis, 2016. http://ndltd.ncl.edu.tw/handle/avs6c4.

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碩士
國立臺灣科技大學
電機工程系
104
Two reconfigurable power-efficient high-performance output-capacitor-less (OCL)linear voltage regulators are proposed in this thesis. These low-drop-out (LDO) voltage regulators are designed for wearable devices in biomedical or internet of things (IoT) applications. Both regulators employ floating-gate programming technologies to achieve reconfigurability and low power consumption. These regulators adopt a floating-gate nMOS pass transistor, an adaptively biased error amplifier, and capacitive circuits for voltage reference generation and for feedback sensing. With a floating-gate nMOS pass transistor, the proposed regulators exhibit superior line regulation to conventional regulators that usually employ a pMOS pass transistor. The error amplifier adopts a class-AB input differential pair and an adaptively biased regulated cascode topology to improve transient response under the stringent constraint of low quiescent current consumption. The reference voltage is implemented by programming charges on capacitors without employing a bandgap circuit. As a result, the power consumption for bandgap reference circuit can be saved. The measured output voltage temperature coefficient can be lower than 45 ppm/◦C. By programming charges in floating-gate transistors, the regulated output voltage can be adjusted in continuum depending on the applications. The proposed first regulator is designed for low-power analog sensing front-end circuits. The designed output voltage ranges from 1.2V to 2.5V and the designed maximum load current is 1mA with output voltage drop less than 0.1%. Since the load current does not change dramatically, the design focus is on line regulation rather on load regulation. A prototype chip is designed and fabricated in a 0.35um CMOS process to demonstrate the reconfigurability and to validate the performance. With programmable quiescent current levels less than 1 A, the current efficiency is higher than 99.9%. From measurements, the line regulation is 0.17mV/V or 75dB. The designed output-capacitor-less regulator remains stable with maximum output load capacitance upto 1nF under the zero load condition. The second regulator is designed for low-power digital circuits. To cope with the dramatic changes of the load current and reduced output voltage, the second regulator improves the required minimum supply voltage of the error amplifier and employs a load transient enhancement circuit that consumes no static power. To prevent huge current consumption during the circuit start-up phase, a power-on-reset (POR) circuit is designed and verified. A folded-class-AB differential pair circuit is employed to reduce the required error amplifier minimum supply voltage to 0.9V. The maximum load current is designed to be 2mA. With programmable quiescent current levels less than 1 A, the current efficiency is higher than 99.95%. From simulations, the line regulation is 0.056mV/V or

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42

"Development of low-power high-accuracy ultrafast-transient-response low-dropout regulators for battery-powered applications". 2013. http://library.cuhk.edu.hk/record=b5884387.

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Ho, Marco.
Thesis (Ph.D.)--Chinese University of Hong Kong, 2013.
Includes bibliographical references.
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract also in Chinese.

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43

Santos, Ângelo Emanuel Neves dos. "Design and simulation of a smart bottle with fill-level sensing based on oxide TFT technology". Master's thesis, 2016. http://hdl.handle.net/10362/19593.

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Packaging is an important element responsible for brand growth and one of the main rea-sons for producers to gain competitive advantages through technological innovation. In this re-gard, the aim of this work is to design a fully autonomous electronic system for a smart bottle packaging, being integrated in a European project named ROLL-OUT. The desired application for the smart bottle is to act as a fill-level sensor system in order to determine the liquid content level that exists inside an opaque bottle, so the consumer can exactly know the remaining quantity of the product inside. An in-house amorphous indium–gallium–zinc oxide thin-film transistor (a-IGZO TFT) model, previously developed, was used for circuit designing purposes. This model was based in an artificial neural network (ANN) equivalent circuit approach. Taking into account that only n-type oxide TFTs were used, plenty of electronic building-blocks have been designed: clock generator, non-overlapping phase generator, a capacitance-to-voltage converter and a comparator. As it was demonstrated by electrical simulations, it has been achieved good functionality for each block, having a final system with a power dissipation of 2.3 mW (VDD=10 V) not considering the clock generator. Four printed circuit boards (PCBs) have been also designed in order to help in the testing phase. Mask layouts were already designed and are currently in fabrication, foreseeing a suc-cessful circuit fabrication, and a major step towards the design and integration of complex trans-ducer systems using oxide TFTs technology.

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