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Gotowa bibliografia na temat „Fully Integrated Voltage Regulators”

Autor: Grafiati

Data publikacji: 6 września 2023

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Artykuły w czasopismach na temat "Fully Integrated Voltage Regulators"

Lambert, William J., Michael J. Hill, Kaladhar Radhakrishnan, Leigh Wojewoda i Anne E. Augustine. "Package Inductors for Intel Fully Integrated Voltage Regulators". IEEE Transactions on Components, Packaging and Manufacturing Technology 6, nr 1 (styczeń 2016): 3–11. http://dx.doi.org/10.1109/tcpmt.2015.2505665.

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Lüders, M., B. Eversmann, D. Schmitt-Landsiedel i R. Brederlow. "Fully-integrated LDO voltage regulator for digital circuits". Advances in Radio Science 9 (1.08.2011): 263–67. http://dx.doi.org/10.5194/ars-9-263-2011.

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Abstract. Low-dropout (LDO) voltage regulators are widely used to supply low-voltage digital circuits. For recent ultra-low-power microcontroller systems, a fully-integrated LDO without any external capacitance is preferred in order to achieve a fast and energy-efficient wake-up. Commonly, an LDO is specified, designed and verified for DC load currents. In contrast, a digital load creates large current spikes. As an LDO designed for low quiescent current is too slow to react on fast current spikes, a minimum on-chip capacitance is required to keep the supply voltage within a certain error window. Different fully-integrated LDO topologies are investigated regarding their suitability to supply low-voltage digital circuits. The any-load stable LDO topology is selected and implemented on a 0.13 μm test-chip. The LDO is able to provide a maximum load current of 2.5 mA while consuming a quiescent current of 17 μA.

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Hosny, Mostafa, i Sameh Ibrahim. "A Tile-Based, Adaptable Boost Converter with Fast Transient Response and Small Voltage Ripples in 40 nm CMOS Technology". Electronics 12, nr 5 (3.03.2023): 1212. http://dx.doi.org/10.3390/electronics12051212.

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This work presents a fully integrated boost switched-capacitor regulator in 40 nm CMOS technology. In addition to using small MOS + MOM capacitors to reduce the area, the regulator utilizes a pseudo-6-bit analog-to-digital converter at the converter’s output to determine the driving capability needed. Combined with a 32-phase clock, this novel approach reduces control complexity, achieves small ripples, and shows a very fast transient response from zero to the maximum load of 6 mA, and vice versa, in 100 ps with output overshoot and undershoot not exceeding 4% of the regulator’s output voltage. A new Figure of Merit is developed to establish a basis for comparing fully integrated switched regulators’ transient response.

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Meyer, Joseph, Reza Moghimi i Noah Sturcken. "Package Voltage Regulators: The Answer for Power Management Challenges". International Symposium on Microelectronics 2019, nr 1 (1.10.2019): 000438–43. http://dx.doi.org/10.4071/2380-4505-2019.1.000438.

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Abstract The generational scaling of CMOS device geometries, as predicted by Moore's law, has significantly outpaced advances in CMOS package and power electronics technology. The conduction of power to a high-performance integrated circuit (IC) die typically requires close to 50% of package and IC I/O and is increasing with trends towards lower supply voltages and higher power density that occur in advanced CMOS nodes. The disparity in scaling of logic, package, and I/O technology has created a significant bottleneck that has become a dominant constraint on computational performance. By performing power conversion and voltage regulation in-package, this limitation can be mitigated. Integration of thin-film ferromagnetic inductors with CMOS technology enables single-chip power converters to be co-packaged with processors, high bandwidth memory (HBM), and/or other modules. This paper highlights the advantages of fully integrated package voltage regulators (PVRs), which include: reducing package I/O allocated for power, eliminating the need for upstream power-conversion stages, and improving transient response. These benefits substantially reduce the size, weight, and power of modern electronic systems.

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Braun, Sebastian, Norbert Kordas, Alexander Utz, Holger Kappert i Rainer Kokozinski. "Fully Integrated Sensor Electronics for Inductive Proximity Switches Operating up to 250 °C". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, HiTen (1.07.2019): 000112–16. http://dx.doi.org/10.4071/2380-4491.2019.hiten.000112.

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Abstract In this paper we present an integrated circuit for inductive proximity switches which requires very few external components and can operate under ambient temperatures up to 250 °C. The sensor system is realized in the Fraunhofer IMS H035 technology which was specifically developed for high temperature operation. The core of the circuit is built of an oscillator which is equipped with a peak detector and readout electronics for threshold detection, references and voltage regulators to provide the necessary internal voltages as well as extensive trimming capabilities to compensate for temperature effects. The circuit can be operated from a single dc-voltage supply from 12 to 35 Volts. Calibration data can be stored in an internal EEPROM. Switching distance and hysteresis are programmable for adapting the circuit to a wide range of different detector coils and sensor geometries. Two output signals are provided that can be independently set to function as push/pull or single ended switches with programmable polarity. The only external components required are blocking capacitors for supply voltage stabilization and the LC resonator circuitry. Reverse polarity protection and special high temperature ESD and clamping structures are also fully integrated on the silicon die.

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Severo, Lucas Compassi, i Wilhelmus Adrianus Maria Van Noije. "A Generic Test Board for the Electrical Characterization of ULP and ULV Fully-Differential Integrated Analog Circuits". Journal of Integrated Circuits and Systems 14, nr 3 (27.12.2019): 1–7. http://dx.doi.org/10.29292/jics.v14i3.90.

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The characterization of ultra-low power (ULP) fully-differential/balanced amplifiers and active filters is challenging due to the incompatibility with the classical single-ended (SE) and 50 Ω impedance equipment. Interface circuits between the device under test (DUT) and the equipment are needed to perform the signal conversion and to work as voltage buffers. In this work, we propose a generic test circuits to be used in the characterization of ULP and ultra-low voltage (ULV) analog circuits. The test board includes balun transformers to the signal conversion, a high input impedance and low capacitance output driver and voltage regulators to provide the target DUT supply voltage. The characterization of the proposed PCB demonstrates a bandwidth of 30 MHz, output driver input impedance of 5 MΩ with 2.5 pF capacitance and low input-referred noise. The proposed circuit was applied to the electrical characterization of two fully-differential ULV and ULP analog integrated circuits.

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Abramov, Eli, Timur Vekslender, Or Kirshenboim i Mor Mordechai Peretz. "Fully Integrated Digital Average Current-Mode Control Voltage Regulator Module IC". IEEE Journal of Emerging and Selected Topics in Power Electronics 6, nr 2 (czerwiec 2018): 485–99. http://dx.doi.org/10.1109/jestpe.2017.2771949.

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Govindan, Srinivasan, Krishna Bharath, Srikrishnan Venkataraman i Dipanjan Gope. "A State-Space-Based Method to Model Vccin Feedthrough Noise in Microprocessors With Fully Integrated Voltage Regulators". IEEE Transactions on Components, Packaging and Manufacturing Technology 11, nr 9 (wrzesień 2021): 1391–401. http://dx.doi.org/10.1109/tcpmt.2021.3098103.

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Al-Shyoukh, Mohammad, i Hoi Lee. "A Compact Fully-Integrated Extremum-Selector-Based Soft-Start Circuit for Voltage Regulators in Bulk CMOS Technologies". IEEE Transactions on Circuits and Systems II: Express Briefs 57, nr 10 (październik 2010): 818–22. http://dx.doi.org/10.1109/tcsii.2010.2058597.

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Yosef-Hay, Yoni, Dennis Øland Larsen, Pere Llimós Muntal i Ivan H. H. Jørgensen. "Fully integrated, low drop-out linear voltage regulator in 180 nm CMOS". Analog Integrated Circuits and Signal Processing 92, nr 3 (1.07.2017): 427–36. http://dx.doi.org/10.1007/s10470-017-1012-5.

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Rozprawy doktorskie na temat "Fully Integrated Voltage Regulators"

Tong, Tao. "Improving SoC Power Delivery With Fully Integrated Switched-Capacitor Voltage Regulators". Thesis, Harvard University, 2015. http://nrs.harvard.edu/urn-3:HUL.InstRepos:23845472.

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Traditional power delivery solutions f or system-on-chip (SoC) applications rely on off-chip voltage regulators. The off-chip power delivery solution is becoming a bottleneck for SoCs, due to 1) coarse voltage domain management, 2) increased cost as well as complexity of the power delivery network, and 3) high I2R loss as supply voltages scale down with the fabrication technology. One promising solution is to integrate the voltage regulators in the SoC. While fully integrated voltage regulators (FIVRs) could resolve these problems, their performance is limited by low efficiency and high chip area overhead, especially if the conversion ratio of the converter is high (≥ 4 to-1). This thesis presents the design and implementation of two fully integrated switched-capacitor (SC) DC-DC voltage regulators. Both regulators are implemented in the SoC along with the microprocessors they deliver power to. I first present a two-stage 4-to-1 SC regulator in a flapping wing micro-robotic bee application. The regulator converts a 3.7V battery voltage down to two lower voltages (~1.8V and ~0.9V) for the rest of the circuits in the SoC. The two-stage topology and the proposed charge recycling technique improve conversion efficiency and provide very fast load regulation to handle the dynamic current fluctuation of the load circuitry. Next, I explore the power delivery architecture at the system level and propose a joint power delivery network that combines SC FIVRs with voltage stacking. Voltage stacking reduces the maximal power that the FIVRs have to provide and “hides” the FIVR conversion loss so that the latter only applies to a portion of the total power consumed by the load. The FIVRs reduce the voltage noise of the stacked voltage domains when the load in the stacked voltage domains consumes a different amount of power. To verify the benefits of this new power delivery system, a fully integrated reconfigurable SC regulator is implemented with 16 Intel microcontroller cores that are stacked in four voltage domains. The SC regulator simultaneously provides power to the four stacked voltage domains (~0.9V) from a single input voltage (~3.6V). The regulator can dynamically change its configuration to optimize its performance according to the current profiles of the stacked load. A hybrid feedback control scheme is implemented to simultaneously regulate the four stacked domains. The proposed power delivery system achieves an average efficiency of 87% and a peak efficiency of 99%. At the end of this thesis, I present my conclusion and discuss the technologies that could further improve FIVR-based power delivery systems in the future.
Engineering and Applied Sciences - Engineering Sciences

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Park, Yongwan. "Fully Integrated Hybrid Voltage Regulator for Low Voltage Applications". Thesis, State University of New York at Stony Brook, 2016. http://pqdtopen.proquest.com/#viewpdf?dispub=10132969.

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A novel hybrid regulator topology is proposed to alleviate the weaknesses of existing hybrid topologies. Contrary to the dominant existing practice, a switched-capacitor converter and a resistorless LDO operate in a parallel fashion to supply current and regulate the output voltage. The proposed topology targets a fully integrated regulator without using any inductors and resistors. The primary emphasis is on maximizing power efficiency while maintaining sufficient regulation capability (with ripple voltage less than 10% of the output voltage) and power density. The first implementation of the proposed topology operates in a single frequency mode. Simulation results in 45 nm technology demonstrate a power efficiency of approximately 85% at 100 mA load current with an input and output voltage of, respectively, 1.15 V and 0.5 V. The worst case transient response time is under 20ns when the load current varies from 65 mA to 130 mA. The worst case ripple is 22 mV while achieving a power density of 0.5 W/mm². This single-frequency hybrid voltage regulator is useful (due to its fast and continuous response and high power efficiency) when the output load current is relatively constant at a certain nominal value. However, the performance is degraded when the load current varies significantly beyond the nominal current since the current provided by switched-capacitor converter is constant. The second implementation of the proposed hybrid regulator topology partially alleviates this issue by employing two different frequencies depending on the load current. This design is also implemented in 45 nm technology. It is demonstrated that the power efficiency is maintained within 60% to 80% even though the load current varies by more than 100 mA. The power density remains the same (0.5 W/mm²). The simulation results of the proposed topology are highly competitive with recent work on integrated voltage regulators.

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Parker, Abdul Basit. "Design Approaches for Reliable Fully Integrated Voltage Regulators of High Performance Microprocessors for Highly Autonomous Systems". Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/23784/.

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High-performance multi-core processors are fully powered by Fully Integrated Voltage Regulators, which are fully integrated with the microprocessor die and provide power to various domains. The FIVR increases the efficiency of the device while also providing a boost to the available peak power. The FIVR is integrated on the die, and therefore it is also susceptible to faults and aging phenomena. These problems are not tolerable for high reliability applications, such as autonomous self-driving vehicles and in smart factories. The previously developed checker is susceptible to some faults which were not detected. These are called the critical faults and are intolerable. Therefore, two alternate schemes have been developed to detect these faults. In case of failure, the Checker is now able to give an error indication, which can be used to activate recovery procedures. Two solutions have been proposed. The first is a Built-In Self-Test Like scheme that is operated in two modes. The first mode is normal mode where the FIVR Checker operates as normal and detects most faults affecting the FIVR. The second mode is an offline testing mode that detects previously critical faults that are not detected in normal modes. The BIST Scheme was verified with respect to stuck-on transistor, stuck-open transistor and resistive bridging faults and was found to have a high fault coverage. The second scheme is a self-checking checker for the FIVR. This scheme is based on modification of the internal structure of a previously proposed monitor, thus making it completely self-checking. A new Error Indicator is also considered which is totally self-checking. Moreover, the self-checking ability of the scheme was verified with respect to stuck-on transistor, stuck-open transistor and resistive bridging faults, and this scheme was verified to be self-checking for the list of faults considered.

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Abdelfattah, Moataz. "Switched-Capacitor DC-DC Converters for Near-Threshold Design". The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1500631539574741.

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Lüders, Michael [Verfasser], Doris [Akademischer Betreuer] Schmitt-Landsiedel, Walter [Gutachter] Stechele i Doris [Gutachter] Schmitt-Landsiedel. "A Fully-Integrated, Digitally-Enhanced Low-Dropout Voltage Regulator for Energy-Constrained Microcontroller Systems / Michael Lüders ; Gutachter: Walter Stechele, Doris Schmitt-Landsiedel ; Betreuer: Doris Schmitt-Landsiedel". München : Universitätsbibliothek der TU München, 2016. http://d-nb.info/1182536123/34.

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Quintero, Francisco Javier 1955. "Analysis of an integrated voltage regulator amplifier and design alternatives". Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276753.

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This Thesis Research involves the analysis, simulation and design alternatives for an industrially-relevant voltage regulator. An initial prototype circuit, designed by Texas Instruments Inc., is simulated and analysed in detail. Then an alternative circuit is derived which improves the circuit performance by implementing different compensation techniques and some transistors modifications. The final circuit has excellent phase margin, transient response and load regulation.

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Zhang, Xin. "Fully Distributed Control and Its Analog IC Design For Scalable Multiphase Voltage Regulators". Diss., Virginia Tech, 2005. http://hdl.handle.net/10919/29576.

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Modern microprocessors require low supply voltage (about 1V), but very high current (maximum current is 300A in servers, 100A in desktop PCs and 70A in notebook PCs), and tighter voltage regulation. However, the size of a CPU Voltage Regulator (VR) needs to be reduced. To achieve much higher power density with decent efficiency in VR design is a major challenge. Moreover, the CPU current rating can vary from 40A to 300A for different kinds of computers, and CPU power supply specifications change quickly even for the same type of computers. Since the maximum power rating of one channel converter is limited, the VR channel number may vary over a large range to meet VR specifications. Traditionally, VR design with different channel numbers needs different types of VR controllers. To reduce the developing cost of different control ICs, and to maximize the market share of one design, scalable phase design based on the same type of IC is a new trend in VR design. To achieve higher power density and at the same time to achieve scalable phase design, the concept of Monolithic Voltage Regulator Channel (MVRC) is introduced in this dissertation. MVRC is a power IC with one channel converter's power MOSFETs, drivers and control circuitries monolithically integrated based on lateral device technology and working at high frequency. It can be used alone to supply a POL (Point of Load). And without the need for a separate master controller, multiple MVRC chips can be paralleled together to supply a higher current load such as a CPU. To make MVRC a reality, the key is to develop a fully distributed control scheme and its associated analog IC circuitry, so that it can provide control functions required by microprocessors and the performance must be equal or better than a traditional a centralized VRM controller. These functions includes: multiphase interleaving, Adaptive Voltage Position (AVP) and current sharing. To achieve interleaving, this dissertation introduces a novel distributed interleaving scheme that can easily achieve scalable phase interleaving without channel number limitation. Each channel's interleaving circuitry can be monolithically integrated without any external components. The proposed scheme is verified by a hardware prototype. The key building block is a self-adjusting saw-tooth generator, which can produce accurate saw-tooth waveforms without trimming. The interleaving circuit for each channel has two self-adjusting saw-tooth generators. One behaves as a Phase Lock Loop to produce accurate phase delay, and the other produces carrier signals. To achieve Adaptive Voltage Position and current sharing, a novel distributed control scheme adopting the active droop control for each channel is introduced. Verified by hardware testing and transient simulations, the proposed distributed AVP and current sharing control scheme meets the requirements of Intel's guidelines for today and future's VR design. Monte Carlo simulation and statistics analysis show that the proposed scheme has a better AVP tolerance band than the traditional centralized control if the same current sensing scheme is used, and its current sharing performance is as good as the traditional control. It is critical for the current sensing to achieve a tight AVP regulation window and good current sharing in both the traditional centralized control scheme and the proposed distributed control scheme. Inductor current sensing is widely adopted because of the acceptable accuracy and no extra power loss. However, the Signal-to-Noise Ratio (SNR) of the traditional inductor current sensing scheme may become too small to be acceptable in high frequency VR design where small inductor with small DCR is often adopted. To improve the SNR, a novel current sensing scheme with an accurate V/I converter is proposed. To reduce the complexity of building an accurate V/I converter with traditional Opamps, an accurate monolithic transconductance (Gm) amplifier with a large dynamic range is developed. The proposed Gm amplifier can achieve accurate V/I conversion without trimming. To obtain further verification, above proposed control schemes are monolithically integrated in a dual channel synchronous BUCK controller using TSMC BiCMOS 0.5um process. Testing results show that all the proposed novel analog circuits work as expected. System testing results show good interleaving, current sharing and AVP performance. The silicon size of each channel is 1800×1000um². With proposed current sensing, interleaving, AVP and current sharing, as well as their associated analog IC implementations, the technical barriers to develop a MVRC are overcome. MVRC has the potential to become a generic power IC solution for today and future POL and CPU power management. The proposed distributed interleaving, AVP and current sharing schemes can also be used in any cellular converter system. The proposed analog building blocks like the self-adjusting saw-tooth generator and the accurate transconductance amplifier can be used as basic building blocks in any DC-DC controller.
Ph. D.

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Banerjee, Saptarshi. "Power Supply Rejection (PSR) Enhancement Techniques for Fully Integrated Low-Dropout (LDO) Regulators". Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-171553.

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In this present world, there is a huge requirement of portable devices for that the analysis of low-dropout or LDO regulators have been on high priority. So, for every respective device, there is a power budget that acts as the main constraint to design an LDO. The LDO design aims to suppress the noise and supply noise-free or low noise output. This thesis paper illustrates several designs of output capacitor-less LDO architecture to enhance Power Supply Rejection (PSR) and optimization of the ideas from different literature to achieve the low quiescent current, stability with fast transient response while the input voltage is low over a wide range of load current. Differ-ent types of transistor schematic designs under definite specifications of the LDOs, which are mostly integrated by major components like Error Amplifier (EA) and pass transistor, feedback resistors, and relatively small output capacitor have mostly considered for the designs. However, some buffer attenuation techniques which can improve the PSR have also been shown with a proper diagram. The design of LDOwith the components and how to design the pass device and their trade off’s have been has been discussed. Different techniques of PSR enhancement among which some of the techniques have been implemented have been illustrated with respective diagrams. A study of executed techniques under the specifications with comparative results has been shown with their trade-off with the other architecture. The contribution is an LDO that has been simulated in Cadence specter and designed in CMOS FinFET process node atVdd= 0.95 V with a load current of 50 mA -75 mA and an output voltage of 0.75 V with a small output capacitor of 200 pF, a PSR of−25 dB at 100 MHz has been achieved whereas the current consumption at the load is 245μA, while meeting the targeted stability analysis of gain margin and phase margin of 47 dB and 63◦respectively. A small voltage droop of 36. 6mV for rising edge and−15.99 mV for falling edge over a 100μA to 75 mA step-change in10 ns has been observed.
I dagens värld finns det stora behov av bärbara enheter och krav på analys avregulatorer (LDO). För varje typ av enhet finns det en energibudget som fungerarsom huvudsaklig begränsning för att utforma en LDO. LDO-konstruktion syftar tillatt leverera brusfri eller lågbrusig utspänning. Detta examensarbete visar på flerakonstruktioner av utgångskondensatorfria LDO-arkitekturer för att förbättra PowerSupply Rejection (PSR). Optimering av idéer från olika litteraturkällor görs för attuppnå låg viloström och stabilitet med snabb respons med låg ingångsspänning överett brett intervall av lastström. Olika typer av konstruktioner schemanivå för precisa LDO-specifikationer, mestadelsintegrerade med de viktigaste komponenter såsom felförstärkare (Error Amplifier,EA) och passtransistor, återkopplingsmotstånd och relativt små utgångskonden-satorer, har studerats. Buffertdämpningstekniker som kan förbättra PSR har ocksåinkluderats. Konstruktion av LDO:er på komponentnivå och man utformar pass-enheten och dess kompromisser diskuteras också. Implementering av några olikatekniker för PSR-förbättring illustreras med schema. En studie av utförda teknikerenligt specifikationerna med jämförande resultat ingår också. Resultat är en LDO som har simulerats i Cadence Spectre i en CMOS FinFETprocess med en matningsspänning på 0,95 V, en belastningsström på 50 mA - 75mA, en utspänning på 0,75 V och med en liten utgångskondensator på 200 pF. PSRpå−25 dB vid 100 MHz har uppnåtts medan strömförbrukningen vid belastningenär 245μA, samtidigt som kraven på marginal för förstärkning på 47 dB och fas 63°har uppnåtts. Ett litet spänningsfall på 36,6 mV för stigande signal och−15,99 mV för fallande signal under en förändring från 100 μA till 75 mA på 10 ns harobserverats.

ISY

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Garcha, Preetinder (Preetinder Kaur). "Fully integrated ultra low voltage cold start system for thermal energy harvesting . ." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/105579.

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Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 93-96).
Wireless sensor networks used in various monitoring and sensing applications rely on energy harvesting for battery-less operation, as it minimizes the need for human intervention, and offers long term monitoring solutions. Typical energy harvesters use high efficiency boost converters, which are able to step-up voltages from as low as 10 mV. However, they often need > 200 mV in order to start up initially. Current solutions for achieving a low voltage start up require the use of bulky off-chip transformers, leading to undesired area overhead. This research work presents proof-of-concept for a fully integrated start-up system, which can cold-start from < 50 mV using on-chip magnetics, and also be used as an energy harvesting charger for ultra low power applications. The use of lossy on-chip transformers in a Meissner Oscillator compared to high-quality off-chip transformers pose new design and optimization challenges. Hence, we have derived intuitive analytical expressions that are well-suited for use with the on-chip magnetics, and used them to co-optimize the oscillator components. An optimized depletion mode MOS transistor was fabricated and tested with an off-chip transformer, to exhibit oscillations from <3 mV DC input voltage. An optimized on-chip transformer, 36x smaller in area than the off-chip transformers, is currently awaiting layout and fabrication. A switched capacitor DC-DC circuit has also been designed, which can rectify and boost up the oscillator's output voltage to 1.2 V, to have a complete start-up system for energy harvesting.
by Preetinder Garcha.
S.M.

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Shoukry, Ehab. "Design of a fully integrated array of high-voltage digital-to-analog converters". Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=83933.

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This thesis presents the first fully integrated array of high-voltage (HV) digital-to-analog converters (DACs). It was designed in DALSA Semiconductor's 0.8mum CMOS/DMOS HV process technology. The 6-bit 300V DACs are based on a current-steering, thermometer coded architecture. Two designs adapted to the HV technology are proposed for the current-to-high-voltage conversion as traditional output resistor or op-amp solutions are not optimum for the HV process: one uses a high-compliance current mirror, while the other uses a simple current mirror. The DACs show a DNL of 0.16LSB and 1LSB, respectively, while the INL profile is 0.16LSB and 13LSBs for the first and second designs. The array is suited for applications requiring a set of digitally-controlled high-voltage signals.

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Książki na temat "Fully Integrated Voltage Regulators"

Aklimi, Eyal. Magnetics and GaN for Integrated CMOS Voltage Regulators. [New York, N.Y.?]: [publisher not identified], 2016.

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Voltage regulator circuit manual. San Diego: Academic Press, 1989.

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Sturcken, Noah. Integrated Voltage Regulators with Thin-Film Magnetic Power Inductors. [New York, N.Y.?]: [publisher not identified], 2013.

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Rincón-Mora, Gabriel A. Analog IC design with low-dropout regulators. New York: McGraw-Hill, 2009.

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Sakurai, Takayasu. Fully-depleted SOI CMOS circuits and technology for ultralow-power applications. New York: Springer, 2011.

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Au, Kristina. Design of integrated low-dropout voltage regulators. 1998, 1998.

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Hinojo, José María, Clara Luján Martínez i Antonio Torralba. Internally Compensated LDO Regulators for Modern System-on-Chip Design. Springer, 2019.

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Hinojo, José María, Clara Luján Martínez i Antonio Torralba. Internally Compensated LDO Regulators for Modern System-on-Chip Design. Springer, 2018.

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Chen, Ke-Horng. Power Management Techniques for Integrated Circuit Design. Wiley & Sons, Incorporated, John, 2016.

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Chen, Ke-Horng. Power Management Techniques for Integrated Circuit Design. Wiley & Sons, Incorporated, John, 2016.

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Części książek na temat "Fully Integrated Voltage Regulators"

Lu, Yan, i Rui P. Martins. "Design of Low Standby Power Fully Integrated Voltage Regulators". W Low-Power Circuits for Emerging Applications in Communications, Computing, and Sensing, 33–56. First edition. | Boca Raton : CRC Press / Taylor & Francis, [2018] | Series: Taylor and Francis series in devices, circuits, & systems: CRC Press, 2018. http://dx.doi.org/10.1201/9780429507564-2.

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Le, Hanh-Phuc. "Circuit Design Techniques for Fully Integrated Voltage Regulator Using Switched Capacitors". W IC Design Insights - from Selected Presentations at CICC 2017, 553–99. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003338499-17.

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Pederson, Donald O., i Kartikeya Mayaram. "Rectifiers, Regulators and Voltage References". W Analog Integrated Circuits for Communication, 521–47. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4757-2128-7_15.

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Redouté, Jean-Michel, i Michiel Steyaert. "EMI Resisting Bandgap References and Low Dropout Voltage Regulators". W EMC of Analog Integrated Circuits, 197–226. Dordrecht: Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-90-481-3230-0_6.

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Szepesi, Thomas. "Design and Circuit Techniques of Integrated Switching Voltage Regulators". W Analog Circuit Design, 265–91. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4757-2353-3_15.

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Meier, Henri B., John E. Marthinsen, Pascal A. Gantenbein i Samuel S. Weber. "Finanzplatz Schweiz: Finance Center Switzerland". W Swiss Finance, 11–62. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-23194-0_2.

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AbstractDuring the past forty years, Switzerland’s financial system has transformed itself from an outdated assortment of trading, clearing, settlement, and payment systems into “Finanzplatz Schweiz” (i.e., “Finance Center Switzerland”), a wholly integrated and fully automated electronic securities trading and post-trading infrastructure, operated and managed by the SIX Group. Because the nation’s financial system competes in a high-stakes global environment, where survival is based on successful risk management and state-of-the-art handling of financial instruments, doing so meant modifying and modernizing Swiss regulators and regulations. Customers expect ever-improving financial depth, breadth, and sophistication. These strengths form the basis for all value-added services the Swiss financial industry offers and enable Swiss financial institutions to compete internationally despite their home country’s diminutive geographical size.

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"A 1 V 5.2 GHz fully integrated CMOS synthesizer for WLAN IEEE 802.11a". W Low-Voltage CMOS RF Frequency Synthesizers, 152–72. Cambridge University Press, 2004. http://dx.doi.org/10.1017/cbo9780511541148.010.

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Daoud, Houda, Dalila Laouej, Jihene Mallek i Mourad Loulou. "Analog Integrated Circuit Optimization". W Advances in Systems Analysis, Software Engineering, and High Performance Computing, 95–130. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-1718-5.ch003.

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This chapter presents a novel telescopic operational transconductance amplifier (OTA) using the bulk-driven MOS technique. This circuit is optimized for ultra-low power applications such as biomedical devices. The proposed the bulk-driven fully differential telescopic OTA with very low threshold voltages is designed under ±0.9V supply voltage. Thanks to the particle swarm optimization (PSO) algorithm, the circuit achieves high performances. The OTA simulation results present a DC gain of 63.6dB, a GBW of 2.8MHz, a phase margin (PM) of 55.8degrees and an input referred noise of 265.3nV/√Hz for a low bias current of 52nA.

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Cornetta, Gianluca, David J. Santos i José Manuel Vázquez. "Passive Components for RF-ICs". W Advances in Wireless Technologies and Telecommunication, 189–214. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-4666-0083-6.ch008.

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The modern wireless communication industry is demanding transceivers with a high integration level operating in the gigahertz frequency range. This, in turn, has prompted intense research in the area of monolithic passive devices. Modern fabrication processes now provide the capability to integrate onto a silicon substrate inductors and capacitors, enabling a broad range of new applications. Inductors and capacitors are the core elements of many circuits, including low-noise amplifiers, power amplifiers, baluns, mixers, and oscillators, as well as fully-integrated matching networks. While the behavior and the modeling of integrated capacitors are well understood, the design of an integrated inductor is still a challenging task since its magnetic behavior is hard to predict accurately. As the operating frequency approaches the gigahertz range, device nonlinearities, coupling effects, and skin effect dominate, making difficult the design of critical parameters such as the self-resonant frequency, the quality factor, and self and mutual inductances. However, despite the parasitic effects and the low quality-factor, integrated inductors still allow for the implementation of integrated circuits with improved performances under low supply voltage. In this chapter, the authors review the technology behind monolithic capacitors and inductors on silicon substrate for high-frequency applications, with major emphasis on physical implementation and modeling.

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Pollicino, Oreste, Valerio Lubello i Aleksandar Stojanović. "Regulating Mobility-as-a-Service". W The Global Community Yearbook of International Law and Jurisprudence 2020, 405–30. Oxford University Press, 2021. http://dx.doi.org/10.1093/oso/9780197618721.003.0018.

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In recent years, Mobility-as-a-Service (MaaS) has been gaining traction among regulators and entrepreneurs. MaaS is a mobility management and distribution platform that connects multiple private and public mobility providers’ offerings to end users. By integrating mobility-supportive and other localized services across cities and states—based on dynamic databases—MaaS is expected to significantly disrupt the current transport ecosystem, making transportation more efficient, equitable, and environmentally responsible. This complex socio-technological phenomenon creates challenges across regulatory fields spanning from the delineation of property rights and data governance to urban planning and competition law. In this chapter, we analyze the EU approach to regulating MaaS. Due to a specific intersection of EU and member states competencies, the regulatory process to MaaS still lacks boilerplate clauses defining liability among integrated transport providers. Second, despite European provisions that impose static data sharing, MaaS requires dynamic sharing data as well. Only if existing regulatory gaps are covered, and more coordination at the EU level is achieved, the power of MaaS to make the transportation market more efficient, equitable, and environmentally responsible can be fully harnessed.

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Streszczenia konferencji na temat "Fully Integrated Voltage Regulators"

Govindan, Srinivasan, Dipanjan Gope, Krishna Bharath i Srikrishnan Venkataraman. "Method to Model Input Voltage Ripple in Multi-Domain Fully Integrated Voltage Regulators". W 2018 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS). IEEE, 2018. http://dx.doi.org/10.1109/edaps.2018.8680865.

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Kumar, Amit, Srinivasan Govindan i Srikrishnan Venkataraman. "A Fast method to predict the Voltage Droop for Fully Integrated Voltage Regulators in Microprocessors". W 2021 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS). IEEE, 2021. http://dx.doi.org/10.1109/edaps53774.2021.9657003.

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Govindan, Srinivasan, Krishna Bharath, Dipanjan Gope i Srikrishnan Venkataraman. "Method to Model Vccin Feedthrough Noise in Multi-Domain Fully Integrated Voltage Regulators". W 2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS). IEEE, 2018. http://dx.doi.org/10.1109/epeps.2018.8534206.

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Govindan, Srinivasan, i Srikrishnan Venkataraman. "Silicon-package power delivery co-simulation with Fully Integrated Voltage Regulators on microprocessors". W 2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS). IEEE, 2014. http://dx.doi.org/10.1109/edaps.2014.7030828.

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Burton, Edward A., Gerhard Schrom, Fabrice Paillet, Jonathan Douglas, William J. Lambert, Kaladhar Radhakrishnan i Michael J. Hill. "FIVR — Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs". W 2014 IEEE Applied Power Electronics Conference and Exposition - APEC 2014. IEEE, 2014. http://dx.doi.org/10.1109/apec.2014.6803344.

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Chen, Yuan-Chuan Steven, Dave Budka, Auston Gibertini i Joe Davis. "Power debug on Fully Integrated Voltage Regulators (FIVR) circuitry introduced deep low power states". W 2015 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2015. http://dx.doi.org/10.1109/irps.2015.7112673.

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Kar, Monodeep, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De i Saibal Mukhopadhyay. "Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines". W ISLPED '16: International Symposium on Low Power Electronics and Design. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/2934583.2934607.

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Govindan, Srinivasan, Krishna Bharath, Dipanjan Gope, Srikrishnan Venkataraman i Nikita Ambasana. "A method to model Vccinfeedthrough Noise in Microprocessors with Fully Integrated Voltage Regulators - Distributed Formulation". W 2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS). IEEE, 2019. http://dx.doi.org/10.1109/epeps47316.2019.193202.

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Govindan, Srinivasan, Krishna Bharath, Srikrishnan Venkataraman i Dipanjan Gope. "A Large-Signal Method for Modeling Vccin feedthrough Noise in Microprocessors with Fully Integrated Voltage Regulators". W 2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS). IEEE, 2020. http://dx.doi.org/10.1109/edaps50281.2020.9312913.

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Bezerra, Pedro A. M., Florian Krismer, Toke M. Andersen, Johann W. Kolar, Arvind Sridhar, Thomas Brunschwiler, Thomas Toifl i in. "Modeling and multi-objective optimization of 2.5D inductor-based Fully Integrated Voltage Regulators for microprocessor applications". W 2015 IEEE 13th Brazilian Power Electronics Conference and 1st Southern Power Electronics Conference (COBEP/SPEC). IEEE, 2015. http://dx.doi.org/10.1109/cobep.2015.7420168.

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Raporty organizacyjne na temat "Fully Integrated Voltage Regulators"

Beshouri, Greg. PR-309-14212-WEB Field Demonstration of Fully Integrated NSCR System. Chantilly, Virginia: Pipeline Research Council International, Inc. (PRCI), wrzesień 2019. http://dx.doi.org/10.55274/r0011623.

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Wednesday, October 9, 2019 3:30 pm. ET PRESENTER: Bob Goffin, Advanced Engine Technologies HOST: Chris Nowak, Kinder Morgan MODERATOR: Gary Choquette, PRCI CLICK THE DOWNLOAD/BUY BUTTON TO ACCESS THE WEBINAR REGISTRATION LINK While superficially a "simple and proven" technology, non-selective catalytic reduction (NSCR) control is in fact extremely complex, far more complex than the control of lean burn engines. Using a systems approach, PRCI research partners defined the most common failure modes for each of the components of the NSCR system. Both regulators and operators often make simplistic assumptions regarding the reliability and robustness of NSCR control. Real world experience has shown those assumptions to be unfounded. Legacy NSCR systems can go "out of compliance" resulting in gross emissions deviations while remaining "in control." This webinar will review the reasons for those deviations and then postulates a system design capable of remaining both "in control" and "in compliance." This system was then designed, developed, installed and tested. The results confirmed the theoretical analysis resulting in satisfactory system performance. The result offers regulators and operators guidelines on procuring and/or developing NSCR systems that will satisfy regulatory expectations. Learning outcomes/Benefits of attending include: - Explains for legacy rich burn engines can be upgraded with NSCR and advanced controls - Explores the instrumentation required - Looks at control algorithms involved Who should attend: - Pipeline operators - Reliability engineers and technicians - Emissions compliance specialists Recommended pre-reading: PR-309-14212-R01 Field Demonstration of Fully Integrated NSCR System Not able to attend? Register anyway to automatically receive a link to the webinar recording to view on-demand at your convenience. Attendance is limited to the first 500 registrants to join the webinar. All remaining registrants will receive a link to view the webinar recording. After registering, you will receive a confirmation email containing information about joining the webinar.

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African Open Science Platform Part 1: Landscape Study. Academy of Science of South Africa (ASSAf), 2019. http://dx.doi.org/10.17159/assaf.2019/0047.

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This report maps the African landscape of Open Science – with a focus on Open Data as a sub-set of Open Science. Data to inform the landscape study were collected through a variety of methods, including surveys, desk research, engagement with a community of practice, networking with stakeholders, participation in conferences, case study presentations, and workshops hosted. Although the majority of African countries (35 of 54) demonstrates commitment to science through its investment in research and development (R&D), academies of science, ministries of science and technology, policies, recognition of research, and participation in the Science Granting Councils Initiative (SGCI), the following countries demonstrate the highest commitment and political willingness to invest in science: Botswana, Ethiopia, Kenya, Senegal, South Africa, Tanzania, and Uganda. In addition to existing policies in Science, Technology and Innovation (STI), the following countries have made progress towards Open Data policies: Botswana, Kenya, Madagascar, Mauritius, South Africa and Uganda. Only two African countries (Kenya and South Africa) at this stage contribute 0.8% of its GDP (Gross Domestic Product) to R&D (Research and Development), which is the closest to the AU’s (African Union’s) suggested 1%. Countries such as Lesotho and Madagascar ranked as 0%, while the R&D expenditure for 24 African countries is unknown. In addition to this, science globally has become fully dependent on stable ICT (Information and Communication Technologies) infrastructure, which includes connectivity/bandwidth, high performance computing facilities and data services. This is especially applicable since countries globally are finding themselves in the midst of the 4th Industrial Revolution (4IR), which is not only “about” data, but which “is” data. According to an article1 by Alan Marcus (2015) (Senior Director, Head of Information Technology and Telecommunications Industries, World Economic Forum), “At its core, data represents a post-industrial opportunity. Its uses have unprecedented complexity, velocity and global reach. As digital communications become ubiquitous, data will rule in a world where nearly everyone and everything is connected in real time. That will require a highly reliable, secure and available infrastructure at its core, and innovation at the edge.” Every industry is affected as part of this revolution – also science. An important component of the digital transformation is “trust” – people must be able to trust that governments and all other industries (including the science sector), adequately handle and protect their data. This requires accountability on a global level, and digital industries must embrace the change and go for a higher standard of protection. “This will reassure consumers and citizens, benefitting the whole digital economy”, says Marcus. A stable and secure information and communication technologies (ICT) infrastructure – currently provided by the National Research and Education Networks (NRENs) – is key to advance collaboration in science. The AfricaConnect2 project (AfricaConnect (2012–2014) and AfricaConnect2 (2016–2018)) through establishing connectivity between National Research and Education Networks (NRENs), is planning to roll out AfricaConnect3 by the end of 2019. The concern however is that selected African governments (with the exception of a few countries such as South Africa, Mozambique, Ethiopia and others) have low awareness of the impact the Internet has today on all societal levels, how much ICT (and the 4th Industrial Revolution) have affected research, and the added value an NREN can bring to higher education and research in addressing the respective needs, which is far more complex than simply providing connectivity. Apart from more commitment and investment in R&D, African governments – to become and remain part of the 4th Industrial Revolution – have no option other than to acknowledge and commit to the role NRENs play in advancing science towards addressing the SDG (Sustainable Development Goals). For successful collaboration and direction, it is fundamental that policies within one country are aligned with one another. Alignment on continental level is crucial for the future Pan-African African Open Science Platform to be successful. Both the HIPSSA ((Harmonization of ICT Policies in Sub-Saharan Africa)3 project and WATRA (the West Africa Telecommunications Regulators Assembly)4, have made progress towards the regulation of the telecom sector, and in particular of bottlenecks which curb the development of competition among ISPs. A study under HIPSSA identified potential bottlenecks in access at an affordable price to the international capacity of submarine cables and suggested means and tools used by regulators to remedy them. Work on the recommended measures and making them operational continues in collaboration with WATRA. In addition to sufficient bandwidth and connectivity, high-performance computing facilities and services in support of data sharing are also required. The South African National Integrated Cyberinfrastructure System5 (NICIS) has made great progress in planning and setting up a cyberinfrastructure ecosystem in support of collaborative science and data sharing. The regional Southern African Development Community6 (SADC) Cyber-infrastructure Framework provides a valuable roadmap towards high-speed Internet, developing human capacity and skills in ICT technologies, high- performance computing and more. The following countries have been identified as having high-performance computing facilities, some as a result of the Square Kilometre Array7 (SKA) partnership: Botswana, Ghana, Kenya, Madagascar, Mozambique, Mauritius, Namibia, South Africa, Tunisia, and Zambia. More and more NRENs – especially the Level 6 NRENs 8 (Algeria, Egypt, Kenya, South Africa, and recently Zambia) – are exploring offering additional services; also in support of data sharing and transfer. The following NRENs already allow for running data-intensive applications and sharing of high-end computing assets, bio-modelling and computation on high-performance/ supercomputers: KENET (Kenya), TENET (South Africa), RENU (Uganda), ZAMREN (Zambia), EUN (Egypt) and ARN (Algeria). Fifteen higher education training institutions from eight African countries (Botswana, Benin, Kenya, Nigeria, Rwanda, South Africa, Sudan, and Tanzania) have been identified as offering formal courses on data science. In addition to formal degrees, a number of international short courses have been developed and free international online courses are also available as an option to build capacity and integrate as part of curricula. The small number of higher education or research intensive institutions offering data science is however insufficient, and there is a desperate need for more training in data science. The CODATA-RDA Schools of Research Data Science aim at addressing the continental need for foundational data skills across all disciplines, along with training conducted by The Carpentries 9 programme (specifically Data Carpentry 10 ). Thus far, CODATA-RDA schools in collaboration with AOSP, integrating content from Data Carpentry, were presented in Rwanda (in 2018), and during17-29 June 2019, in Ethiopia. Awareness regarding Open Science (including Open Data) is evident through the 12 Open Science-related Open Access/Open Data/Open Science declarations and agreements endorsed or signed by African governments; 200 Open Access journals from Africa registered on the Directory of Open Access Journals (DOAJ); 174 Open Access institutional research repositories registered on openDOAR (Directory of Open Access Repositories); 33 Open Access/Open Science policies registered on ROARMAP (Registry of Open Access Repository Mandates and Policies); 24 data repositories registered with the Registry of Data Repositories (re3data.org) (although the pilot project identified 66 research data repositories); and one data repository assigned the CoreTrustSeal. Although this is a start, far more needs to be done to align African data curation and research practices with global standards. Funding to conduct research remains a challenge. African researchers mostly fund their own research, and there are little incentives for them to make their research and accompanying data sets openly accessible. Funding and peer recognition, along with an enabling research environment conducive for research, are regarded as major incentives. The landscape report concludes with a number of concerns towards sharing research data openly, as well as challenges in terms of Open Data policy, ICT infrastructure supportive of data sharing, capacity building, lack of skills, and the need for incentives. Although great progress has been made in terms of Open Science and Open Data practices, more awareness needs to be created and further advocacy efforts are required for buy-in from African governments. A federated African Open Science Platform (AOSP) will not only encourage more collaboration among researchers in addressing the SDGs, but it will also benefit the many stakeholders identified as part of the pilot phase. The time is now, for governments in Africa, to acknowledge the important role of science in general, but specifically Open Science and Open Data, through developing and aligning the relevant policies, investing in an ICT infrastructure conducive for data sharing through committing funding to making NRENs financially sustainable, incentivising open research practices by scientists, and creating opportunities for more scientists and stakeholders across all disciplines to be trained in data management.

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