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Piróg, S., R. Stala i Ł. Stawiarski. "Power electronic converter for photovoltaic systems with the use of FPGA-based real-time modeling of single phase grid-connected systems". Bulletin of the Polish Academy of Sciences: Technical Sciences 57, nr 4 (1.12.2009): 345–54. http://dx.doi.org/10.2478/v10175-010-0137-9.
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Power electronic converter for photovoltaic systems with the use of FPGA-based real-time modeling of single phase grid-connected systemsThe paper presents a method of investigation of grid connected systems with a renewable energy source. The method enables fast prototyping of control systems and power converters components by real-time simulation of the system. Components of the system such as energy source (PV array), converters, filters, sensors and control algorithms are modeled in FPGA IC. Testing the systems before its practical application reduces cost and time-to-market. FPGA devices are commonly used for digital control. The resources of the FPGAs used for preliminary testing can be sufficient for the complete system modelling. Debugging tools for FPGA enable observation of many signals of the analyzed power system (as a result of the control), with very advanced triggering tools. The presented method of simulation with the use of hardware model of the power system in comparison to classical simulation tools gives better possibilities for verification of control algorithms such as MPPT or anti-islanding.
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Göhringer, Diana, Jonathan Obie, André L. S. Braga, Michael Hübner, Carlos H. Llanos i Jürgen Becker. "Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems". International Journal of Reconfigurable Computing 2011 (2011): 1–17. http://dx.doi.org/10.1155/2011/985931.
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The design space of FPGA-based processor systems is huge, because many parameters can be modified at design- and runtime to achieve an efficient system solution in terms of performance, power and energy consumption. Such parameters are, for example, the number of processors and their configurations, the clock frequencies at design time, the use of dynamic frequency scaling at runtime, the application task distribution, and the FPGA type and size. The major contribution of this paper is the exploration of all these parameters and their impact on performance, power dissipation, and energy consumption for four different application scenarios. The goal is to introduce a first approach for a developer's guideline, supporting the choice of an optimized and specific system parameterization for a target application on FPGA-based multiprocessor systems-on-chip. The FPGAs used for these explorations were Xilinx Virtex-4 and Xilinx Virtex-5. The performance results were measured on the FPGA while the power consumption was estimated using the Xilinx XPower Analyzer tool. Finally, a novel runtime adaptive multiprocessor architecture for dynamic clock frequency scaling is introduced and used for the performance, power and energy consumption evaluations.
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Trinh, Nguyen, Anh Le Thi Kim, Hung Nguyen i Linh Tran. "Algorithmic TCAM on FPGA with data collision approach". Indonesian Journal of Electrical Engineering and Computer Science 22, nr 1 (1.04.2021): 89. http://dx.doi.org/10.11591/ijeecs.v22.i1.pp89-96.
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<span>Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA resources have been proposed through recent years. Algorithmic TCAM on FPGA have the advantages of FPGAs low power consumption and high intergration scalability. This paper proposes a scaleable algorithmic TCAM design on FPGA. The design uses memory blocks to negate power dissipation issue and data collision to save area. The paper also presents a design of a 256 x 104-bit algorithmic TCAM on Intel FPGA Cyclone V, evaluates the performance and application ability of the design on large scale and in future developments.</span>
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Ding, Dian Kuan, Li Xin Li, Yi Wan i Qi Xue. "Studies on MPPT in the Grid-Connected Photovoltaic Power Generation System Application". Applied Mechanics and Materials 63-64 (czerwiec 2011): 377–80. http://dx.doi.org/10.4028/www.scientific.net/amm.63-64.377.
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A set of PV grid-connected controlling system basing on FPGA and MCU is designed after the study of PV grid-connected system in this paper. The function of FPGA is to control the inverter main current, and the MCU is used to realize the MPPT technology. It is very effective after testing.
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UZUN, ISA SERVAN, i ABBES AMIRA. "A FPGA-BASED PARAMETRIZABLE SYSTEM FOR HIGH-RESOLUTION FREQUENCY-DOMAIN IMAGE FILTERING". Journal of Circuits, Systems and Computers 14, nr 05 (październik 2005): 895–921. http://dx.doi.org/10.1142/s0218126605002775.
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Signal and image processing applications require high computational power with the ability to experiment different algorithms involving matrix transforms. Reconfigurable hardware devices in the form of Field Programmable Gate Arrays (FPGAs) have been proposed to obtain high performance at an economical price. However, the users must program FPGAs at a very low level and must have a detailed knowledge of the architecture of the device being used. In trying to reconcile the dual requirements of high performance and the ease of development, this paper reports the design and realization of the Fast Fourier Transforms (FFTs) using a FPGA-based environment, which enables system designer to meet different system requirements (i.e., chip area, speed, memory, etc.) for a range of signal processing and imaging applications. The use of the proposed environment has been proven by the developing a high-level FPGA-based parametrizable image processing system for frequency-domain filtering application. The system achieves real-time image filtering performance exceeding those of currently available solutions by an order of magnitude in frame rate and input image size.
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Drozd, Oleksandr, Grzegorz Nowakowski, Anatoliy Sachenko, Viktor Antoniuk, Volodymyr Kochan i Myroslav Drozd. "Power-Oriented Monitoring of Clock Signals in FPGA Systems for Critical Application". Sensors 21, nr 3 (25.01.2021): 792. http://dx.doi.org/10.3390/s21030792.
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This paper presents a power-oriented monitoring of clock signals that is designed to avoid synchronization failure in computer systems such as FPGAs. The proposed design reduces power consumption and increases the power-oriented checkability in FPGA systems. These advantages are due to improvements in the evaluation and measurement of corresponding energy parameters. Energy parameter orientation has proved to be a good solution for detecting a synchronization failure that blocks logic monitoring circuits. Key advantages lay in the possibility to detect a synchronization failure hidden in safety-related systems by using traditional online testing that is based on logical checkability. Two main types of power-oriented monitoring are considered: detecting a synchronization failure based on the consumption and the dissipation of power, which uses temperature and current consumption sensors, respectively. The experiments are performed on real FPGA systems with the controlled synchronization disconnection and the use of the computer-aided design (CAD) utility to estimate the decreasing values of the energy parameters. The results demonstrate the limited checkability of FPGA systems when using the thermal monitoring of clock signals and success in monitoring by the consumption current.
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Hosseinghorban, Ali, i Akash Kumar. "A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications". Electronics 11, nr 7 (22.03.2022): 978. http://dx.doi.org/10.3390/electronics11070978.
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Rapid and continuous evolution in telecommunication standards and applications has increased the demand for a platform with high parallelization capability, high flexibility, and low power consumption. FPGAs are known platforms that can provide all these requirements. However, the evaluation of approaches, architectures, and scheduling policies in this era requires a suitable and open-source benchmark suite that runs on FPGA. This paper harnesses high-level synthesis tools to implement high-performance, resource-efficient, and easy-maintenance kernels for FPGAs. We provide various implementations of each kernel of PHY-Bench and WiBench, which are the most well-known benchmark suites for telecommunication applications on FPGAs. We analyze the execution time and power consumption of different kernels on ARM processors and FPGA. We have made all sources and documentation public for the benefit of the research community. The codes are flexible, and all kernels can easily be regenerated for different sizes. The results show that the FPGA can increase the speed by up to 19.4 times. Furthermore, we show that the power consumption of the FPGA can be reduced by up to 45% by partially reconfiguring a kernel that fits the size of the input data instead of using a large kernel that supports all inputs. We also show that partial reconfiguration can improve the execution time for processing a sub-frame in the uplink application by 33% compared to an FPGA-based approach without partial reconfiguration.
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Blouin, Dominique, Daniel Chillet, Eric Senn, Sébastien Bilavarn, Robin Bonamy i Christian Samoyeau. "AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC". International Journal of Reconfigurable Computing 2011 (2011): 1–15. http://dx.doi.org/10.1155/2011/425401.
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With the evolution of technology, the system complexity increased and the application fields of the embedded system expanded. Current applications need a high degree of performance, flexibility, and efficient development environments. Today, reconfigurable logic allows to meet the on-chip processing requirements with new benefits resulting from partial and dynamic reconfiguration. But the dimension introduced in the design of these systems requires more abstraction to manage their complexity and efficient models to provide reliable preliminary estimations. While classical multiprocessor systems can be modeled without difficulty, the use of partial run-time reconfiguration in heterogeneous flexible system-on-chips is generally not covered. The contribution of this paper is to address this with an extension of the AADL language able to model the reconfigurable logic, possibly considering dynamic reconfiguration and power consumption requirements. The proposed AADL model is divided into three levels to provide a generic and hierarchical approach separating the static and dynamic parts of current FPGAs. These levels are exposed in detail and illustrated on a concrete example of FPGA device. The design space exploration of an application deployment using this model is also presented.
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Jamieson, Peter, Donald Blank, Janelle Ghanem, Tyler McGrew i Giancarlo Corti. "A Methodology for an FPGA Implementation of a Programmable Logic Controller to Control an Atomic Layer Deposition System". International Journal of Reconfigurable Computing 2022 (6.05.2022): 1–10. http://dx.doi.org/10.1155/2022/8827417.
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In this work, we present an industrial cold walled Atomic Layer Deposition (ALD) system, which can be controlled by either a traditional programmable logic controller (PLC) system or a field-programmable gate array (FPGA) prototyping board. This work presents an FPGA controlled system that takes ladder diagram (LD) control for a PLC and converts this control to Verilog HDL and programs an FPGA such that the FPGA prototyping board is used to control a real industrial application. We explore this approach since FPGA implementation of LD control could significantly reduce the cost of implementing these controllers with other potential advantages such as the improved granularity of timing control from milliseconds to nanoseconds, additional available pins for inputs and outputs far exceeding that of microprocessors, and lower power consumption for control. In this work, we provide details and descriptions of our industrial system (ALD), the LD control of this system and its implementation, our software flow to convert LDs to Verilog HDL, and our FPGA prototype board design to replace the existing electronic controller. We show how our LD-Verilog HDL converter in conjunction with FPGAs matches a PLC and demonstrate some of the benefits of using an FPGA.
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Zhu, Qi Shen. "The Application of Remote Monitoring System Based on FPGA in Power System". Advanced Materials Research 433-440 (styczeń 2012): 4038–41. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.4038.
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Modbus bus has been widely used in the power system. For the seamless integrated realization of enterprise control and management information, the remote interaction of Modbus bus meter data is needed. This design is based on the problems involved in the process of practical power system application. Using FPGA EP2C35F672 hardware platform, UART, DM9000A external chips are extended to complete remote operation and monitoring of Modbus equipment. The field bus and the Internet network interconnection can be realized, so the decentralization and open for control system are improved. The design can be used to rebuild the existing power field bus network. This design has good prospects and practical value.
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Akkar, Hanan A. R., i Huthaifa Salman Khairy. "Design of a Field Programmable Gate Array for Swarm Intelligent Controller Based on a Portable Robotic System". Journal of Cases on Information Technology 23, nr 2 (kwiecień 2021): 65–75. http://dx.doi.org/10.4018/jcit.20210401.oa6.
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Portable robots are considered an important device in many areas such as in medical, space research, emergency situations, applications, etc. The robots complete tasks efficiently and effectively without any human interaction. The most important advantages of portable robots are their small size and very high speed in problem processing with relatively high accuracy and efficiency compared with constant devices. In this paper, the authors discussed the applications of the robot systems based on swarm intelligent controller and field programmable gate array (FPGA). A component-oriented FPGA design platform is proposed for robot system integration because FPGAs are known to be power-efficient hardware platforms. From the results, they found that FPGA and swarm intelligence are very efficient in robotic systems and used in a wide area of applications.
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Doğan, Atakan, i Kemal Ebcioğlu. "Cloud Building Block Chip for Creating FPGA and ASIC Clouds". ACM Transactions on Reconfigurable Technology and Systems 15, nr 2 (30.06.2022): 1–35. http://dx.doi.org/10.1145/3466822.
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Hardware-accelerated cloud computing systems based on FPGA chips (FPGA cloud) or ASIC chips (ASIC cloud) have emerged as a new technology trend for power-efficient acceleration of various software applications. However, the operating systems and hypervisors currently used in cloud computing will lead to power, performance, and scalability problems in an exascale cloud computing environment. Consequently, the present study proposes a parallel hardware hypervisor system that is implemented entirely in special-purpose hardware, and that virtualizes application-specific multi-chip supercomputers, to enable virtual supercomputers to share available FPGA and ASIC resources in a cloud system. In addition to the virtualization of multi-chip supercomputers, the system’s other unique features include simultaneous migration of multiple communicating hardware tasks, and on-demand increase or decrease of hardware resources allocated to a virtual supercomputer. Partitioning the flat hardware design of the proposed hypervisor system into multiple partitions and applying the chip unioning technique to its partitions, the present study introduces a cloud building block chip that can be used to create FPGA or ASIC clouds as well. Single-chip and multi-chip verification studies have been done to verify the functional correctness of the hypervisor system, which consumes only a fraction of (10%) hardware resources.
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Li, Shuai, Kuangyuan Sun, Yukui Luo, Nandakishor Yadav i Ken Choi. "Novel CNN-Based AP2D-Net Accelerator: An Area and Power Efficient Solution for Real-Time Applications on Mobile FPGA". Electronics 9, nr 5 (18.05.2020): 832. http://dx.doi.org/10.3390/electronics9050832.
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Standard convolutional neural networks (CNNs) have large amounts of data redundancy, and the same accuracy can be obtained even in lower bit weights instead of floating-point representation. Most CNNs have to be developed and executed on high-end GPU-based workstations, for which it is hard to transplant the existing implementations onto portable edge FPGAs because of the limitation of on-chip block memory storage size and battery capacity. In this paper, we present adaptive pointwise convolution and 2D convolution joint network (AP2D-Net), an ultra-low power and relatively high throughput system combined with dynamic precision weights and activation. Our system has high performance, and we make a trade-off between accuracy and power efficiency by adopting unmanned aerial vehicle (UAV) object detection scenarios. We evaluate our system on the Zynq UltraScale+ MPSoC Ultra96 mobile FPGA platform. The target board can get the real-time speed of 30 fps under 5.6 W, and the FPGA on-chip power is only 0.6 W. The power efficiency of our system is 2.8× better than the best system design on a Jetson TX2 GPU and 1.9× better than the design on a PYNQ-Z1 SoC FPGA.
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Pérez, Ignacio, i Miguel Figueroa. "A Heterogeneous Hardware Accelerator for Image Classification in Embedded Systems". Sensors 21, nr 8 (9.04.2021): 2637. http://dx.doi.org/10.3390/s21082637.
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Convolutional neural networks (CNN) have been extensively employed for image classification due to their high accuracy. However, inference is a computationally-intensive process that often requires hardware acceleration to operate in real time. For mobile devices, the power consumption of graphics processors (GPUs) is frequently prohibitive, and field-programmable gate arrays (FPGA) become a solution to perform inference at high speed. Although previous works have implemented CNN inference on FPGAs, their high utilization of on-chip memory and arithmetic resources complicate their application on resource-constrained edge devices. In this paper, we present a scalable, low power, low resource-utilization accelerator architecture for inference on the MobileNet V2 CNN. The architecture uses a heterogeneous system with an embedded processor as the main controller, external memory to store network data, and dedicated hardware implemented on reconfigurable logic with a scalable number of processing elements (PE). Implemented on a XCZU7EV FPGA running at 200 MHz and using four PEs, the accelerator infers with 87% top-5 accuracy and processes an image of 224×224 pixels in 220 ms. It consumes 7.35 W of power and uses less than 30% of the logic and arithmetic resources used by other MobileNet FPGA accelerators.
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Sönmez, Burcu, i Ahmet Bedri Özer. "Power Side Channel Analysis and Anomaly Detection of Modular Exponentiation Method in Digital Signature Algorithm Based Fpga". ITM Web of Conferences 22 (2018): 01041. http://dx.doi.org/10.1051/itmconf/20182201041.
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In this study, digital signature application was performed on FPGA with classical RSA and Chinese Remainder Theorem (CRT). The power consumption of the system was observed when the digital signature process was performed on the FPGA. In order to distinguish the modular exponentiation methods as the classical RSA and the Chinese Remainder Theorem (CRT), the anomaly detection method was applied to the digital signature application using the power side channel analysis of the system. According to the obtained result, it is proved that information about the structure of the algorithm executing in the system can be obtained by using the power information consumed by a cryptographic device.
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Cong, Vo. "Industrial robot arm controller based on programmable System-on-Chip device". FME Transactions 49, nr 4 (2021): 1025–34. http://dx.doi.org/10.5937/fme2104025c.
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Field-programmable gate arrays (FPGAs) and, recently, System on Chip (SoC) devices have been applied in a wide area of applications due to their flexibility for real-time implementations, increasing the processing capability on hardware as well as the speed of processing information in real-time. The most important applications based on FPGA/SoC devices are focused on signal/image processing, Internet of Things (IoT) technology, artificial intelligence (AI) algorithms, energy systems applications, automatic control and industrial applications. This paper develops a robot arm controller based on a programmable System-OnChip (SoC) device that combines the high-performance and flexibility of a CPU and the processing power of an FPGA. The CPU consists of a dual-core ARM processor that handles algorithm calculations, motion planning and manages communication and data manipulation. FPGA is mainly used to generate signals to control servo and read the feedback signals from encoders. Data from the ARM processor is transferred to the programmable logic side via the AXI protocol. This combination delivers superior parallel-processing and computing power, real-time performance and versatile connectivity. Additionally, having the complete controller on a single chip allows the hardware design to be simpler, more reliable, and less expensive.
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Al-Haddad, R., R. Oreifej, R. A. Ashraf i R. F. DeMara. "Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption". International Journal of Reconfigurable Computing 2011 (2011): 1–25. http://dx.doi.org/10.1155/2011/430808.
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As reconfigurable devices' capacities and the complexity of applications that use them increase, the need forself-relianceof deployed systems becomes increasingly prominent. Organic computing paradigms have been proposed for fault-tolerant systems because they promote behaviors that allow complex digital systems to adapt and survive in demanding environments. In this paper, we develop asustainable modular adaptive redundancy technique (SMART)composed of a two-layered organic system. The hardware layer is implemented on a XilinxVirtex-4Field Programmable Gate Array (FPGA) to provide self-repair using a novel approach calledreconfigurable adaptive redundancy system (RARS). The software layer supervises the organic activities on the FPGA and extends the self-healing capabilities through application-independent, intrinsic, and evolutionary repair techniques that leverage the benefits of dynamic partial reconfiguration (PR). SMART was evaluated using a Sobel edge-detection application and was shown to tolerate stressful sequences of injected transient and permanent faults while reducing dynamic power consumption by 30% compared to conventionaltriple modular redundancy (TMR)techniques, with nominal impact on the fault-tolerance capabilities. Moreover, PR is employed to keep the system on line while under repair and also to reduce repair time. Experiments have shown a 27.48% decrease in repair time when PR is employed compared to the full bitstream configuration case.
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Liu, Cheng, Zhe Li i Jia Jia Hou. "Simulation and Application of PLD in Electric Power System Circuit". Applied Mechanics and Materials 241-244 (grudzień 2012): 1931–35. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.1931.
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Programmable Logic Device(PLD) has been widely used in hardware circuit, and it has evolved into two types: Complex Programmable Logic Device(CPLD) and Field Programmable Gate Array(FPGA). This paper takes small current grounding in electric power system as background, uses xc95144, a representative CPLD of Xilinx Company in the signal collecting circuit to collect voltage and current signals, and do some other operations to spare circuit board area. This paper also tries to translate the schematic into VHDL-described text and do simulation to the text.
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Singh, Vijay Kumar, i Ravi Nath Tripathi. "An FPGA Hardware-in-the-Loop Approach for Comprehensive Analysis and Development of Grid-Connected VSI System". Energies 16, nr 2 (9.01.2023): 759. http://dx.doi.org/10.3390/en16020759.
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Power electronic converters are used for an efficient and controlled conversion of power generated from renewable energy sources and can interface generated power to the grid. Among available power converters, voltage source inverters (VSIs) have been widely employed for grid-connected applications due to better controllability with higher efficiency. Although various conventional, as well as modern control techniques, have been developed for grid connected VSI system, there is a need to select suitable control technique based on application and control requirements. Hardware-in-the-loop (HIL) is considered as a realistic approach for the development of system and control due to the inclusion of an actual hardware system. In this paper, a HIL approach is adopted for the comprehensive analysis and development of a grid connected VSI system using a field programmable gate array (FPGA). The control techniques must deal with trade-off, based on the features and limitations. Therefore, a grid-connected VSI system is developed considering employment of two different conventional control techniques: hysteresis current control (HCC) and PI-based space vector modulation (PI-SVM), as well as finite state model predictive control (FS-MPC) as a modern control technique for investigation considering different parameters. All three control systems are developed through a digital simulator of Xilinx that is integrated with MATLAB-Simulink, while considering an FPGA based system development and testing through FPGA HIL co-simulation methodology.
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Masadeh, Mahmoud, Yassmeen Elderhalli, Osman Hasan i Sofiene Tahar. "A Quality-assured Approximate Hardware Accelerators–based on Machine Learning and Dynamic Partial Reconfiguration". ACM Journal on Emerging Technologies in Computing Systems 17, nr 4 (31.10.2021): 1–19. http://dx.doi.org/10.1145/3462329.
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Machine learning is widely used these days to extract meaningful information out of the Zettabytes of sensors data collected daily. All applications require analyzing and understanding the data to identify trends, e.g., surveillance, exhibit some error tolerance. Approximate computing has emerged as an energy-efficient design paradigm aiming to take advantage of the intrinsic error resilience in a wide set of error-tolerant applications. Thus, inexact results could reduce power consumption, delay, area, and execution time. To increase the energy-efficiency of machine learning on FPGA, we consider approximation at the hardware level, e.g., approximate multipliers. However, errors in approximate computing heavily depend on the application, the applied inputs, and user preferences. However, dynamic partial reconfiguration has been introduced, as a key differentiating capability in recent FPGAs, to significantly reduce design area, power consumption, and reconfiguration time by adaptively changing a selective part of the FPGA design without interrupting the remaining system. Thus, integrating “Dynamic Partial Reconfiguration” (DPR) with “Approximate Computing” (AC) will significantly ameliorate the efficiency of FPGA-based design approximation. In this article, we propose hardware-efficient quality-controlled approximate accelerators, which are suitable to be implemented in FPGA-based machine learning algorithms as well as any error-resilient applications. Experimental results using three case studies of image blending, audio blending, and image filtering applications demonstrate that the proposed adaptive approximate accelerator satisfies the required quality with an accuracy of 81.82%, 80.4%, and 89.4%, respectively. On average, the partial bitstream was found to be 28.6 smaller than the full bitstream .
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Luo, Yukun. "FPGA Implementation for Rapid Prototyping of High Performance Voltage Source Inverters". CPSS Transactions on Power Electronics and Applications 6, nr 4 (grudzień 2021): 320–31. http://dx.doi.org/10.24295/cpsstpea.2021.00030.
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Field-programmable gate array (FPGA) is a powerful platform that can play an essential role in high-performance digital control of power electronics systems. However, the FPGA system’s design is quite different from that of a traditional microprocessor or a digital signal processor (DSP). Instead of sequential programming using high-level languages, such as C/C++, FPGA controller implementation requires a hardware description language (HDL) such as Verilog and VHDL, which requires extensive verification and optimization during the design process. This paper proposes a systematic FPGA design methodology with optimum resource utilization for rapid prototyping of high-performance power electronics applications to facilitate the widespread adoption of FPGA technology in power electronics. The FPGA controller design is concurrent with the power stage and utilizes high-level synthesis (HLS) tools and Simulink code generation toolbox. This paper covers the detailed design, implementation, and experimental validation of two specific applications, i.e., an active power filter (APF) and a motor emulator (ME), demonstrating the generalized features of the methodology. Employing fundamentally different control structures, both application examples achieve ultra-high current control bandwidth leveraging SiC MOSFETs switching at no less than 100 kHz.
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Przybył, Andrzej. "FPGA-Based Optimization of Industrial Numerical Machine Tool Servo Drives". Electronics 12, nr 17 (24.08.2023): 3585. http://dx.doi.org/10.3390/electronics12173585.
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This paper presents an analysis of the advantages stemming from the application of field-programmable gate arrays (FPGAs) in servo drives used within the control systems of industrial numerical machine tools. The method of improving the control system that allows for increasing the precision of machining, as well as incorporating new functionalities and streamlining diagnostic processes, is described. As demonstrated, the utilization of digital controllers with robust computational power and high-performance real-time communication interfaces is essential for achieving these objectives. This study underscores the limitations of commonly employed digital controllers in servo drives, which are constructed based on microcontrollers or signal processors collaborating with application-specific integrated circuits (ASICs). In contrast, the proposed FPGA-based solution offers substantial computational power and significantly reduced latencies in the real-time communication interface compared to other examined alternatives. This enables the realization of the planned objectives, specifically the enhancement of technical parameters and diagnostic capabilities of machine tools. Furthermore, the research indicates that FPGA-based digital controllers exhibit relatively low power consumption and a simplified design of the electronic printed circuit board in comparison to other analyzed digital platforms. These features can contribute to heightened reliability and diminished production costs of such controllers. Additional conclusions drawn from the study indicate that FPGA-based controllers provide greater developmental possibilities and their production is marked by potential resilience to challenges associated with the availability of electronic components in the market.
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Yang, Jiarun. "FPGA-based PPM Modulation System Design". Highlights in Science, Engineering and Technology 53 (30.06.2023): 98–107. http://dx.doi.org/10.54097/hset.v53i.9687.
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As a widely used modulation technique in the field of communication, PPM modulation techniques have the advantages of high interference immunity, simple coding and high-power utilization, and are often applied in practical scenarios. PPM modulation techniques can be divided into three categories. single pulse position modulation, differential pulse position modulation and multi pulse position modulation. In different application scenarios, different kinds of pulse position modulation methods should be selected for modulation. In this paper, the frame structures of these three types of pulse position modulation are discussed using the Verilog language based on FPGA, the corresponding mapping relationships for each type of pulse position modulation are given, and the design and performance of these three types of pulse position modulation demodulation systems are compared.
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Silva, Francisco de Assis Tavares Ferreira da, Magno Prudêncio de Almeida Filho, Antonio Macilio Pereira de Lucena i Alexandre Guirland Nowosad. "Pattern recognition on FPGA for aerospace applications". Research, Society and Development 10, nr 12 (14.09.2021): e83101219181. http://dx.doi.org/10.33448/rsd-v10i12.19181.
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This paper presents a low power near real-time pattern recognition technique based on Mathematical Morphology-MM implemented on FPGA (Field Programmable Gate Array). The key to the success of this approach concerns the advantages of machine learning paradigm applied to the translation invariant template-matching operators from MM. The paper shows that compositions of simple elementary operators from Mathematical Morphology based on ELUTs (Elementary Look-Up Tables) are very suitable to embed in FPGA hardware. The paper also shows the development techniques regarding all mathematical modeling for computer simulation and system generating models applied for hardware implementation using FPGA chip. In general, image processing on FPGAs requires low-level description of desired operations through Hardware Description Language-HDL, which uses high complexity to describe image operations at pixel level. However, this work presents a reconfiguring pattern recognition device implemented directly in FPGA from mathematical modeling simulation under Matlab/Simulink/System Generator environment. This strategy has reduced the hardware development complexity. The device will be useful mainly when applied on remote sensing tasks for aerospace missions using passive or active sensors.
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Sharma, Dimple, Lev Kirischian i Valeri Kirischian. "Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC". Computers 7, nr 4 (11.10.2018): 52. http://dx.doi.org/10.3390/computers7040052.
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Systems for application domains like robotics, aerospace, defense, autonomous vehicles, etc. are usually developed on System-on-Programmable Chip (SoPC) platforms, capable of supporting several multi-modal computation-intensive tasks on their FPGAs. Since such systems are mostly autonomous and mobile, they have rechargeable power sources and therefore, varying power budgets. They may also develop hardware faults due to radiation, thermal cycling, aging, etc. Systems must be able to sustain the performance requirements of their multi-task multi-modal workload in the presence of variations in available power or occurrence of hardware faults. This paper presents an approach for mitigating power budget variations and hardware faults (transient and permanent) by run-time structural adaptation of the SoPC. The proposed method is based on dynamically allocating, relocating and re-integrating task-specific processing circuits inside the partially reconfigurable FPGA to accommodate the available power budget, satisfy tasks’ performances and hardware resource constraints, and/or to restore task functionality affected by hardware faults. The proposed method has been experimentally implemented on the ARM Cortex-A9 processor of Xilinx Zynq XC7Z020 FPGA. Results have shown that structural adaptation can be done in units of milliseconds since the worst-case decision-making process does not exceed the reconfiguration time of a partial bit-stream.
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Saddik, Amine, Rachid Latif i Abdelhafid El Ouardi. "Low-Power FPGA Architecture Based Monitoring Applications in Precision Agriculture". Journal of Low Power Electronics and Applications 11, nr 4 (30.09.2021): 39. http://dx.doi.org/10.3390/jlpea11040039.
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Today’s on-chip systems technology has grounded impressive advances in computing power and energy consumption. The choice of the right architecture depends on the application. In our case, we were studying vegetation monitoring algorithms in precision agriculture. This study presents a system based on a monitoring algorithm for agricultural fields, an electronic architecture based on a CPU-FPGA SoC system and the OpenCL parallel programming paradigm. We focused our study on our own dataset of agricultural fields to validate the results. The fields studied in our case are in the Guelmin-Oued noun region in the south of Morocco. These fields are divided into two areas, with a total surface of 3.44 Ha2 for the first field and 3.73 Ha2 for the second. The images were collected using a DJI-type unmanned aerial vehicle and an RGB camera. Performance evaluation showed that the system could process up to 86 fps versus 12 fps or 20 fps in C/C++ and OpenMP implementations, respectively. Software optimizations have increased the performance to 107 fps, which meets real-time constraints.
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Śmigielski, Grzegorz. "Numerical control system based on a programmable logic device". MATEC Web of Conferences 357 (2022): 01005. http://dx.doi.org/10.1051/matecconf/202235701005.
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The article presents a numerical control system of a multi-axis machine built using a programmable logic device.The system consists of PC, motor controller (based on FPGA), power stages and motors. The complete code of controller was written in the VHDL language and implementing in Xilinx Spartan 3 board. The PC program was created using LabVIEW.The logical and functional tests of the system have been carried out. The application of a programmable device enables its quick configuration according to the requirements set by the user.The main advantage of FPGA is the option to expand to following modules, such as the incremental encoder support module, PWM, FOC etc. In these applications, the advantage of the programmable system becomes visible, which due to its specifics, is built for parallel processing or generating signals.
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Naresh, M. "Modelling and Analysis of Microcontroller Based MPPT Method Using FPGA". Scientific Bulletin of Naval Academy XIV, nr 2 (15.12.2021): 167–76. http://dx.doi.org/10.21279/1454-864x-21-i2-017.
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Now days, the renewable energy sources (RES) are the most accomplished system for power generation. In this paper, focus on FPGA based digital controller for the grid connected DG system. The study and performance analysis of grid-connected PV system as follows to improve the efficiency of the grid system and to extract the maximum power. This work is designed & development of FPGA. The DC power and battery capture on the DC bus system we have maintained the unity power factor and harmonics current in the DG system. The bi-directional battery systems also provide quick response & the performance under the variable DC voltage. Then, to develop the effectiveness control strategy is to manage the power flow equally AC & DC sides. This system simulated in MTTLAB Tools and FPGA System.
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Więcek, Bogusław, i Sebastian Urbaś. "Development of Low-Resolution, Low-Power and Low-Cost Infrared System". Pomiary Automatyka Robotyka 25, nr 2 (30.06.2021): 47–52. http://dx.doi.org/10.14313/par_240/47.
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The article presents the construction of a thermal imaging camera with low power consumption. The 80 × 80 Micro80Gen2 microbolometric array of detectors records infrared radiation in the LWIR spectral range (long infrared wave, 8–12 µm). The entire digital part of the electronic circuit has been integrated within the reprogrammable FPGA chip from the Spartan 6 family. In order to read and display thermograms, an application for the .NetFremework 3.1 platform, which implements non-uniformity correction (NUC) and image processing, is written. Due to its low cost, small size and weight, the camera can be used in various applications, e.g. in unmanned aerial vehicles (UAV) known as drones.
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Ohkawa, Takeshi, Daichi Uetake, Takashi Yokota i Kanemitsu Ootsu. "Component-Based FPGA Circuit Design and Verification for Robotic Systems Using JavaRock and ORB Engine - A Case Study". Applied Mechanics and Materials 433-435 (październik 2013): 1849–52. http://dx.doi.org/10.4028/www.scientific.net/amm.433-435.1849.
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In order to improve flexibility and productivity of designing complex robot systems which consists of a number of sensors, actuators and processors for control, component-based design methodology is a key issue. Meanwhile, an FPGA (Field Programmable Gate Array) is a potential candidate for controlling real-time system like a robot, because it can achieve shorter response time and higher performance-power efficiency by its parallel processing of hardwired digital circuits. However, it is difficult to introduce an FPGA for robot systems because designing an FPGA requires implementation of the user application into a circuit using HDL (Hardware Description Language). In this paper, design and verification flow using a Java-to-HDL synthesizer (JavaRock) and a distributed object environment (ORB Engine) is proposed. A case study of designing an inverted pendulum robot system is described, which achieves below 10 us processing time for controlling the inverted pendulum system successfully within a small FPGA chip in battery operation.
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Caba, Julián, María Díaz, Jesús Barba, Raúl Guerra i Jose A. de la Torre and Sebastián López. "FPGA-Based On-Board Hyperspectral Imaging Compression: Benchmarking Performance and Energy Efficiency against GPU Implementations". Remote Sensing 12, nr 22 (13.11.2020): 3741. http://dx.doi.org/10.3390/rs12223741.
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Remote-sensing platforms, such as Unmanned Aerial Vehicles, are characterized by limited power budget and low-bandwidth downlinks. Therefore, handling hyperspectral data in this context can jeopardize the operational time of the system. FPGAs have been traditionally regarded as the most power-efficient computing platforms. However, there is little experimental evidence to support this claim, which is especially critical since the actual behavior of the solutions based on reconfigurable technology is highly dependent on the type of application. In this work, a highly optimized implementation of an FPGA accelerator of the novel HyperLCA algorithm has been developed and thoughtfully analyzed in terms of performance and power efficiency. In this regard, a modification of the aforementioned lossy compression solution has also been proposed to be efficiently executed into FPGA devices using fixed-point arithmetic. Single and multi-core versions of the reconfigurable computing platforms are compared with three GPU-based implementations of the algorithm on as many NVIDIA computing boards: Jetson Nano, Jetson TX2 and Jetson Xavier NX. Results show that the single-core version of our FPGA-based solution fulfils the real-time requirements of a real-life hyperspectral application using a mid-range Xilinx Zynq-7000 SoC chip (XC7Z020-CLG484). Performance levels of the custom hardware accelerator are above the figures obtained by the Jetson Nano and TX2 boards, and power efficiency is higher for smaller sizes of the image block to be processed. To close the performance gap between our proposal and the Jetson Xavier NX, a multi-core version is proposed. The results demonstrate that a solution based on the use of various instances of the FPGA hardware compressor core achieves similar levels of performance than the state-of-the-art GPU, with better efficiency in terms of processed frames by watt.
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Cheng, Zhihai, i Hui Liu. "Application of space vector pulse width modulation algorithm based on programmable logic array in power system". Journal of Physics: Conference Series 2108, nr 1 (1.11.2021): 012003. http://dx.doi.org/10.1088/1742-6596/2108/1/012003.
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Abstract In the traditional power system, the voltage regulation and frequency modulation control method used for boiler induced draft fan is limited in control accuracy. With the improvement of furnace pressure change accuracy, higher requirements are put forward for motor control algorithm. This paper studies permanent magnet synchronous motor (PMSM) as the executive part of induced draft fan servo control system, and adopts FOC control method based on space vector pulse width modulation (SVPWM). Firstly, the simulation model of SVPWM pulse width modulation algorithm is established by MATLAB to provide theoretical support for the subsequent debugging algorithm; When using FPGA to realize SVPWM modulation algorithm, FPGA has the advantages of high reliability and high real-time processing, which provides theoretical support and application guidance for the realization of high-precision motor control of boiler induced draft fan in power system.
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Liu, Hailiang, Jiade Cheng i Asnidar Hanim Yusuf. "Design of Light Emitting Diodes (LEDs) Lighting System and Its Application in Garden Landscape Decoration". Journal of Nanoelectronics and Optoelectronics 15, nr 6 (1.06.2020): 734–42. http://dx.doi.org/10.1166/jno.2020.2793.
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Light Emitting Diode (LED) is widely used in garden landscape decoration because of its small size, low power, concentrated light, and the capability of showing more vivid colors. While designing the LED lighting system, considering that a single Advanced RISC Machine (ARM)-based control system cannot achieve large-scale LED display, and a single Field Programmable Gate Array (FPGA)-based control system cannot control the lighting system well, an LED system with the combination of ARM processor-FPGA is proposed. In this system, the ARM processor is used as the major control component. The Linux system realizes remote monitoring and intelligent management of image data. In addition, FPGA is used for LED data output. The lighting system consists of a major control node and a lighting node. The nodes are connected in parallel through a chain network. The major control node uses an ARM Cortex processor and is equipped with a Linux operating system. The lighting node uses ARM + FPGA hardware architecture. During the experiments, the LED lighting system is tested first. The results show that the reading and writing speed is fast. The LED display screen meets the lighting requirements. This LED lighting system is used for night lighting of garden landscapes. During the brightness test, the brightness of lighting objects and the background is used as research objects. Experiments have proved that the ratio of the lighting object brightness to the background brightness between (Yu, M. and Li, X., 2012. A little current k-factor method for measuring junction temperature of aviation lighting power led. Guangxue Jishu/Optical Technique, 38(3), pp.371–375; Monas, A., Verma, A., Gawari, A. and Paswan, R. S., 2016. Portable network monitor using arm processor. Procedia Computer Science, 92, pp.493–497.) is suitable for night lighting of garden landscape decoration, which will not bring discomfort to people who enjoy night scenery.
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Dorothy, R., i Sasilatha T. "System on Chip Based RTC in Power Electronics". Bulletin of Electrical Engineering and Informatics 6, nr 4 (1.12.2017): 358–63. http://dx.doi.org/10.11591/eei.v6i4.867.
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Current control systems and emulation systems (Hardware-in-the-Loop, HIL or Processor-in-the-Loop, PIL) for high-end power-electronic applications often consist of numerous components and interlinking busses: a micro controller for communication and high level control, a DSP for real-time control, an FPGA section for fast parallel actions and data acquisition, multiport RAM structures or bus systems as interconnecting structure. System-on-Chip (SoC) combines many of these functions on a single die. This gives the advantage of space reduction combined with cost reduction and very fast internal communication. Such systems become very relevant for research and also for industrial applications. The SoC used here as an example combines a Dual-Core ARM 9 hard processor system (HPS) and an FPGA, including fast interlinks between these components. SoC systems require careful software and firmware concepts to provide real-time control and emulation capability. This paper demonstrates an optimal way to use the resources of the SoC and discusses challenges caused by the internal structure of SoC. The key idea is to use asymmetric multiprocessing: One core uses a bare-metal operating system for hard real time. The other core runs a “real-time” Linux for service functions and communication. The FPGA is used for flexible process-oriented interfaces (A/D, D/A, switching signals), quasi-hard-wired protection and the precise timing of the real-time control cycle. This way of implementation is generally known and sometimes even suggested–but to the knowledge of the author’s seldomly implemented and documented in the context of demanding real-time control or emulation. The paper details the way of implementation, including process interfaces, and discusses the advantages and disadvantages of the chosen concept. Measurement results demonstrate the properties of the solution.
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Kong, Qing Chen, Guang Can Zhang i Yong Xin Li. "Research on the Development of Large Application Specific Integrated Circuit Based on SOPC". Advanced Materials Research 328-330 (wrzesień 2011): 1663–66. http://dx.doi.org/10.4028/www.scientific.net/amr.328-330.1663.
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This paper introduces a design of ASIC with the advantages of high performance, low power, low cost and short development cycle, which is especially suitable for the middle and small scale production of complicated large programmable ASIC. Through introducing the performance and latest development of HardCopy series devices and Stratix FPGA series devices, and based on the development platform of Quartus II and Nios II system, this paper analyzes the complete development process of Stratix FPGA and HardCopy ASIC based on SOPC. This paper concludes the seamless transplant from Stratix FPGA to HardCopy ASIC based on the SOPC with IP multiplexing, which is the most promising development direction of producing large programmable ASIC with high performance and low cost in the future.
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Pei, Yu Jie, Yun Shan Zhang, Jian Guo Xu, Jing Long Mu, Lei Zhang, Pin Dong, Bo Cong i Shu Han Wang. "Implementation of Single Phase Locked Loop Based on FPGA and its Application in SVC". Advanced Materials Research 986-987 (lipiec 2014): 1826–32. http://dx.doi.org/10.4028/www.scientific.net/amr.986-987.1826.
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Whereas three-phase phase locked loop could not get accurate phase position under three-phase unbalanced condition of the power grid, the design of single phase locked loop is implemented in the principle of single phase locked loop, based on FPGA technology. the paper explains design difficulties of single phase locked loop in detail, puts forward adaptive sampling scheme using single phase locked loop under variable frequency, increases accuracy of SVC sampling system. And tests response speed of phase locked loop via Real Time Digital Simulator for Power Systems (RTDS), through final verification in Fushun Lishizhai SVC Project, the design could meet system requirement for voltage phase accuracy.
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Li, Hui Rong, Li Juan Pang, Xue Feng Zhang, Gang Deng i Yan Wei Tong. "The Application of FPGA and DSP Techniques in Intelligent Wattmeter". Advanced Materials Research 201-203 (luty 2011): 2096–100. http://dx.doi.org/10.4028/www.scientific.net/amr.201-203.2096.
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According to the demand of data acquisition in power system, the intelligent wattmeter is constructed, which is based on DSP and FPGA as the data acquisition and processing system, meanwhile, the administration center of the intelligent wattmeter is based on single-chip computer 8051. With these, high speed, multi-point sampling, a large quantity accumulation and real-time calculation are realized. At the same time it reduces the effect of the measuring accuracy upon higher harmonic and the measuring accuracy could reach to 0.02 grade.
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Zhang, Yue, i Linwei Tao. "Multi-Channel Data Acquisition System Based on FPGA and STM32". Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 38, nr 2 (kwiecień 2020): 351–58. http://dx.doi.org/10.1051/jnwpu/20203820351.
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In order to realize the acquisition and storage of underwater acoustic signals for aiming at the requirements of multi-channel, low power consumption and small volume for underwater receiver extension of sonar system, a multi-channel signal acquisition and storage system based on FPGA and STM32 with variable number of working channels and sampling frequency is designed, in which the system is consisted of 8 pieces, 8 channel and 24 bits high dynamic range Δ-Σ ADS1278 ADC chip to synchronous multi-channel analog signal acquisition. FPGA, as the acquisition sequence and logic control, reads and collates the ADC chip data and writes it into the internal high-capacity FIFO, and adds corresponding operations according to the characteristics of FIFO in an application. SMT32 single-chip microcomputer reads the FIFO data through the high-speed SPI interface with FPGA and writes the multi-channel data into the high-capacity SD card. The testing results have verified that the system has characteristics such as stable and reliable, easy configuration, low power consumption, can guarantee the multichannel data serial transmission, storage, accurate, up to 64 analog signals at the same time the real-time collection and storage, top 20 kHz sampling rate, the system total power of the system of about 3W, data rates up to 100 Mb/s, fully meet the needs of underwater sound acquisition system.
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Grout, Ian, i Lenore Mullin. "Hardware Considerations for Tensor Implementation and Analysis Using the Field Programmable Gate Array". Electronics 7, nr 11 (13.11.2018): 320. http://dx.doi.org/10.3390/electronics7110320.
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In today’s complex embedded systems targeting internet of things (IoT) applications, there is a greater need for embedded digital signal processing algorithms that can effectively and efficiently process complex data sets. A typical application considered is for use in supervised and unsupervised machine learning systems. With the move towards lower power, portable, and embedded hardware-software platforms that meet the current and future needs for such applications, there is a requirement on the design and development communities to consider different approaches to design realization and implementation. Typical approaches are based on software programmed processors that run the required algorithms on a software operating system. Whilst such approaches are well supported, they can lead to solutions that are not necessarily optimized for a particular problem. A consideration of different approaches to realize a working system is therefore required, and hardware based designs rather than software based designs can provide performance benefits in terms of power consumption and processing speed. In this paper, consideration is given to utilizing the field programmable gate array (FPGA) to implement a combined inner and outer product algorithm in hardware that utilizes the available hardware resources within the FPGA. These products form the basis of tensor analysis operations that underlie the data processing algorithms in many machine learning systems.
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Akkar, Hanan A. R., i Sameh J. Mohammed. "Artificial Intelligent Technique for Power Management Lighting Based on FPGA". Engineering and Technology Journal 38, nr 2A (25.02.2020): 232–39. http://dx.doi.org/10.30684/etj.v38i2a.305.
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The modern technological advances gave rise to new intelligent ways of performance and management in various fields of our lives. The employment of the artificial intelligent techniques proved influential in enhancing the technological developments and in meeting the demands for new, more efficient, more reliable and faster ways of performing activities and tasks. Lighting systems are an important part of human life. For this reason, it is important to reduce and manage energy consumption properly. Light dimming paves the way for massive energy saving in lighting applications. The options include simply reducing the output during the night and achieve maximum saving with variable dimming. Advantage can be taken of off-peak times (no light needed) to reduce energy consumption significantly. Pulse Width Modulation (PWM) technique is used as dimming method. The proposed system offers intelligent management of lighting to reduce power consumption, extend lamp life and reduce maintenance. In this work, we will be using multiple sensors such as light dependent resistor (LDR) and Motion Sensor (PIR) for LED dimming system to achieve intelligent LED lighting system to manage energy consumption. The data collected by sensors is processed by Artificial Neural Network (ANN), which is implemented by using Field Programmable Gate Arrays (FPGAs), Spartan 3A starter kit that controls the light intensity of LED from changing the duty cycle of the PWM signals. FPGA was used to implement the design, because of the re-programmability of the FPGAs, which can support the re-configuration necessary to implement the design.
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Ma, Dezhuang, i Lunhui Deng. "Research on data transmission application based on USB3.0 bridge chip and FPGA". MATEC Web of Conferences 189 (2018): 04002. http://dx.doi.org/10.1051/matecconf/201818904002.
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Aiming at the shortcomings of data transmission system, such as poor portability, unstable data transmission and high cost, the combination of FPGA and USB3.0 technology is adopted to realize the real-time and reliable access to the host computer platform. Practical application shows that this platform has the advantages of small size, low power consumption, hot plug, etc. And the system meets the design requirements.
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Shieh, Cheng Shion. "From Simulation to FPGA Control Circuit Implementation for Wind Power with Battery Charging". Advanced Materials Research 588-589 (listopad 2012): 777–80. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.777.
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While application of field-programmable gate array (FPGA) chip has been extensively investigated, the charging control is relatively unexplored. This paper proposes a flow chart of energy storage for wind power system with Lead-Acid battery whose charging control is constructed by Very High Speed Integrated Circuit Hardware Description Language (VHDL) code. This research focuses on the proposed digital control algorithm can be directly downloaded into field-programmable gate array (FPGA) chip after simulation finishing. This saves greatly time on hardware circuit design. A simulation is presented to illustrate the effectiveness of the proposed charging flow chart.
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Abbes, Hanen, Hafedh Abid, Kais Loukil, Mohamed Abid i Ahmad Toumi. "Fuzzy-based MPPT algorithm implementation on FPGA chip for multi-channel photovoltaic system". International Journal of Reconfigurable and Embedded Systems (IJRES) 11, nr 1 (1.03.2022): 49. http://dx.doi.org/10.11591/ijres.v11.i1.pp49-58.
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<span lang="EN-US">Microprocessors and microcontrollers are mostly used to control electrical systems. These chips front into problems while monitoring systems that need heavy computing and important processing. Likewise, they fail while handling inputs and outputs speeds, especially with multi-channel photovoltaic (PV) systems. In comparison to a digital signal processor (DSP) and microcontroller implementations, field programmable gate array (FPGA) device is able to integrate a great number of PV channels and to achieve short development time, cost less and more flexible operation. As well, new control algorithms are increasingly complex; using new performing technologies is very motivating. Mainly, FPGA technology is adopted thanks to its ability to control complex applications and intelligent laws. In opposition to traditional controls, fuzzy logic based control presents more efficiency and reliability response for non-linear systems. Therefore, this paper deals with the execution of the fuzzy-based maximum power point tracking (MPPT) technique by the means of the FPGA chip for a multi-channel photovoltaic system. A multi-channel photovoltaic system is designed. Then, the FPGA circuit is investigated to get benefits from this hardware solution. Since software implementation way integrates a limited number of PV panels, hardware implementation is a promising solution that reduces execution time and therefore controls a huge number of photovoltaic channels. Finally, results of simulation of the fuzzy technique implementation on FPGA chip show that the proposed PV system controls more than 4400 channels. Therefore, the system output power is increased and the system profitability is improved.</span>
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Yu, Fei, Zhao Jie, Jing Xia Wang i Liu Li. "Design of on Line Car Battery Monitor System Base on FPGA". Advanced Materials Research 741 (sierpień 2013): 104–7. http://dx.doi.org/10.4028/www.scientific.net/amr.741.104.
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For the reason of high failure rate of car battery and car electric generator, an on line car battery monitor base on Altera FPGA/CPLD chip MAX serials was realized, which combining with the AD collection and power handling technology. The equipment can monitor the voltage, quantity, current leakage of the battery and the electric generator failure. It can make judgment of battery performance and has a good application value.
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Cifredo-Chacón, María-Ángeles, Fernando Perez-Peña, Ángel Quirós-Olozábal i Juan-José González-de-la-Rosa. "Implementation of Processing Functions for Autonomous Power Quality Measurement Equipment: A Performance Evaluation of CPU and FPGA-Based Embedded System". Energies 12, nr 5 (9.03.2019): 914. http://dx.doi.org/10.3390/en12050914.
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Motivated by the effects of deregulation over power quality and the subsequent need of new types of measurements, this paper assesses different implementations of an estimate for the spectral kurtosis, considered as a low-level harmonic detection. Performance of a processor-based system is compared with a field programmable gate array (FPGA)-based solution, in order to evaluate the accuracy of this processing function for implementation in autonomous measurement equipment. The fourth-order spectrum, with applications in different fields, needs advanced digital signal processing, making it necessary to compare implementation alternatives. In order to obtain reproducible results, the implementations have been developed using common design and programming tools. Several characteristics of the implementations are compared, showing that the increasing complexity and reduced cost of the current FPGA models make the implementation of complex mathematical functions feasible. We show that FPGAs improve the processing capability of the best processor using an operating frequency 33 times lower. This fact strongly supports its implementation in hand-held instruments.
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Luo, Wenhui, Qingli Ou, Fei Yu, Li Cui i Jie Jin. "Analysis of a New Hidden Attractor Coupled Chaotic System and Application of Its Weak Signal Detection". Mathematical Problems in Engineering 2020 (23.12.2020): 1–15. http://dx.doi.org/10.1155/2020/8849283.
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In order to improve the complexity of the chaotic system and the accuracy of the weak signal detection, this paper propose a new hidden attractor coupled chaotic system and a corresponding weak signal detection system, which can be used to obtain the phase diagram of the proposed system using the fourth order of the Runge-Kutta method. The dynamic behavior of the chaotic system is analyzed through the bifurcation diagram, Lyapunov exponent, and power spectrum. The Lyapunov exponent is used to depict the basins of attraction for the system. After research, it is discovered that symmetry exists in the system. Comparative analysis has demonstrated that the system has higher detection accuracy and excellent antinoise performance. Finally, the circuit simulation and FPGA realization of the system indicated that the numerical simulation results are consistent with the FPGA implementation results, proving the theoretical analysis to be correct and the accuracy of the detection results.
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Sánchez, Diego F., Daniel M. Muñoz, Carlos H. Llanos i José M. Motta. "A Reconfigurable System Approach to the Direct Kinematics of a 5D.o.fRobotic Manipulator". International Journal of Reconfigurable Computing 2010 (2010): 1–10. http://dx.doi.org/10.1155/2010/727909.
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Hardware acceleration in high performance computer systems has a particular interest for many engineering and scientific applications in which a large number of arithmetic operations and transcendental functions must be computed. In this paper a hardware architecture for computing direct kinematics of robot manipulators with 5 degrees of freedom (5D.o.f) using floating-point arithmetic is presented for 32, 43, and 64 bit-width representations and it is implemented in Field Programmable Gate Arrays (FPGAs). The proposed architecture has been developed using several floating-point libraries for arithmetic and transcendental functions operators, allowing the designer to select (pre-synthesis) a suitable bit-width representation according to the accuracy and dynamic range, as well as the area, elapsed time and power consumption requirements of the application. Synthesis results demonstrate the effectiveness and high performance of the implemented cores on commercial FPGAs. Simulation results have been addressed in order to compute the Mean Square Error (MSE), using the Matlab as statistical estimator, validating the correct behavior of the implemented cores. Additionally, the processing time of the hardware architecture was compared with the same formulation implemented in software, using the PowerPC (FPGA embedded processor), demonstrating that the hardware architecture speeds-up by factor of 1298 the software implementation.
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Pacini, Tommaso, Emilio Rapuano, Gianmarco Dinelli i Luca Fanucci. "A Multi-Cache System for On-Chip Memory Optimization in FPGA-Based CNN Accelerators". Electronics 10, nr 20 (15.10.2021): 2514. http://dx.doi.org/10.3390/electronics10202514.
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In recent years, FPGAs have demonstrated remarkable performance and contained power consumption for the on-the-edge inference of Convolutional Neural Networks. One of the main challenges in implementing this class of algorithms on board an FPGA is resource management, especially with regard to memory. This work presents a multi-cache system that allows for noticeably shrinking the required on-chip memory with a negligible variation of timing performance and power consumption. The presented methods have been applied to the CloudScout CNN, which was developed to perform cloud detection directly on board the satellite, thus representing a relevant case study for on the edge applications. The system was validated and characterized on a Xilinx ZCU106 Evaluation Board. The result is a 64.48% memory saving if compared to an alternative hardware accelerator developed for the same algorithm, with comparable performance in terms of inference time and power consumption. The paper also presents a detailed analysis of the hardware accelerator power consumption, focusing on the impact of data transfer between the accelerator and the external memory. Further investigation shows that the proposed strategies allow the implementation of the accelerator on FPGAs with a smaller size, guaranteeing benefits in terms of power consumption and hardware costs. A broader evaluation about the applicability of the presented methods to other models demonstrates valuable results in terms of memory saving with respect to other works reported in the literature.
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Meitei, Huirem Bharat, i Manoj Kumar. "Implementation of a secure wireless communication system using true random number generator for internet of things". Indonesian Journal of Electrical Engineering and Computer Science 30, nr 2 (1.05.2023): 982. http://dx.doi.org/10.11591/ijeecs.v30.i2.pp982-992.
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This paper describes the design and implementation of an internet of thing (IoT)-based application that uses a true random number generator (TRNG) with an all digital phase locked loop (ADPLL) for secure wireless communication. Field programmable gate array (FPGA) boards were used on the transmitter and receiver sides and were interfaced with Esp8266 chips to wirelessly send and receive encrypted sensor data. The MQ-2 gas sensor and tracking sensor were connected to the FPGA board on the transmitter side, where data from the sensors was encrypted using the exclusive-OR (XOR) function and the TRNG architecture. The system can be controlled by users through a web browser served by the ThingSpeak cloud. The Artix-7 FPGA device is used to implement the proposed wireless communication system, for which design and synthesis were done using the Xilinx Vivado 2015.2 tool. The proposed system uses a low amount of power and is suitable for a standalone, highly secure TRNG-based IoT application. The National Institute of Standard and Testing (NIST SP 800-22) test showed that ADPLL with finite impulse response (FIR) filter-based TRNGs are better for encrypting IoT devices for secure wireless communication.
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Hu, Shun Ren, Ya Chen Gan, Ming Bao i Jing Wei Wang. "Based on FPGA Intelligent Physiological Parameters Acquisition". Applied Mechanics and Materials 344 (lipiec 2013): 107–10. http://dx.doi.org/10.4028/www.scientific.net/amm.344.107.
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For the physiological signal monitoring applications, as a micro-controller based on field programmable gate array (FPGA) physiological parameters intelligent acquisition system is given, which has the advantages of low cost, high speed, low power consumption. FPGA is responsible for the completion of pulse sensor, the temperature sensor, acceleration sensor data acquisition and serial output and so on. Focuses on the design ideas and architecture of the various subsystems of the whole system, gives the internal FPGA circuit diagram of the entire system. The whole system is easy to implement and has a very good promotional value.