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Artykuły w czasopismach na temat "Floating point"
Jorgensen, Alan A., Las Vegas, Connie R. Masters, Ratan K. Guha i Andrew C. Masters. "Bounded Floating Point: Identifying and Revealing Floating-Point Error". Advances in Science, Technology and Engineering Systems Journal 6, nr 1 (styczeń 2021): 519–31. http://dx.doi.org/10.25046/aj060157.
Pełny tekst źródłaM. Somasekhar, M. Somasekhar. "Floating Point Operations in PipeRench CGRA". International Journal of Scientific Research 1, nr 6 (1.06.2012): 67–68. http://dx.doi.org/10.15373/22778179/nov2012/24.
Pełny tekst źródłaBoldo, Sylvie, Claude-Pierre Jeannerod, Guillaume Melquiond i Jean-Michel Muller. "Floating-point arithmetic". Acta Numerica 32 (maj 2023): 203–90. http://dx.doi.org/10.1017/s0962492922000101.
Pełny tekst źródłaBlinn, J. F. "Floating-point tricks". IEEE Computer Graphics and Applications 17, nr 4 (1997): 80–84. http://dx.doi.org/10.1109/38.595279.
Pełny tekst źródłaGhosh, Aniruddha, Satrughna Singha i Amitabha Sinha. ""Floating point RNS"". ACM SIGARCH Computer Architecture News 40, nr 2 (31.05.2012): 39–43. http://dx.doi.org/10.1145/2234336.2234343.
Pełny tekst źródłaKavya, Nagireddy. "Design and Implementation of Floating-Point Addition and Floating-Point Multiplication". International Journal for Research in Applied Science and Engineering Technology 10, nr 1 (31.01.2022): 98–101. http://dx.doi.org/10.22214/ijraset.2022.39742.
Pełny tekst źródłaBaidas, Z., A. D. Brown i A. C. Williams. "Floating-point behavioral synthesis". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, nr 7 (lipiec 2001): 828–39. http://dx.doi.org/10.1109/43.931000.
Pełny tekst źródłaSayers, David, i du Croz Jeremy. "Validating floating-point systems". Physics World 2, nr 6 (czerwiec 1989): 59–62. http://dx.doi.org/10.1088/2058-7058/2/6/33.
Pełny tekst źródłaErle, Mark A., Brian J. Hickmann i Michael J. Schulte. "Decimal Floating-Point Multiplication". IEEE Transactions on Computers 58, nr 7 (lipiec 2009): 902–16. http://dx.doi.org/10.1109/tc.2008.218.
Pełny tekst źródłaNannarelli, Alberto. "Tunable Floating-Point Adder". IEEE Transactions on Computers 68, nr 10 (1.10.2019): 1553–60. http://dx.doi.org/10.1109/tc.2019.2906907.
Pełny tekst źródłaRozprawy doktorskie na temat "Floating point"
Skogstrøm, Kristian. "Implementation of Floating-point Coprocessor". Thesis, Norwegian University of Science and Technology, Department of Computer and Information Science, 2005. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9202.
Pełny tekst źródłaThis thesis presents the architecture and implementation of a high-performance floating-point coprocessor for Atmel's new microcontroller. The coprocessor architecture is based on a fused multiply-add pipeline developed in the specialization project, TDT4720. This pipeline has been optimized significantly and extended to support negation of all operands and single-precision input and output. New hardware has been designed for the decode/fetch unit, the register file, the compare/convert pipeline and the approximation tables. Division and square root is performed in software using Newton-Raphson iteration. The Verilog RTL implementation has been synthesized at 167 MHz using a 0.18 um standard cell library. The total area of the final implementation is 107 225 gates. The coprocessor has also been synthesized with the CPU. Test-programs have been run to verify that the coprocessor works correctly. A complete verification of the floating-point coprocessor, however, has not been performed due to limitations in time.
Zhang, Yiwei. "Biophysically accurate floating point neuroprocessors". Thesis, University of Bristol, 2011. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.544427.
Pełny tekst źródłaBaidas, Zaher Abdulkarim. "High-level floating-point synthesis". Thesis, University of Southampton, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.325049.
Pełny tekst źródłaDuracz, Jan Andrzej. "Verification of floating point programs". Thesis, Aston University, 2010. http://publications.aston.ac.uk/15778/.
Pełny tekst źródłaRoss, Johan, i Hans Engström. "Voice Codec for Floating Point Processor". Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15763.
Pełny tekst źródłaAs part of an ongoing project at the department of electrical engineering, ISY, at Linköping University, a voice decoder using floating point formats has been the focus of this master thesis. Previous work has been done developing an mp3-decoder using the floating point formats. All is expected to be implemented on a single DSP.The ever present desire to make things smaller, more efficient and less power consuming are the main reasons for this master thesis regarding the use of a floating point format instead of the traditional integer format in a GSM codec. The idea with the low precision floating point format is to be able to reduce the size of the memory. This in turn reduces the size of the total chip area needed and also decreases the power consumption.One main question is if this can be done with the floating point format without losing too much sound quality of the speech. When using the integer format, one can represent every value in the range depending on how many bits are being used. When using a floating point format you can represent larger values using fewer bits compared to the integer format but you lose representation of some values and have to round the values off.From the tests that have been made with the decoder during this thesis, it has been found that the audible difference between the two formats is very small and can hardly be heard, if at all. The rounding seems to have very little effect on the quality of the sound and the implementation of the codec has succeeded in reproducing similar sound quality to the GSM standard decoder.
Englund, Madeleine. "Hybrid Floating-point Units in FPGAs". Thesis, Linköpings universitet, Datorteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-86587.
Pełny tekst źródłaXiao, Yancheng. "Two floating point LLL reduction algorithms". Thesis, McGill University, 2013. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=114503.
Pełny tekst źródłaLe Lenstra, Lenstra et réduction Lovasz (LLL) est la réduction de réseaux plus populaire et il est un outil puissant pour résoudre de nombreux problèmes complexes en mathématiques et en informatique. La technique bloc LLL bloquante reformule les algorithmes en termes de matrice-matrice opérations de permettre la réutilisation efficace des données dans les algorithmes bloc LLL. Dans cette thèse, nous utilisons la technique de blocage de développer les deux algorithmes de réduction bloc LLL en points flottants, l'algorithme de réduction bloc LLL de la gauche vers la droite (LRBLLL) et l'algorithme de réduction bloc LLL en partition alternative (APBLLL), et donner a l'analyse de la complexité des ces deux algorithmes. Nous comparons ces deux algorithmes de réduction bloc LLL avec l'algorithme de réduction LLL original (en arithmétique au point flottant) et l'algorithme de réduction LLL partielle (PLLL) dans la littérature en termes de temps d'exécution CPU, flops et les erreurs de l'arrière par rapport. Les résultats des simulations montrent que les temps d'exécution CPU pour les deux algorithmes de réduction blocs LLL sont plus rapides que l'algorithme de réduction LLL partielle et beaucoup plus rapide que la réduction LLL originale, même si les deux algorithmes par bloc coûtent plus de flops que l'algorithme de réduction LLL partielle dans certains cas. L'inconvénient de ces deux algorithmes par blocs, c'est que parfois, ils peuvent n'être pas aussi stable numériquement que les algorithmes originaux et les algorithmes de réduction LLL partielle. Le parallélisation de APBLLL est discutée.
Kupriianova, Olga. "Towards a modern floating-point environment". Thesis, Paris 6, 2015. http://www.theses.fr/2015PA066584/document.
Pełny tekst źródłaThis work investigates two ways of enlarging the current floating-point environment. The first is to support several implementation versions of each mathematical function (elementary such as $\exp$ or $\log$ and special such as $\erf$ or $\Gamma$), the second one is to provide IEEE754 operations that mix the inputs and the output of different \radixes. As the number of various implementations for each mathematical function is large, this work is focused on code generation. Our code generator supports the huge variety of functions: it generates parametrized implementations for the user-specified functions. So it may be considered as a black-box function generator. This work contains a novel algorithm for domain splitting and an approach to replace branching on reconstruction by a polynomial. This new domain splitting algorithm produces less subdomains and the polynomial degrees on adjacent subdomains do not change much. To produce vectorizable implementations, if-else statements on the reconstruction step have to be avoided. Since the revision of the IEEE754 Standard in 2008 it is possible to mix numbers of different precisions in one operation. However, there is no mechanism that allows users to mix numbers of different radices in one operation. This research starts an examination ofmixed-radix arithmetic with the worst cases search for FMA. A novel algorithm to convert a decimal character sequence of arbitrary length to a binary floating-point number is presented. It is independent of currently-set rounding mode and produces correctly-rounded results
Kupriianova, Olga. "Towards a modern floating-point environment". Electronic Thesis or Diss., Paris 6, 2015. http://www.theses.fr/2015PA066584.
Pełny tekst źródłaThis work investigates two ways of enlarging the current floating-point environment. The first is to support several implementation versions of each mathematical function (elementary such as exp or log and special such as erf or Γ), the second one is to provide IEEE754 operations that mix the inputs and the output of different radixes. As the number of various implementations for each mathematical function is large, this work is focused on code generation. Our code generator supports the huge variety of functions: it generates parametrized implementations for the user-specified functions. So it may be considered as a black-box function generator. This work contains a novel algorithm for domain splitting and an approach to replace branching on reconstruction by a polynomial. This new domain splitting algorithm produces less subdomains and the polynomial degrees on adjacent subdomains do not change much. To produce vectorizable implementations, if-else statements on the reconstruction step have to be avoided. Since the revision of the IEEE754 Standard in 2008 it is possible to mix numbers of different precisions in one operation. However, there is no mechanism that allows users to mix numbers of different radices in one operation. This research starts an examination ofmixed-radix arithmetic with the worst cases search for FMA. A novel algorithm to convert a decimal character sequence of arbitrary length to a binary floating-point number is presented. It is independent of currently-set rounding mode and produces correctly-rounded results
Aamodt, Tor. "Floating-point to fixed-point compilation and embedded architectural support". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ58787.pdf.
Pełny tekst źródłaKsiążki na temat "Floating point"
L, Wallis Peter J., red. Improving floating-point programming. Chichester, England: Wiley, 1990.
Znajdź pełny tekst źródłaMuller, Jean-Michel, Nicolas Brunie, Florent de Dinechin, Claude-Pierre Jeannerod, Mioara Joldes, Vincent Lefèvre, Guillaume Melquiond, Nathalie Revol i Serge Torres. Handbook of Floating-Point Arithmetic. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-76526-6.
Pełny tekst źródłaMuller, Jean-Michel, Nicolas Brisebarre, Florent de Dinechin, Claude-Pierre Jeannerod, Vincent Lefèvre, Guillaume Melquiond, Nathalie Revol, Damien Stehlé i Serge Torres. Handbook of Floating-Point Arithmetic. Boston: Birkhäuser Boston, 2010. http://dx.doi.org/10.1007/978-0-8176-4705-6.
Pełny tekst źródłaservice), SpringerLink (Online, red. Handbook of floating-point arithmetic. Boston: Birkhäuser, 2010.
Znajdź pełny tekst źródłaVekaria, R. Bandpass filters using floating point arithmtic. London: University of East London, 1994.
Znajdź pełny tekst źródłaAamodt, Tor. Floating-point to fixed-point compilation and embedded architectural support. Ottawa: National Library of Canada, 2001.
Znajdź pełny tekst źródłaRussinoff, David M. Formal Verification of Floating-Point Hardware Design. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-87181-9.
Pełny tekst źródłaRussinoff, David M. Formal Verification of Floating-Point Hardware Design. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-95513-1.
Pełny tekst źródłaMotorola. MC68881/MC68882 floating-point coprocessor user's manual. Wyd. 2. Englewood Cliffs, N.J: Prentice Hall, 1989.
Znajdź pełny tekst źródłaIEEE Computer Society. Standards Committee. Working group of the Microprocessor Standards Subcommittee. i American National Standards Institute, red. IEEE standard for binary floating-point arithmetic. New York, N.Y: Institute of Electrical and Electronics Engineers, Inc, 1985.
Znajdź pełny tekst źródłaCzęści książek na temat "Floating point"
Kneusel, Ronald T. "Floating Point". W Numbers and Computers, 75–111. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-17260-6_3.
Pełny tekst źródłaKneusel, Ronald T. "Floating Point". W Numbers and Computers, 81–115. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-50508-4_3.
Pełny tekst źródłaLloris Ruiz, Antonio, Encarnación Castillo Morales, Luis Parrilla Roure, Antonio García Ríos i María José Lloris Meseguer. "Floating Point". W Arithmetic and Algebraic Circuits, 173–220. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-67266-9_4.
Pełny tekst źródłaStoyan, Gisbert, i Agnes Baran. "Floating Point Arithmetic". W Compact Textbooks in Mathematics, 1–14. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-44660-8_1.
Pełny tekst źródłaKormanyos, Christopher. "Floating-Point Mathematics". W Real-Time C++, 213–39. Berlin, Heidelberg: Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-47810-3_12.
Pełny tekst źródłaDeschamps, Jean-Pierre, Gustavo D. Sutter i Enrique Cantó. "Floating Point Arithmetic". W Lecture Notes in Electrical Engineering, 305–36. Dordrecht: Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-94-007-2987-2_12.
Pełny tekst źródłaVan Hoey, Jo. "Floating-Point Arithmetic". W Beginning x64 Assembly Programming, 95–100. Berkeley, CA: Apress, 2019. http://dx.doi.org/10.1007/978-1-4842-5076-1_11.
Pełny tekst źródłaSmith, Stephen. "Floating-Point Operations". W Raspberry Pi Assembly Language Programming, 211–32. Berkeley, CA: Apress, 2019. http://dx.doi.org/10.1007/978-1-4842-5287-1_11.
Pełny tekst źródłaSmith, Stephen. "Floating-Point Operations". W Programming with 64-Bit ARM Assembly Language, 269–89. Berkeley, CA: Apress, 2020. http://dx.doi.org/10.1007/978-1-4842-5881-1_12.
Pełny tekst źródłaMihailescu, Marius Iulian, i Stefania Loredana Nita. "Floating-Point Arithmetic". W Pro Cryptography and Cryptanalysis, 109–32. Berkeley, CA: Apress, 2020. http://dx.doi.org/10.1007/978-1-4842-6367-9_4.
Pełny tekst źródłaStreszczenia konferencji na temat "Floating point"
Zaki, Ahmad M., Mohamed H. El-Shafey, Ayman M. Bahaa-Eldin i Gamal M. Aly. "Accurate floating-point operation using controlled floating-point precision". W 2011 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PacRim). IEEE, 2011. http://dx.doi.org/10.1109/pacrim.2011.6032978.
Pełny tekst źródłaGemini, Vipin. "Reconfigurable floating point adder". W 2014 1st International Conference on Information Technology, Computer and Electrical Engineering (ICITACEE). IEEE, 2014. http://dx.doi.org/10.1109/icitacee.2014.7065719.
Pełny tekst źródłaCollins, George E., i Werner Krandick. "Multiprecision floating point addition". W the 2000 international symposium. New York, New York, USA: ACM Press, 2000. http://dx.doi.org/10.1145/345542.345585.
Pełny tekst źródłaFandrianto, Jan, i B. Y. Woo. "VLSI floating-point processors". W 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH). IEEE, 1985. http://dx.doi.org/10.1109/arith.1985.6158947.
Pełny tekst źródłaHan, Kyungtae, Alex G. Olson i Brian L. Evans. "Automatic Floating-Point to Fixed-Point Transformations". W 2006 Fortieth Asilomar Conference on Signals, Systems and Computers. IEEE, 2006. http://dx.doi.org/10.1109/acssc.2006.356588.
Pełny tekst źródłaMarynets, K. "Study of the Antarctic Circumpolar Current via the Shallow Water Large Scale Modelling". W Floating Offshore Energy Devices. Materials Research Forum LLC, 2022. http://dx.doi.org/10.21741/9781644901731-11.
Pełny tekst źródłaRao, R. Prakash, N. Dhanunjaya Rao, K. Naveen i P. Ramya. "IMPLEMENTATION OF THE STANDARD FLOATING POINT MAC USING IEEE 754 FLOATING POINT ADDER". W 2018 Second International Conference on Computing Methodologies and Communication (ICCMC). IEEE, 2018. http://dx.doi.org/10.1109/iccmc.2018.8487626.
Pełny tekst źródłaLam, Michael O., i Barry L. Rountree. "Floating-Point Shadow Value Analysis". W 2016 5th Workshop on Extreme-Scale Programming Tools (ESPT). IEEE, 2016. http://dx.doi.org/10.1109/espt.2016.007.
Pełny tekst źródłaSheikh, Basit Riaz, i Rajit Manohar. "An Asynchronous Floating-Point Multiplier". W 2012 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE, 2012. http://dx.doi.org/10.1109/async.2012.19.
Pełny tekst źródłaAarnio, Tomi, Claudio Brunelli i Timo Viitanen. "Efficient floating-point texture decompression". W 2010 International Symposium on System-on-Chip - SOC. IEEE, 2010. http://dx.doi.org/10.1109/issoc.2010.5625555.
Pełny tekst źródłaRaporty organizacyjne na temat "Floating point"
Chen, Yirng-An, i Randal E. Bryant. Verification of Floating-Point Adders. Fort Belvoir, VA: Defense Technical Information Center, kwiecień 1997. http://dx.doi.org/10.21236/ada346061.
Pełny tekst źródłaKahan, W. Rational Arithmetic in Floating-Point. Fort Belvoir, VA: Defense Technical Information Center, wrzesień 1986. http://dx.doi.org/10.21236/ada175190.
Pełny tekst źródłaDally, William J. Micro-Optimization of Floating-Point Operations. Fort Belvoir, VA: Defense Technical Information Center, sierpień 1988. http://dx.doi.org/10.21236/ada202001.
Pełny tekst źródłaHauser, John R. Handling Floating-point Exceptions in Numeric Programs. Fort Belvoir, VA: Defense Technical Information Center, marzec 1995. http://dx.doi.org/10.21236/ada637041.
Pełny tekst źródłaKong, Soonho, Sicun Gao i Edmund M. Clarke. Floating-point Bugs in Embedded GNU C Library. Fort Belvoir, VA: Defense Technical Information Center, listopad 2013. http://dx.doi.org/10.21236/ada600185.
Pełny tekst źródłaJensen, Debby. Control Implementation for the SPUR Floating Point Coprocessor. Fort Belvoir, VA: Defense Technical Information Center, sierpień 1987. http://dx.doi.org/10.21236/ada604004.
Pełny tekst źródłaPresuhn, R. Textual Conventions for the Representation of Floating-Point Numbers. RFC Editor, sierpień 2011. http://dx.doi.org/10.17487/rfc6340.
Pełny tekst źródłaChen, Yirng-An, i Randal E. Bryant. PBHD: An Efficient Graph Representation for Floating Point Circuit Verification,. Fort Belvoir, VA: Defense Technical Information Center, maj 1997. http://dx.doi.org/10.21236/ada327995.
Pełny tekst źródłaNagayama, Shinobu, Tsuotomu Sasao i Jon T. Butler. Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs. Fort Belvoir, VA: Defense Technical Information Center, maj 2010. http://dx.doi.org/10.21236/ada547647.
Pełny tekst źródłaNash, J. G. VLSI (Very Large Scale Integration) Floating Point Chip Design Study. Fort Belvoir, VA: Defense Technical Information Center, listopad 1985. http://dx.doi.org/10.21236/ada164198.
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