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1
Chen, Tsuhan Vaidyanathan P. P. Vaidyanathan P. P. "Multidimensional multirate filters and filter banks : theory, design, and implementation /". Diss., Pasadena, Calif. : California Institute of Technology, 1993. http://resolver.caltech.edu/CaltechETD:etd-08232007-095226.
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Davati, Soheil. "VLSI implementation of recursive digital notch filter". Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183128831.
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Chen, Min. "Implementation and optimization of a modulated filter bank based on allpass filters". Thesis, University of Ottawa (Canada), 2001. http://hdl.handle.net/10393/9192.
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A filter bank based on an allpass IIR filter with brick-wall response was designed by A. J. Van Leest in [17]; however, the delay in the filter bank is too long to be used in real time applications. In order to reduce the delay, the orders of coefficients, transition bandwidth and filter bank structures must be optimized. The order of coefficients can be reduced by increasing the stopband attenuation. In order to further reduce the delay, the sharpness of the filter bank has to be reduced. This thesis also discussed the number of band and filter bank structure against to filter bank delay. The filter bank can be used in non-real time application such as CD compression with high order coefficient. The minimum transition bandwidth can be reached at 0.03257pi/number of band. This thesis expands upon DCT modulations of IIR based modulated filter banks and investigate the Hartley transformation in filter bank modulation as a new modulation technique. These modulation techniques generate the real output signal with real input signals. The quantization errors from quantizing the coefficient are studied. It is concluded that at least 16 bits are required in order for a filter bank to give a good performance as designed without quantization.
4
Gebart, Joakim. "GPU Implementation of the Particle Filter". Thesis, Linköpings universitet, Reglerteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-94190.
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This thesis work analyses the obstacles faced when adapting the particle filtering algorithm to run on massively parallel compute architectures. Graphics processing units are one example of massively parallel compute architectures which allow for the developer to distribute computational load over hundreds or thousands of processor cores. This thesis studies an implementation written for NVIDIA GeForce GPUs, yielding varying speed ups, up to 3000% in some cases, when compared to the equivalent algorithm performed on CPU. The particle filter, also known in the literature as sequential Monte-Carlo methods, is an algorithm used for signal processing when the system generating the signals has a highly nonlinear behaviour or non-Gaussian noise distributions where a Kalman filter and its extended variants are not effective. The particle filter was chosen as a good candidate for parallelisation because of its inherently parallel nature. There are, however, several steps of the classic formulation where computations are dependent on other computations in the same step which requires them to be run in sequence instead of in parallel. To avoid these difficulties alternative ways of computing the results must be used, such as parallel scan operations and scatter/gather methods. Another area where parallel programming still is not widespread is the area of pseudo-random number generation. Pseudo-random numbers are required by the algorithm to simulate the process noise as well as for avoiding the particle depletion problem using a resampling step. In this thesis a recently published counter-based pseudo-random number generator is used.
5
Ozkaya, Hasan. "Parallel Active Filter Design, Control, And Implementation". Master's thesis, METU, 2007. http://etd.lib.metu.edu.tr/upload/12608438/index.pdf.
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The parallel active filter (PAF) is the modern solution for harmonic current
mitigation and reactive power compensation of nonlinear loads. This thesis is
dedicated to detailed analysis, design, control, and implementation of a PAF for a 3-
phase 3-wire rectifier load. Specifically, the current regulator and switching ripple
filter (SRF) are thoroughly investigated. A novel discrete time hysteresis current
regulator with multi-rate current sampling and flexible PWM output, DHCR3, is
proposed. DHCR3 exhibits a high bandwidth while limiting the maximum switching
frequency for thermal stability and its implementation is simple. In addition to the
development of DHCR3, in the thesis state of the art current regulation methods are
considered and thoroughly compared with DHCR3. Since the current regulator type
determines the SRF topology choice, various SRF topologies are considered and a
thorough design study is conducted and SRF topology selection and parameter
determination methods are presented via numerical examples. Through a PAF
designed for a 10kW diode/thyristor rectifier load, the superior performance of
DHCR3 is verified through simulations and experiments and via comparison to other
current regulators. The sufficient switching ripple attenuation of the SRF structures
for the designed PAF system and the overall performance of the designed and built
PAF system are demonstrated via detailed computer simulations and laboratory
experiments. This thesis aids the PAF current regulator and SRF selection, design,
and implementation.
6
Dempster, Andrew. "Digital filter design for low-complexity implementation". Thesis, University of Cambridge, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.362967.
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Einarsson, Henrik. "Implementation and Performance Analysis of Filternets". Thesis, Linköping University, Department of Biomedical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5601.
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Nord, Magnus. "Cosine Modulated Filter Banks". Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1641.
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The initial goal of this report was to implement and compare cosine modulated filter banks. Because of time limitations, focus shifted towards the implementation. Filter banks and multirate systems are important in a vast range of signal processing systems. When implementing a design, there are several considerations to be taken into account. Some examples are word length, number systems and type of components. The filter banks were implemented using a custom made software, especially designed to generate configurable gate level code. The generated code was then synthesized and the results were compared. Some of the results were a bit curious. For example, considerable effort was put into implementing graph multipliers, as these were expected to be smaller and faster than their CSDC (Canonic Signed Digit Code) counterparts. However, with one exception, they turned out to generate larger designs. Another conclusion drawn is that the choice of FPGA is important. There are several things left to investigate, though. For example, a more thorough comparison between CSDC and graph multipliers should be carried out, and other DCT (Discrete Cosine Transform) implementations should be investigated.
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Alam, Syed Asad. "Techniques for Efficient Implementation of FIR and Particle Filtering". Doctoral thesis, Linköpings universitet, Datorteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-124195.
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FIR filters occupy a central place many signal processing applications which either alter the shape, frequency or the sampling frequency of the signal. FIR filters are used because of their stability and possibility to have linear-phase but require a high filter order to achieve the same magnitude specifications as compared to IIR filters. Depending on the size of the required transition bandwidth the filter order can range from tens to hundreds to even thousands. Since the implementation of the filters in digital domain requires multipliers and adders, high filter orders translate to a large number of these arithmetic units for its implementation. Research towards reducing the complexity of FIR filters has been going on for decades and the techniques used can be roughly divided into two categories; reduction in the number of multipliers and simplification of the multiplier implementation. One technique to reduce the number of multipliers is to use cascaded sub-filters with lower complexity to achieve the desired specification, known as FRM. One of the sub-filters is a upsampled model filter whose band edges are an integer multiple, termed as the period L, of the target filter's band edges. Other sub-filters may include complement and masking filters which filter different parts of the spectrum to achieve the desired response. From an implementation point-of-view, time-multiplexing is beneficial because generally the allowable maximum clock frequency supported by the current state-of-the-art semiconductor technology does not correspond to the application bound sample rate. A combination of these two techniques plays a significant role towards efficient implementation of FIR filters. Part of the work presented in this dissertation is architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of the periodic model filters. These time-multiplexed FRM filters not only reduce the number of multipliers but lowers the memory usage. Although the FRM technique requires a higher number delay elements, it results in fewer memories and more energy efficient memory schemes when time-multiplexed. Different memory arrangements and memory access schemes have also been discussed and compared in terms of their efficiency when using both single and dual-port memories. An efficient pipelining scheme has been proposed which reduces the number of pipelining registers while achieving similar clock frequencies. The single optimal point where the number of multiplications is minimum for non-time-multiplexed FRM filters is shown to become a function of both the period, L and time-multiplexing factor, M. This means that the minimum number of multipliers does not always correspond to the minimum number of multiplications which also increases the flexibility of implementation. These filters are shown to achieve power reduction between 23% and 68% for the considered examples. To simplify the multiplier, alternate number systems like the LNS have been used to implement FIR filters, which reduces the multiplications to additions. FIR filters are realized by directly designing them using ILP in the LNS domain in the minimax sense using finite word length constraints. The branch and bound algorithm, a typical algorithm to implement ILP problems, is implemented based on LNS integers and several branching strategies are proposed and evaluated. The filter coefficients thus obtained are compared with the traditional finite word length coefficients obtained in the linear domain. It is shown that LNS FIR filters provide a better approximation error compared to a standard FIR filter for a given coefficient word length. FIR filters also offer an opportunity in complexity reduction by implementing the multipliers using Booth or standard high-radix multiplication. Both of these multiplication schemes generate pre-computed multiples of the multiplicand which are then selected based on the encoded bits of the multiplier. In TDF FIR filters, one input data is multiplied with a number of coefficients and complexity can be reduced by sharing the pre-computation of the multiplies of the input data for all multiplications. Part of this work includes a systematic and unified approach to the design of such computation sharing multipliers and a comparison of the two forms of multiplication. It also gives closed form expressions for the cost of different parts of multiplication and gives an overview of various ways to implement the select unit with respect to the design of multiplexers. Particle filters are used to solve problems that require estimation of a system. Improved resampling schemes for reducing the latency of the resampling stage is proposed which uses a pre-fetch technique to reduce the latency between 50% to 95% dependent on the number of pre-fetches. Generalized division-free architectures and compact memory structures are also proposed that map to different resampling algorithms and also help in reducing the complexity of the multinomial resampling algorithm and reduce the number of memories required by up to 50%.
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Velmurugan, Rajbabu. "Implementation Strategies for Particle Filter based Target Tracking". Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/14611.
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This thesis contributes new algorithms and implementations for particle filter-based target tracking. From an algorithmic perspective, modifications that improve a batch-based acoustic direction-of-arrival (DOA), multi-target, particle filter tracker are presented. The main improvements are reduced execution time and increased robustness to target maneuvers. The key feature of the batch-based tracker is an image template-matching approach that handles data association and clutter in measurements. The particle filter tracker is compared to an extended Kalman filter~(EKF) and a Laplacian filter and is shown to perform better for maneuvering targets. Using an approach similar to the acoustic tracker, a radar range-only tracker is also developed. This includes developing the state update and observation models, and proving observability
for a batch of range measurements.
From an implementation perspective, this thesis provides new low-power and real-time implementations for particle filters. First, to achieve a very low-power implementation, two mixed-mode implementation strategies that use
analog and digital components are developed. The mixed-mode implementations use analog, multiple-input translinear element (MITE) networks to realize nonlinear functions. The power dissipated in the mixed-mode implementation of a particle filter-based, bearings-only tracker is compared to a digital implementation that uses the CORDIC algorithm to realize the nonlinear functions. The mixed-mode method that uses predominantly analog components is shown to provide a factor of twenty improvement in power savings compared to a digital implementation. Next, real-time implementation strategies for the batch-based acoustic DOA tracker are developed. The characteristics of the digital implementation of the tracker are quantified using digital signal processor (DSP) and field-programmable gate array (FPGA) implementations. The FPGA implementation uses a soft-core or hard-core processor to implement the Newton search in the particle proposal stage. A MITE implementation of the nonlinear DOA update function in the tracker is also presented.
11
Oruc, Sacid. "Electronically Tunable Microwave Bandstop Filter Design And Implementation". Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/12612419/index.pdf.
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In modern broadband microwave applications, receivers are very sensitive to interference signals which can come from the system itself or from hostile emitters. Electronically tunable bandstop filters can be used to eliminate these interference signals with adaptation to changing frequency conditions. In this thesis, electronically tunable bandstop filter design techniques are investigated for microwave frequencies. The aim is to find filter topologies which allow narrowband bandstop or &lsquonotch&rsquo
filter designs with low-Q resonators and with tuning capability. Tunability will be provided by the use of electronically tunable capacitors, specifically varactor diodes. For this purpose, firstly direct bandstop filter techniques are investigated and their performances are analyzed. Then phase cancellation approach, which enables high quality bandstop filter design with lossy circuit elements, is introduced and analyzed. Lastly, a novel notch filter design technique called as all-pass filter approach is introduced. This approach allows a systematic design method and enables to design very good tunable notch filter characteristics with low-Q resonators. Three filter topologies using this approach are given and their performances are analyzed. Also prototype tunable notch filters operating in X-Band are designed and implemented by using these three topologies.
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Conell, David. "Hardware Implementation of a Digital Anti-aliasing Filter". International Foundation for Telemetering, 1989. http://hdl.handle.net/10150/614669.
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International Telemetering Conference Proceedings / October 30-November 02, 1989 / Town & Country Hotel & Convention Center, San Diego, CaliforniaThis paper presents a practical application of a realtime, in-flight programmable digital filter. This filter consists of one module in a PCM system consisting of a central unit and one or more remotes. The paper will also discuss how filtering is achieved given that the PCM format is also user programmable.
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Karlsson, Magnus. "Implementation of digital-serial filters /". Linköping : Dept. of Electrical Engineering, Univ, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-3520.
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Mohsén, Mikael. "Implementation and Evaluation of Single Filter Frequency Masking Narrow-Band High-Speed Recursive Digital Filters". Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1522.
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In this thesis two versions of a single filter frequency masking narrow-band high-speed recursive digital filter structure, proposed in [1], have been implemented and evaluated considering the maximal clock frequency, the maximal sample frequency and the power consumption. The structures were compared to a conventional filter structure, that was also implemented. The aim was to see if the proposed structure had some benefits when implemented and synthesized, not only in theory. For the synthesis standard cells from AMS csx 0.35 mm CMOS technology were used.
15
Karlsson, Magnus. "Implementation of digit-serial filters". Doctoral thesis, Linköpings universitet, Institutionen för systemteknik, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-3520.
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In this thesis we discuss the design and implementation of Digital Signal Processing (DSP) applications in a standard digital CMOS technology. The aim is to fulfill a throughput requirement with lowest possible power consumption. As a case study a frequency selective filter is implemented using a half-band FIR filter and a bireciprocal Lattice Wave Digital Filter (LWDF) in a 0.35 µm CMOS process. The thesis is presented in a top-down manner, following the steps in the topdown design methodology. This design methodology, which has been used for bit-serial maximally fast implementations of IIR filters in the past, is here extended and applied for digit-serial implementations of recursive and non-recursive algorithms. Transformations such as pipelining and unfolding for increasing the throughput is applied and compared from throughput and power consumption points of view. A measure of the level of the logic pipelining is developed, i.e., the Latency Model (LM), which is used as a tuning variable between throughput and power consumption. The excess speed gained by the transformations can later be traded for low power operation by lowering the supply voltage, i.e., architecture driven voltage scaling. In the FIR filter case, it is shown that for low power operation with a given throughput requirement, that algorithm unfolding without pipelining is preferable. Decreasing the power consumption with 40, and 50 percent compared to pipelining at the logic or algorithm level, respectively. The digit-size should be tuned with the throughput requirement, i.e., using a large digit-size for low throughput requirement and decrease the digit-size with increasing throughput. In the bireciprocal LWDF case, the LM order can be used as a tuning variable for a trade-off between low energy consumption and high throughput. In this case using LM 0, i.e., non-pipelined processing elements yields minimum energy consumption and LM 1, i.e., use of pipelined processing elements, yields maximum throughput. By introducing some pipelined processing elements in the non-pipelined filter design a fractional LM order is obtained. Using three adders between every pipeline register, i.e., LM 1/3, yields a near maximum throughput and a near minimum energy consumption. In all cases should the digit-size be equal to the number of fractional bits in the coefficient. At the arithmetic level, digit-serial adders is designed and implemented in a 0.35 µm CMOS process, showing that for the digit-sizes, , the Ripple-Carry Adders (RCA) are preferable over Carry-Look-Ahead adders (CLA) from a throughput point of view. It is also shown that fixed coefficient digitserial multipliers based on unfolding of serial/parallel multipliers can obtain the same throughput as the corresponding adder in the digit-size range D = 2...4. A complex multiplier based on distributed arithmetic is used as a test case, implemented in a 0.8 µm CMOS process for evaluation of different logic styles from robustness, area, speed, and power consumption points of view. The evaluated logic styles are, non-overlapping pseudo two-phase clocked C2MOS latches with pass-transistor logic, Precharged True Single Phase Clocked logic (PTSPC), and Differential Cascade Voltage Switch logic (DCVS) with Single Transistor Clocked (STC) latches. In addition we propose a non-precharged true single phase clocked differential logic style, which is suitable for implementation of robust, high speed, and low power arithmetic processing elements, denoted Differential NMOS logic (DN-logic). The comparison shows that the two-phase clocked logic style is the best choice from a power consumption point of view, when voltage scaling can not be applied and the throughput requirement is low. However, the DN-logic style is the best choice when the throughput requirements is high or when voltage scaling is used.
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Kleinbauer, Rachel. "Kalman filtering implementation with Matlab". [S.l. : s.n.], 2004. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB11612048.
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Kaake, Fadi M. "A VLSI-nMOS hardware implementation of an IIR bandpass orthogonal digital filter". Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183133214.
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Wilbur, Mickey Joe D. "The VLSI implementation of a GIC switched capacitor filter". Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1998. http://handle.dtic.mil/100.2/ADA346083.
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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, March 1998.Thesis advisor(s): Sherif N. Michael. "March 1998."--Cover. Includes bibliographical references (p. 141-142). Also available online.
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Khosravi, Mehdi. "Morphological approaches to linear filter implementation and template matching". Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/13745.
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Petrie, Neil. "The design and implementation of digital wave filter adaptors". Thesis, University of Edinburgh, 1985. http://hdl.handle.net/1842/15641.
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Bailey, Daniel A. "Simulation and implementation of fixed-point digital filter structures". Thesis, This resource online, 1995. http://scholar.lib.vt.edu/theses/available/etd-07112009-040546/.
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Lin, Andrew Y. "Implementation considerations for fpga-based adaptive transversal filter designs". [Gainesville, Fla.] : University of Florida, 2003. http://purl.fcla.edu/fcla/etd/UFE0001395.
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Svanström, Fredrik. "Kalman filtering : With a radar tracking implementation". Thesis, Linnéuniversitetet, Institutionen för matematik (MA), 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:lnu:diva-30855.
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The Kalman filter algorithm can be applied as a recursive estimator of the state of a dynamic system described by a linear difference equation. Given discrete measurements linearly related to the state of the system, but corrupted by white Gaussian noise, the Kalman filter estimate of the system is statistically optimal with respect to a quadratic function of the estimate error. The first objective of this paper is to give deep enough insight into the mathematics of the Kalman filter algorithm to be able to choose the correct type of algorithm and to set all the parameters correctly in a basic application. This description also includes several examples of different approaches to derive and to explain the Kalman filter algorithm. In addition to the mathematical description of the Kalman filter algorithm this paper also provides an implementation written in MATLAB. The objective of this part is to correctly replicate the target tracker used in the surveillance radar PS-90. The result of the implementation is evaluated using a simulated target programmed to have an aircraft-like behaviour and done without access to the actual source code of the tracker in the PS-90 radar
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Vishwanath, T. G. "Adaptive estimation theory with real-time implementation". Thesis, University of the West of Scotland, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.376566.
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Alwan, Abdulrahman. "Implementation of Wavelet-Kalman Filtering Technique for Auditory Brainstem Response". Thesis, Linköpings universitet, Informationskodning, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-85116.
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Auditory brainstem response (ABR) evaluation has been one of the most reliable methods for evaluating hearing loss. Clinically available methods for ABR tests require averaging for a large number of sweeps (~1000-2000) in order to obtain a meaningful ABR signal, which is time consuming. This study proposes a faster new method for ABR filtering based on wavelet-Kalman filter that is able to produce a meaningful ABR signal with less than 500 sweeps. The method is validated against ABR data acquired from 7 normal hearing subjects with different stimulus intensity levels, the lowest being 30 dB NHL. The proposed method was able to filter and produce a readable ABR signal using 400 sweeps; other ABR signal criteria were also presented to validate the performance of the proposed method.
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Matharu, P. S. "Architectures for the VLSI implementation of digital filters". Thesis, City University London, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.382819.
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Ahmed, Kadrya Mohammed. "The design and implementation of a microprocessor controlled adaptive filter". Thesis, Durham University, 1986. http://etheses.dur.ac.uk/7092/.
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This thesis describes the construction and implementation of a microprocessor controlled recursive adaptive filter applied as a noise canceller. It describes the concept of the adaptive noise canceller, a method of estimating the received signal corrupted with additive interference (noise). This canceller has two inputs, the primary input containing the corrupted signal and the reference input consisting of the additive noise correlated in some unknown way to the primary noise. The reference input is filtered and subtracted from the primary input without degrading the desired components of the signal. This filtering process is adaptive and based on Widrow-Hoff Least-Mean-Square algorithm. Adaptive filters are programmable and have the capability to adjust their own parameters in situations where minimum piori knowledge is available about the inputs. For recursive filters, these parameters include feed-forward (non-recursive) as well as feedback (recursive) coefficients. A new design and implementation of the adaptive filter is suggested which uses a high speed 68000 microprocessor to accomplish the coefficients updating operation. Many practical problems arising in the hardware implementation are investigated. Simulation results illustrate the ability of the adaptive noise canceller to have an acceptable performance when the coefficients updating operation is carried out once every N sampling periods. Both simulation and hardware experimental results are in agreement.
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Pettit, Steven L. "VLSI implementation of a digitally programmable three stage GIC filter". Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1995. http://handle.dtic.mil/100.2/ADA311308.
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Kubicki, Adam R. "The design and implementation of a digitally programmable GIC filter". Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1999. http://handle.dtic.mil/100.2/ADA370247.
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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, September 1999."September 1999". Thesis advisor(s): Sherif Michael. Includes bibliographical references (p. 135). Also available online.
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Lind, Johnny. "Signal Processor Implementation of Digital Filter and Linear Systems Laborations". Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-19077.
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The goal of this bachelor thesis has been to investigate if the laboratory exercises in the courses digital filters and linear systems can be moved from matlab to a digital signal processor. The processor is a TMS320C6713 floating point processor mounted on a development board.
The original laboratories have been implemented and analyzed and some suggested changes have been presented for the digital filter laboration. For the laboration in linear systems, the exercise can be implemented as it is today. Furthermore, a transmultiplexer has been implemented and tested for real time execution.
Finally, an application programming interface has also been implemented, with common functions, used in the laboratories.
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Tunströmer, Anders. "Analysis and Implementation of a Digital Filter for Wire Guidance". Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-69676.
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This master thesisinvestigates the possibilities to implement a digital filter for wire guidancein a truck. The analog circuits in the truck, today, are analyzed to understandtheir signal processing. The component MAX261 is especially interesting and itis analyzed in a special Section to make sure that all needed details, todevelop a digital filter, are available. When all theoretical calculation wasfinished, all the circuits were simulated to make sure that the calculationsare correct. The digital filter is based onan analog filter which is expensive and not so easy to purchase. A requirementspecification was developed by analysis of the properties of the analog filterand how it is currently used. The analog filter is a part of a chain of analogsignal processing which mostly can be performed digitally instead. The special type of the analogfilter makes the requirements, on the digital filter, very tough and anextensive analysis of digital filter structures was performed in order to finda suitable filter. The digital filter is of WDF (Wave Digital Filter)-type andit is very special, because it has two variable coefficients, one for thesteepness and one for the center frequency. The digital filter consists of anumber of first order filters, because a higher order filter with desiredproperties has coefficient values that are large which makes the stabilityproperties worse. The best type ofimplementation of this filter and the signal processing are also analyzed.Finally, a prototype was developed on a development board where the maincomponent is a DSP (Digital Signal Processor). The program for the prototype iswritten in C-code and the performance of the system was verified by differenttests and measurements.
32
Wang, Wei. "Implementation of a Filter and Multiplier for Next Generation Transceivers". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-92239.
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A new sub-sampling technology is presented to greatly lower the sampling frequency of the transceivers with wideband inputs. The innovation of the theory is the flexible selection and conversion of any single band out of a multiband spectrum. According to the theoretical work on a sub-sampling wideband receiver, such a technology enables demodulation of wideband inputs with a sampling frequency much lower than the carrier frequencies, and converts the band of interest to a low frequency band simultaneously. The purpose is to make it easier for the subsequent ADC to process a single band when applying a low-pass filter after the demodulation. The technology is also fit for the transmitter, which inversely converts wideband inputs to a high frequency band and make the band of interest located on the carrier frequency point. Compared with traditional demodulation, we generate a waveform containing a multiple set of sinusoids instead of using a single local oscillator, and pass them through a carefully designed band-pass filter. The filter eliminates all the harmonics except the one located at the band of our interest. Then both the multiband inputs and the output of the filter are mixed by an analog multiplier. After such a process, the band we want is now converted to a low frequency. The objective of this master thesis is verification and implementation of the principle in order to evaluate which best performance can be reached. The whole architecture is simulated and finally validated in circuit level using 90nm CMOS technology.
33
Rector, Timothy Leigh. "Design and real-time implementation of a multifrequency tracking filter". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0025/MQ62145.pdf.
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Chen, Tsuhan. "Multidimensional multirate filters and filter banks : theory, design, and implementation". Thesis, 1993. https://thesis.library.caltech.edu/3207/1/Chen_t_1993.pdf.
Pełny tekst źródłaStreszczenie:
Multidimensional (MD) multirate systems, which find applications in the coding and compression of image and video data, and in high definition television (HDTV) systems, have recently attracted much attention. Central to these systems is the idea of sampling lattices. The basic building blocks in an MD multirate system are the decimation matrix M, the expansion matrix L, and MD digital filters. When M and L are diagonal, most of the one-dimensional (1D) multirate results can be extended automatically, using separable approaches (i.e., separate operations in each dimension). Separable approaches are commonly used in practice due to their low complexity in implementation. However, nonseparable operations, with respect to nondiagonal decimation and expansion matrices, often provide more flexibility and better performance. Several applications, such as the conversion between progressive and interlaced video signals, actually require the use of nonseparable operations. For the nonseparable case, extensions of 1D results to the MD case are nontrivial. In this thesis, we will introduce some developments in these extensions. The three main results are: the design of nonseparable MD filters and filter banks derived from 1D filters, the commutativity of MD decimators and expanders and its applications to the efficient polyphase implementation of MD rational decimation systems, and the vector space framework for unifying MD filter bank and wavelet theory. In particular, properties of integer matrices like matrix fraction descriptions, coprimeness, the Bezout identity, etc., of which the polynomial versions are known in system theory, are used for the first time in the area of multirate signal processing.
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Pei-yi, Ju, i 朱珮儀. "Implementation of Speculation Pre-Filter". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/81661538808155597782.
Pełny tekst źródłaStreszczenie:
碩士國立交通大學
電機學院電信學程
100
Pattern matching, finding patterns to gain wealthy information, is one of the most applied techniques in information retrieval and malware detection. Based on the purpose of improving pattern matching outcome, we review several most popular theories of pattern matching process in current technology, including pre-filter, a quickly excluder to eliminate the nullity part of patterns, which is a common technique to lead to efficient pattern matching result . The Speculation pre-filter developed by NTL Lab is an efficient pre-filter that utilizes all previous query results by software programming. In the research, it is provided three different pre-filters implemented by Xilinx FPGA, containing Stateful pre-filter, Speculation pre-filter and Pipeline speculation pre-filter. Dual-port ram and pipeline are expected to accelerate pattern matching speed by multi-tasking function and enhance the performance of the hardware utility. Experimental result shows that the throughput in Speculation pre-filter is 1.5 times greater than Stateful pre-filter. Moreover, we discover that the throughput in pipe-line speculation pre-filter is 4 times faster than which in Speculation pre-filter, however, LUT in pipe-line speculation pre-filter only increases 2 times than which in Speculation pre-filter and no extra RAM spaces in pipe-line speculation pre-filter added. In the conclusion, pipe-line with pre-filters promises higher efficiency and performance in pattern matching.
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Liao, Kuohsiang, i 廖國翔. "Artificial Neural Network Implementation Of Bilateral Filter And Mean Shift Filter". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/86300114613336742226.
Pełny tekst źródłaStreszczenie:
碩士義守大學
資訊工程學系
100
Many algorithms have been proposed to deal with noises which have outstanding results in the abatement of noise, but it could not avoid the artificial product. For example, in the blurred images the noise and the details of images belong to the high frequency component and distinguish are more difficult. In this paper, we apply bilateral filter and mean shift filter which smooth images and remove the noises, and preserve the edge signals. Bilateral filter is improved by the Gaussian function that in the spatial domain and intensity domain. Bilateral filter characteristic can smooth the image but the edge of the high-frequency information can be retained and not be smoothed. Mean shift filter characteristics can smooth and segment in the image but at the edge will obviously be distinction. We apply Artificial Neural Network (ANN) to simulate bilateral filter and mean shift filter. The proposed ANN method for non-linear filters will use different activation functions and the kernel functions which can perform more complex operations and is more flexible than the traditional filter.
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Ming-Ta, Yang, i 楊明達. "Implementation of Digital Active Power Filter". Thesis, 1998. http://ndltd.ncl.edu.tw/handle/27309731383038396886.
Pełny tekst źródłaStreszczenie:
碩士國立雲林科技大學
電機工程技術研究所
86
Power electronics have been widely used in ac to dc converters. They own performances of fast response, small volume, and high efficiency, but serious power pollution is also introduced. Traditional solutions are using capacitor and inductor to make up passive filter for solving harmonics problem. To improve system power factor, a reactive power compensator is used to increase the power efficiency and reduce the transmission line loss. Active power filter not only has the properties of reactive power compensator but also simultaneously eliminate harmonic currents. The architecture of active power filter can be classified into series type, chopping type, dual power conversion type, and shunt type. This thesis presented two cases of study of the algorithm compensated-reference-current-computing and the current control techniques of shunt active power filter. There are two methods for the computing compensated reference current. For generating compensated currents three kinds of current control are used. Including 1) three-phase independent hysteresis band control 2) three-phase independent triangular carrier control 3) two-phase dependent d-q axis space vector control. This thesis studies the performance of steady state, dynamic response, and current harmonic spectrum distribution for both methods. The control algorithms are simulated using software SIMNON and tested by experimental prototype hardware based on TMS320C50 DSP. With the high performance DSP chips, most of complex computations can be accomplished in one sampling cycle.
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Bhatia, Zorawar. "On Kalman filter implementation on FPGAs". Thesis, 2012. http://hdl.handle.net/1828/4365.
Pełny tekst źródłaStreszczenie:
The following dissertation attempts to highlight and address the implementation and
performance of a Kalman filter on an FPGA. The reasons for choosing the Kalman filter
and the platform for implementation are highlighted as well as an in depth explanation of
the components and theory behind both are given.
A controller system which allows the optimal performance of the Kalman filter on it is
developed in VHDL. The design of the controller is dictated by the analysis of the
Kalman filter which ensures only the most necessary components and operations are built
into the instruction set. The controller is made up of several components including the
loader, the ALU, Data RAM, KF IO, Control Store and the Branch Unit. The components
working in conjunction allows the system to interface though a handshaking protocol
with a peripheral of arbitrary latency. The control store is loaded with program code that
is determined by converting human readable assembler into machine code through a Perl
encoder. The controller system is tested and verified though an extensive testbench
environment that emulates all outside signals and views internal operations. The
controller system is capable of five matrix operations which are computed in parallel due
to the FPGA development environment, which is far superior in this case to the
alternative: a software solution, due to the vector operations inherent in the Kalman filter
algorithm.
The Kalman filter operation is analyzed and simulated in a MATLAB environment and
this analysis confirms the need for the parallel processing power of the FPGA system
upon which the controller has been built. FPGA statistical analysis confirms the
successful implementation of the system meeting all criteria set at the outset of the
project, including memory usage, IO usage and performance and accuracy benchmarks.Graduate
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HU, SHU-HAO, i 胡書豪. "Design and Implementation of Broadband Filter". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/e959hv.
Pełny tekst źródłaStreszczenie:
碩士逢甲大學
通訊工程所
100
Bandpass Filter has extensively been exploited as one of the key building blocks in the front of the RF (Radio Frequency) system to improve signal quality,In the paper, based on the multi-mode resonance of the Coplanar Waveguide (CPW) , broadside-coupled and defected ground structure (DGS) to design three kinds of BroadDual Bandpass Filters with Wide-band Behavior.This Filter not only up to 78% fractional bandwidth, had simple structure, high sheep, simple structure also good performance of the GSM (1800 MHz ),GPS(1.57 GHz) and WCDMA (2.1 GHz ) application can be exhibited.Finally, We used the bend skill, making the filter more compact ,and this structure is fabricated on a FR4 substrate.
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陳治華. "Analysis and implementation of EMI filter". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/25792062805841606853.
Pełny tekst źródłaStreszczenie:
碩士明新科技大學
電機工程研究所
94
The aim of this research is to analyze, design and implement of EMI filter. It is well known that EMI filter is useful for suppressing conducted electromagnetic interference. The conducted electromagnetic interference produced by switching power supply and electronic ballast are serious due to their voltage switching phenomena. In this thesis, the conducted electromagnetic interference of switching power supply and electronic ballast will be studied and various EMI filters are designed to reduce these EMI effects. The standards of FCC Part 15; Class B Conducted and EN 55022; Class B Conducted were used in this study. The EMI effect can be reduced by using ferrite core in high frequency range. In the procedure of designing EMI filter, power splitter is used to isolate the noise of equipment under test (EUT) into common mode and differential mode. Matlab and Pspice are used to extract the component and decaying values of EMI filter. With suitable design of EMI filter, the conducted emissions of PC power supply and electronic ballast will be reduced and accord with the limitations of FCC Part 15; Class B Conducted and EN 55022; Class B Conducted.
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Yang, Meng-Ru, i 楊孟儒. "The FPGA Implementation of Adaptive Filter". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/39765239672492410930.
Pełny tekst źródłaStreszczenie:
碩士元智大學
電機工程學系
90
Adaptive filters are widely used algorithm used for applications such as echo cancellation, system identification and control, channel equalization, acoustic beamforming, voiceband modems, digital mobile radio, and speech and image processing. In particular, LMS adaptive filter has advantages of low cost, simplification, and good performance. In this thesis, a soft IP of a configurable fixed-point LMS adaptive filter is designed with VHDL. The design is verified with FPGA. It can be used for any filter order as long as the FPGA has enough gate numbers. The LMS design is a parallel architecture and it is pipelined with relax look-ahead technology. It can be used by adjusting the filter order and parameters for different applications.
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Petrone, Joseph Foo Simon Y. "Adaptive filter architectures for FPGA implementation". 2004. http://etd.lib.fsu.edu/theses/available/etd-07062004-133258.
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Thesis (M.S.)--Florida State University, 2004.Advisor: Dr. Simon Y. Foo, Florida State University, College of Engineering, Dept. of Electrical and Computer Engineering. Title and description from dissertation home page (viewed Sept. 27, 2004). Includes bibliographical references.
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HUANG, JHAN-YU, i 黃展育. "LUT-based Bilateral Filter Hardware Implementation". Thesis, 2019. http://ndltd.ncl.edu.tw/handle/p4uq89.
Pełny tekst źródłaStreszczenie:
碩士國立中正大學
電機工程研究所
107
Image blurring is a technique majoring to reduce image noise and reduce detail when image processing and inferior sampling, Therefore, image blurring can effectively reduce image noise. This research focuses on a technology applied to image blurring, bilateral filters for hardware, and the desire to improve the image quality without consuming too much hardware cost and achieving weight reduction. Since exponential calculation is difficult to implement on hardware, we use the look-up table method as the basis for exponential calculation because of computing hardware and memory usage. By analyzing the two weights of the bilateral filter for the traditional bilateral filter, which is the Similarity weight and the Closeness weight. According to our algorithm, the original formula can be simplified to a certain extent to achieve the purpose of hardware simplification. In addition to improving image quality, this study also focuses on reducing the computational complexity and hardware cost of the algorithm. the research also focused on reducing the computational complexity and hardware cost. We are devoted to implement the hardware of real-time applications with line buffer-based algorithm.
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Ravi, Rakesh Kumar. "FPGA implementation of adaptive filter architectures". Thesis, 2012. http://ethesis.nitrkl.ac.in/3888/1/Ravi_thesis.pdf.
Pełny tekst źródłaStreszczenie:
This thesis proposes an FPGA Implementation of an Adaptive Filter architecture using LMS algorithm. Adaptive filters are commonly used in a wide range of applications such as Echo cancellation, Noise cancellation, Prediction, Adaptive interference canceling, System modeling or system identification, Radar signal processing, Equalizations of communication channels, Biomedical signal enhancements, Navigational systems, Digital communication Receiver, Adaptive antenna systems beamforming and many more. In this thesis, adaptive filter architecture implemented mainly application for noise cancellation, system identification and channel equalization. For noise cancellation, architecture is taken both sequential as well as parallel. For implementing Adaptive filter architecture, LMS algorithm is used because of low computational complexity, simplicity and its better performance in different running environments. In this thesis most of the adaptive filter architecture is taken a Gaussian noise, but in many practical real situation it is seen that, using Gaussian noise is not sufficient, because Gaussian noise has a fixed shape “Bell curve “ but many situation can’t predict the noise shape, So impulsive noise consideration is very important. Impulsive noise generally has no fixed shape it varying large amplitude spikes which is overlapped so many samples. So it is very difficult to detect or cancel it. The impulsive noise is generally destructive types of signal distortion. So in this thesis impulsive noise reduction is also main aim of implementation. In all adaptive filter architecture try to minimize error i.e. minimization of different between the desired output and the real one for all the input vectors.Nowadays, the use of Field programmable gate arrays (FPGAs) is growing. Field programmable gate arrays (FPGAs) are widely used in many areas such as audio and video, Digital signal processing, Image signal Processing, Digital communication systems, mobile communication system and many other embedded applications, because of their high performance, parallel processing ability and flexibility. Implementation of FPGA, generally two ways either writing a HDL Code or by using a System Generator tool. Using Hardware Description Languages (HDL) for FPGA implementation is too time consuming and needs background in a chip design, so in thesis all architecture implemented on FPGA using Xilinx Spartan-3E Starter Kit as the target board and Xilinx System Generator (XSG). Using System Generator tool is easy because it is generates automatically HDL (VHDL/Verilog) code. Generated HDL code can be synthesized and implemented in the Xilinx FPGAs.
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SHREYANSH. "ACTIVE FILTER IMPLEMENTATION USING CURRENT MODE BLOCK". Thesis, 2021. http://dspace.dtu.ac.in:8080/jspui/handle/repository/18939.
Pełny tekst źródłaStreszczenie:
One of the famous and fundamental building block that may be utilised in a variety of ways to
perform various analog processing function is a Current Conveyor abbreviated as CC. Till date
various researches has been made in this regards and various functionality like amplifier, filters
etc can be achieved by using these devices. A Current Conveyor is a minimum three terminal
devices but not limited to it. CC’s can be classified according to their generation. The current
conveyor (CC) concept was first released in 1968 this is called as first generation of current
conveyor and after two years in 1970 second generation has been developed and later on third
generation of current conveyor is also developed, we will discuss about this in greater details
in upcoming chapters..
Various other analog processing block also uses current conveyor as these primary block. The
CFOA (current feedback opamp ) & CCII (second-generation current conveyor) are considered
adaptable building blocks in analog current mode signal processing. One of the famous novel
five-port analog building block that combine these two CFOA & CCII is OFCC (operational
floating conveyor) and this may be used for a variety of applications. It combines the functions
of a current feedback op-amp & a current conveyor in one package.
This thesis shows the implementation of OFCC block as universal current mode device which
can be used in realization of various functions where earlier an operational amplifier were used.
Further it also shows the implementation of active biquad filter using new OFCC Block in a)
TAM (Trans Admittance Mode) b) VM (Voltage mode) c) TIM (Trans Impedance Mode) d)
CM (Current Mode). The OFCC block and amplifier is implemented in CMOS 90nm and
130nm technology node and later filter has been implemented on CMOS 130nm technology
node by using software Symica DE. For low voltage applications and to minimize power
consumption it uses single supply of 0.4 V. Various plots for OFCC block, amplifier and filter
are also present in this thesis.
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Tsuei, Danny Teng-Hsiang. "2D Digital Filter Implementation on a FPGA". Thesis, 2011. http://hdl.handle.net/10012/6221.
Pełny tekst źródłaStreszczenie:
The use of two dimensional (2D) digital filters for real-time 2D data processing has found important practical applications in many areas, such as aerial surveillance, satellite
imaging and pattern recognition. In the case of military operations, real-time image pro-cessing is extensively used in target acquisition and tracking, automatic target recognition and identi cation, and guidance of autonomous robots. Furthermore, equal opportunities exist in civil industries such as vacuum cleaner path recognition and mapping and car collision detection and avoidance. Many of these applications require dedicated hardware for signal processing. It is not efficient to implement 2D digital filters using a single processor for real-time applications due to the large amount of data. A multiprocessor
implementation can be used in order to reduce processing time.
Previous work explored several realizations of 2D denominator separable digital filters
with minimal throughput delay by utilizing parallel processors. It was shown that regardless of the order of the filter, a throughput delay of one adder and one multiplier can be
achieved. The proposed realizations have high regularity due to the nature of the processors. In this thesis, all four realizations are implemented in a Field Programming Gate
Array (FPGA) with floating point adders, multipliers and shift registers. The implementation details and design trade-offs are discussed. Simulation results in terms of performance, area and power are compared.
From the experimental results, realization four is the ideal candidate for implementation on an Application Specific Integrated Circuit (ASIC) since it has the best performance, dissipates the lowest power, and uses the least amount of logic when compared to other realizations of the same filter size. For a filter size of 5 by 5, realization four can produce a throughput of 16.3 million pixels per second, which is comparable to realization one and about 34% increase in performance compared to realization one and two. For the given
filter size, realization four dissipates the same amount of dynamic power as realization one, and roughly 54% less than realization three and 140% less than realization two. Furthermore, area reduction can be applied by converting floating point algorithms to fixed point algorithms. Alternatively, the denormalization and normalization stage of the floating point pipeline can be eliminated and fused together in order to save hardware resources.
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Ching, Chen Chia, i 陳家慶. "The Design and Implementation of Filter Algorithm". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/33864841092857219667.
Pełny tekst źródłaStreszczenie:
碩士真理大學
數理科學研究所
92
Based on the vector space model and the self-description advantage of XML, an information retrieval algorithm, with better precision and performance, is proposed in this thesis. In this study, the system is structured by a native XML database and a feedback approach. Moreover, the algorithm for this system reduces unnecessary computations and speeds up the performance of the searching. This study provides a new approach that employs the tree method to filter the undesired data and a new weighting formula to have better precision. According to the data analyses of a demonstrative example, this system have shown better precision and less retrieving time than the traditional approach.
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Wu, Bo Cheng, i 吳柏成. "Subband coding and its multirate filter implementation". Thesis, 1994. http://ndltd.ncl.edu.tw/handle/35344264541052307505.
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Yang, Jeng-Shiann, i 楊政憲. "Design and Implementation of Digital Filter Banks". Thesis, 2000. http://ndltd.ncl.edu.tw/handle/48030945401907568186.
Pełny tekst źródłaStreszczenie:
碩士國立高雄第一科技大學
電腦與通訊工程系
88
The designs of two-channel filter banks have attracted a lot of researchers in the past years and the associated algorithms have developed greatly. These multirate systems can be applied in many areas, such as subband image coding, speech processing and video compression. In this thesis, we collect the related algorithms and propose other approaches. We use the Lagrange multiplier approach to find out all the continuous coefficients of the analysis filters in the two-channel perfect-reconstruction filter banks. This method minimizes the squared error of the overall filter bank so it is optimal in the least squares sense. Lagrange multiplier approach can also be applied to search all the discrete coefficients. We can, therefore, just use the Lagrange multiplier approach to design the wanted systems, such as 1-D three-channel, 2-D two-channel perfect reconstruction filter banks. The application of McClellan transform to the design of 2-D two-channel perfect reconstruction filter banks has been proposed and performs very well. In this thesis, we implement the architecture of 11-tap filter. The required coefficients are fed into the designed system externally and this structure would produce a truncated 9-bit integer output every one clock. This architecture is described and simulated by using Verilog tools. Then we adopt Synopsys and Cadence tools to translate the original design into the physical layout. Finally, this chip is fabricated in TSMC 0.35μm CMOS technology.
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SHIH, YU-CHENG, i 施有政. "Real-Time Bilateral Filter by FPGA Implementation". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/91793145941549715951.
Pełny tekst źródłaStreszczenie:
碩士輔仁大學
電機工程學系碩士班
105
This thesis applies the FPGA (Field-Programmable Gate Array) to implement real-time bilateral filter for image denoising. The advantages of bilateral filter are to reduce noise effectively but at same time preserve the structural information of images. Therefore, the bilateral filter is widely used in image processing. However, the bilateral filter needs more computational resources because of its complex calculation involved. We propose a method to implement a real-time bilateral filter through reducing computational complexity. Our design is designed on register-level parallelized pipeline architecture, and separating bilateral filter’s input data into groups. After calculating the similarity function, results were transferred to a distance component and then an adder tree. This process is introduced to accelerate the operation of the similarity function and obtain result in real-time. The filter size of this method can be easily adjustable different filtering effects. This method was implemented on Xilinx Zynq, and the frequency of FPGA is 150MHz. We used PSNR (Peak Signal to Noise Ratio) and SSIM (Structural Similarity Index) to validate our design and the comparison with the existing methods with the different filter sizes demonstrates that our design can achieve better image quality. In terms of execution speed, our design is 574 times faster than the classical bilateral filter running on a PC for grey images that are 1920x1080 and have 8-bit depth. Our method can achieve real-time performance with 33 FPS.