Rozprawy doktorskie na temat „Field Programmable Gate Arrays”
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Howard, Neil John. "Defect-tolerant Field-Programmable Gate Arrays". Thesis, University of York, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.359290.
Pełny tekst źródłaHall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach". Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.
Pełny tekst źródłaPrvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.
Leong, David Chin Kuang. "Incremental placement for field-programmable gate arrays". Thesis, University of British Columbia, 2006. http://hdl.handle.net/2429/31671.
Pełny tekst źródłaApplied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
Messa, Norman C. "Design implementation into field programmable gate arrays". Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/26451.
Pełny tekst źródłaNiu, Jianyong. "Digital control using field programmable gate arrays". Thesis, University of Sheffield, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.434507.
Pełny tekst źródłaLu, Aiguo. "Logic synthesis for field programmable gate arrays". Thesis, University of Bristol, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295061.
Pełny tekst źródłaNewalkar, Aditya. "Alternative techniques for Built-In Self-Test of Field Programmable Gate Arrays". Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Summer/master's/NEWALKAR_ADITYA_6.pdf.
Pełny tekst źródłaКарнаушенко, В. П., i А. В. Бородин. "Field Programmable Counter Arrays Integration with Field Programmable Gates Arrays". Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-004.
Pełny tekst źródłaVachranukunkiet, Petya Nagvajara Prawat Johnson Jeremy. "Power flow computation using field programmable gate arrays /". Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1789.
Pełny tekst źródłaCamus, Dominic Roger. "Improved logic optimisation for field programmable gate arrays". Thesis, University of Oxford, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.301840.
Pełny tekst źródłaJames, Calvin L. "COMPLEX WAVEFORM GENERATION UTILIZING FIELD PROGRAMMABLE GATE ARRAYS". International Foundation for Telemetering, 1997. http://hdl.handle.net/10150/609692.
Pełny tekst źródłaThe basic building blocks for implementing complex waveform generators using a look-up table approach are random access memory (RAM) and read only memory (ROM) devices. Due to technological advancements in field programmable gate array (FPGA) development, these devices have the ability to allocate large amounts of memory elements within the same structure. The self containment property makes the FPGA a suitable topology for complex waveform generation applications. In addition, this self containment property significantly reduces implementation costs by reducing the number of external components required to support many applications. This paper examines the use of FPGA’s in various complex waveform generation applications. In particular, a discussion will ensue examining possible mappings of the time domain response of the complex waveform into memory elements of the FPGA. The analyses and examples contained in the sequel are from existing waveform generation applications, developed for Gauissian Minimum Shift Keying (GMSK) and Unbalanced Quadriphase Shift Keying (UQPSK) modulation formats.
Malik, Usama Computer Science & Engineering Faculty of Engineering UNSW. "Configuration encoding techniques for fast FPGA reconfiguration". Awarded by:University of New South Wales. School of Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/26212.
Pełny tekst źródłaKoh, Shannon Computer Science & Engineering Faculty of Engineering UNSW. "Generating the communication infrastracture for module-based dynamic reconfiguration of FPGas". Publisher:University of New South Wales. Computer Science & Engineering, 2008. http://handle.unsw.edu.au/1959.4/41418.
Pełny tekst źródłaWood, Christopher Landon. "Runtime partial FPGA reconfiguration". Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15051.
Pełny tekst źródłaGalindo, Juan Manuel. "A novel partial reconfiguration methodology for FPGAs of multichip systems /". Online version of thesis, 2008. http://hdl.handle.net/1850/7784.
Pełny tekst źródłaRajagopalan, Kamal. "An FPGA architecture for improved arithmetic performance /". St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16460.pdf.
Pełny tekst źródłaGray, Jordan D. "Application of Floating-Gate Transistors in Field Programmable Analog Arrays". Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7540.
Pełny tekst źródłaKällström, Petter. "Direct Digital Frequency Synthesis in Field-Programmable Gate Arrays". Thesis, Linköping University, Department of Electrical Engineering, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-56550.
Pełny tekst źródłaThis thesis is about creation of a Matlab program that suggests and automatically generates a Phase to Sine Amplitude Converter (PSAC) in the hardware language VHDL, suitable for Direct Digital Frequency Synthesis (DDFS). Main hardware target is Field Programmable Gate Arrays (FPGAs).
Focus in this report is how an FPGA works, different methods for sine amplitude generation and their signal qualities vs the hardware resources they use.
Detta exjobb handlar om att skapa ett Matlab-program som föreslår och implementerar en sinusgenerator i hårdvaruspråket VHDL, avsedd för digital frekvenssyntes (DDFS). Ämnad hårdvara för implementeringen är en fältprogrammerbar grindmatris (FPGA).
Fokus i denna rapport ligger på hur en FPGA är uppbyggd, olika metoder för sinusgenerering och vilka kvaliteter på sinusvågen de ger och vilka resurser i hårdvaran de använder.
Mutlu, Baris Ragip. "Real-time Motion Control Using Field Programmable Gate Arrays". Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/12612049/index.pdf.
Pełny tekst źródłaand finally an assembled solution is developed to test the overall design. Tests of the overall design are realized via hardware-in-the-loop simulation of a real-world control problem, selected as a CNC machining center. The developed methods are discussed in terms of their success, resource consumptions and attainable sampling rates.
Raina, Baljit Singh. "Delay-optimized placement in symmetrical field-programmable gate arrays". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ31862.pdf.
Pełny tekst źródłaTickle, Andrew Jason. "Applications of Morphological Operators on Field Programmable Gate Arrays". Thesis, University of Liverpool, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.507628.
Pełny tekst źródłaAmbat, Shadab Gopinath. "SINGLE EVENT UPSET DETECTION IN FIELD PROGRAMMABLE GATE ARRAYS". UKnowledge, 2008. http://uknowledge.uky.edu/gradschool_theses/511.
Pełny tekst źródłaSelf, R. P. "Software-orientated system design for field programmable gate arrays". Thesis, University of Essex, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.397736.
Pełny tekst źródłaSharma, Akshay. "Place and route techniques for FPGA architecture advancement /". Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.
Pełny tekst źródłaShen, Ying. "Compiling a synchronous programming language into field programmable gate arrays". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0029/MQ47476.pdf.
Pełny tekst źródłaSareen, Aman. "Reconfigurable design for pattern recognition using field programmable gate arrays". Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1175625525.
Pełny tekst źródłaDixon, Bobby Earl Stroud Charles E. "Built-in self-test of the programmable interconnect in field programmable gate arrays". Auburn, Ala, 2008. http://repo.lib.auburn.edu/EtdRoot/2008/FALL/Electrical_and_Computer_Engineering/Thesis/Dixon_Bobby_16.pdf.
Pełny tekst źródłaBrown, Simon James. "Fault-tolerance of field-programmable gate arrays subjected to radiation". Thesis, University of Salford, 2010. http://usir.salford.ac.uk/26592/.
Pełny tekst źródłaMacQueen, Daniel Montgomery. "Total ionizing dose effects on Xilinx field-programmable gate arrays". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ59840.pdf.
Pełny tekst źródłaRoyal, Andrew Peter. "Globally asynchronous locally synchronous interconnect for field programmable gate arrays". Thesis, Imperial College London, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.415717.
Pełny tekst źródłaGundam, Madhuri. "Implementation of Directional Median Filtering using Field Programmable Gate Arrays". ScholarWorks@UNO, 2010. http://scholarworks.uno.edu/td/111.
Pełny tekst źródłaDavis, James. "Low-overhead fault-tolerant logic for field-programmable gate arrays". Thesis, Imperial College London, 2015. http://hdl.handle.net/10044/1/44382.
Pełny tekst źródłaPapadonikolakis, Markos. "Mapping of support vector machines on field programmable gate arrays". Thesis, Imperial College London, 2012. http://hdl.handle.net/10044/1/10004.
Pełny tekst źródłaPotgieter, Juan-Pierre. "Single event upset testing of flash based field programmable gate arrays". Thesis, Nelson Mandela Metropolitan University, 2015. http://hdl.handle.net/10948/12520.
Pełny tekst źródłaOrtiz, Gual Fernando Enrique. "Novel reconfigurable computing architectures for embedded high performance signal processing and numerical applications". Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file 1.73 Mb., 102 p, 2006. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&res_dat=xri:pqdiss&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&rft_dat=xri:pqdiss:3221141.
Pełny tekst źródłaMilton, Daniel. "Built-in self test of configurable memory resources in field programmable gate arrays". Auburn, Ala., 2007. http://repo.lib.auburn.edu/07M%20Theses/MILTON_DANIEL_9.pdf.
Pełny tekst źródłaLin, Yu Colin, i 林郁. "ArchSyn: an energy-efficient FPGA high-level synthesizer". Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2012. http://hub.hku.hk/bib/B49799599.
Pełny tekst źródłapublished_or_final_version
Electrical and Electronic Engineering
Doctoral
Doctor of Philosophy
Hauck, Scott. "Multi-FPGA systems /". Thesis, Connect to this title online; UW restricted, 1995. http://hdl.handle.net/1773/7008.
Pełny tekst źródłaJohnson, Steven A. "Implementation of a configurable fault tolerant processor (CFTP)". Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Mar%5FJohnson.pdf.
Pełny tekst źródłaThesis advisor(s): Herschel H. Loomis, Alan A. Ross. Includes bibliographical references (p. 117). Also available online.
Han, Yi. "Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology". Thesis, [S.l. : s.n.], 2008. http://dk.cput.ac.za/cgi/viewcontent.cgi?article=1011&context=td_cput.
Pełny tekst źródłaSchlottmann, Craig Richard. "Analog signal processing on a reconfigurable platform". Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29623.
Pełny tekst źródłaCommittee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam. Part of the SMARTech Electronic Thesis and Dissertation Collection.
Mak, Wai-kei. "Partitioning and routing for multi-FPGA systems /". Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.
Pełny tekst źródłaChang, Mark L. "Variable precision analysis for FPGA synthesis /". Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5901.
Pełny tekst źródłaKumar, Akhilesh. "Leakage Power Modeling and Reduction Techniques for Field Programmable Gate Arrays". Thesis, University of Waterloo, 2006. http://hdl.handle.net/10012/766.
Pełny tekst źródłaIn this work an analytical state dependent leakage power model for FPGAs is developed, followed by dual-Vt based designs of the FPGA architecture for reducing leakage power.
The leakage power model computes subthreshold and gate leakage in FPGAs, since these are the two dominant components of total leakage power in the scaled nanometer technologies. The leakage power model takes into account the dependency of gate and subthreshold leakage on the state of the circuit inputs. The leakage power model has two main components, one which computes the probability of a state for a particular FPGA circuit element, and the other which computes the leakage of the FPGA circuit element for a given input using analytical equations. This FPGA power model is particularly important for rapidly analyzing various FPGA architectures across different technology nodes.
Dual-Vt based designs of the FPGA architecture are proposed, developed, and evaluated, for reducing the leakage power using a CAD framework. The logic and the routing resources of the FPGA are considered for dual-Vt assignment. The number of the logic elements that can be assigned high-Vt in the ideal case by using a dual-Vt assignment algorithm in the CAD framework is estimated. Based upon this estimate two kinds of architectures are developed and evaluated, homogeneous and heterogeneous architectures. Results indicate that leakage power savings of up to 50% can be obtained from these architectures. The analytical state dependent leakage power model developed has been used for estimating the leakage power savings from the dual-Vt FPGA architectures. The CAD framework that has been developed can also be used for developing and evaluating different dual-Vt FPGA architectures, other than the ones proposed in this work.
Wilton, Steven J. E. "Architectures and algorithms for field-programmable gate arrays with embedded memory". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp03/NQ28082.pdf.
Pełny tekst źródłaLi, Wei. "Routability prediction for field programmable gate arrays with hierarchical interconnection structures". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ31846.pdf.
Pełny tekst źródłaDai, Zhibin. "Routability prediction for Field Programmable Gate Arrays with a routing hierarchy". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ56315.pdf.
Pełny tekst źródłaLamoureux, Julien. "Modeling and reduction of dynamic power in field-programmable gate arrays". Thesis, University of British Columbia, 2007. http://hdl.handle.net/2429/414.
Pełny tekst źródłaCampregher, Nicola. "Interconnect yield analysis and fault tolerance for field programmable gate arrays". Thesis, Imperial College London, 2007. http://hdl.handle.net/10044/1/11966.
Pełny tekst źródłaInuani, Maurice Kilavuka. "Technology mapping of heterogeneous lookup table based field programmable gate arrays". Thesis, University of Oxford, 1998. http://ora.ox.ac.uk/objects/uuid:8ec8745f-c0b2-43c0-994f-bd949d9fdefa.
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