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Soldner, Wolfgang Wilhelm. "HF-ESD-Codesign". Aachen Shaker, 2009. http://d-nb.info/996579168/04.
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Drüen, Stephan [Verfasser]. "Virtual ESD Test – : An ESD Analysis Methodology at Chip Level / Stephan Drüen". Aachen : Shaker, 2007. http://d-nb.info/1166508595/34.
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Soldner, Wolfgang W. [Verfasser]. "HF ESD CODESIGN / Wolfgang W Soldner". Aachen : Shaker, 2009. http://d-nb.info/1159834857/34.
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Chung, Youngeun. "Education for Sustainable Development (ESD) in Sweden: A study of ESD within a transition affected by PISA reports". Thesis, Uppsala universitet, Institutionen för geovetenskaper, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-210157.
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Education for Sustainable Development (ESD) has been called for playing a crucial role in integrating principles,values, and practices accorded with sustainable development. Holistic approach, ethical values, norm transitionand behavior changes are required to achieve the aim of ESD. However, while both external and internal impactsof the Swedish education system have affected its fundamental values and aims, core elements of ESD inSwedish curriculum were also influenced. This paper analyzes, in particular, the changes that PISA reportsbrought in the Swedish curriculum at the discourse level, and its potential effects on ESD. Discourse analysiswas mainly used for comparing two curricula and two syllabi. With the help of situational contexts of PISA andthe curriculum of 2011, a transition observed from text analysis was interpreted and the final discussion wasanchored with social contexts from educational discourses. The result indicated that influences from PISA in thenew curriculum and syllabus were observed in corresponded aims and goals. Situational and social contexts alsopointed to the same direction of transition due to the previous goals-oriented curriculum that made a wide rangeof teaching. Thus, fundamental values, aims and goals were changed into providing clearer guidelines forteaching scope and gradings as well as into focusing literacy skills and knowledge of concepts. In the process ofthe transition, holistic approach, ethical and democratical values, as well as focus on cultural aspects and pupils’ attributes were removed or shrunken, which implied negative impacts on ESD. On the other hand, emphasis onliteracy skills of students in the new curriculum was expected to bring positive achievement for ESD.Furthermore, in order to achieve the norm transition toward sustainable development, those lost immeasurable values are suggested to be addressed in future Swedish education.
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Dukhan, Al-Hytham, i Dastan Hassan. "Undersökning av alternativa ESD-skydd inom produktion". Thesis, Högskolan i Skövde, Institutionen för ingenjörsvetenskap, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:his:diva-19657.
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Tillverkning av elektroniska produkter ökar och utvecklas vilket medför till att flera skyddsåtgärder behöver vidtas under tillverkningsprocessen. Elektroniska komponenter kan skadas av elektrostatisk urladdning (ESD). Elektroniktillverkande industrier vill minimera ESD-risken inom produktionsmiljön för att minimera skaderisken i samband med produkterna. Företag använder sig av skyddsåtgärd i form av olika ESD-skyddssystem vilket bidrar till en ESD-kontrollerad produktionsmiljö. Ett projekt har utförts på företaget Veoneer, projektet bygger på en undersökning av det nuvarande ESD-systemet samt en undersökning av två alternativa ESD-skyddssystem. Vetenskapliga artiklar baserat på tre olika ESD-skyddssystem har undersökts för att evaluera kostnaderna och implementationsmöjligheten i produktionen. Undersökningen användes för att utvärdera neutraliseringseffektiviteten av den statiska uppladdningen. De undersökta ESD-skyddssystemen är följande ESD-emballagen som används i nuläget, ersättning av ESD-plast till enbart plast i samband med jonisatorer och slutligen justering av luftfuktigheten. Det nuvarande ESD-systemet skyddar produktionen från elektrostatiska urladdningar. Problemet med systemet är det höga priset för ESD-emballagen. Projektstyrningen baseras på tillvägagångsättet projekt base, projektstyrningsmetoden består av följande fyra stadier förstudier, planering, genomförande och avslut. Den nuvarande ESD-systemet och jonisator systemet undersöktes genom forskningsstudier och experiment. Justering av luftfuktigheten undersöktes enbart via litteraturstudier samt via företagsrapporter. För att möjliggöra experimenten anordnades mätverktyg för att uppmäta den elektrostatiska uppladdningen av ESD-emballagen samt plastemballagen. Jonisatorer implementerades inför slutexperimentet för att uppmätta den elektrostatiska neutraliseringsförmågan. Ekonomiska kalkyler av ESD-plastemballagen har utformats i samband med jonisatorer och plastemballage för att fastställa prisskillnaden mellan ESD-skyddssystemen. Experimentet bidrog till säkra och godkända mätvärden vilket medför ur ett experimentperspektiv till att jonisator systemet och det nuvarande system inte utsätter produkterna för någon ESD-risk. Införandet av jonisatorer leder till en stor ekonomisk besparing om lösningen skulle tillämpas som ersättningsalternativ. Jonisatorn bör inte implementeras direkt, fler utförliga studier behöver åstadkommas innan ett nytt ESD-system införskaffas. Företagets luftfuktighetsstudier påvisade negativa resultat vilket medförde till att inga fysiska luftfuktighetsexperiment kunde verkställas på företaget. Flera förbättringsförslag har åstadkommits i samband med nulägets ESD-skyddssystem och jonisator systemet. Förbättringsförslagen innefattar materialbyte ur ett ekonomiskt och ekologiskt hållbarhetsperspektiv samt har förslag på arbetsstandarden åstadkommits.As time goes on, the manufacturing of electronic products is increasing and evolving, which calls for the introduction of protective measures on electronic components. Electronic components can be problematic as they produce electrostatic discharge (ESD), something that the manufacturing industry aims to reduce. By implementing safety measures in various ESD-protective systems, which leads to a minimized risk of ESD damage. A project has been carried out at the company Veoneer, the project is based on a study regarding the current ESD-system and a study on two other ESD-protection systems. Literature study and experimentation have been accomplished in relation to the three ESD-protective systems to evaluate the costs and implementation possibilities of production and to further evaluate the effectiveness of neutralization of the static charge. The following ESD-protective systems examined are the currently using ESD-packaging, replacement of ESD-plastic to plastic trays only in combination with ionizers and finally adjustment of the relative humidity. The current ESD-system protects production from electrostatic discharges. The problem with the current system is the costly price ratio of the ESD-packaging. Veoneer carried out a project based on a study regarding the current ESD-system and a study on two other ESD-protective systems. Through the study of relevant literature and experimentation, the three ESD-protective systems have been analyzed to evaluate the costs and implementation possibilities of production and further evaluate the static charge's effectiveness of neutralization. The following ESD-protective systems currently use ESD-packaging, replacement of ESD-plastic trays to plastic trays with ionizers, and finally, adjusting the relative humidity. On the one hand, the current ESD-system protects production from electrostatic discharges, but the current system's problem is the costly price ratio of the ESD-packaging. Project management is centered around the project-based approach. The project-management method consists of four stages of feasibility: studies, planning, implementation, and closure. The control methodology has ensured that the project runs smoothly. The current ESD and ionizer systems were investigated through research studies and experiments, whereas adjustment of humidity was investigated solely through literature studies and company reports. To begin the experiments, measuring tools were arranged to calculate the electrostatic charge in regards to the ESD-packaging and the plastic packaging. Ionizers were utilized for the final experiment to measure the electrostatic neutralization capacity with plastic packaging. Economic calculations have been carried out by the ESD-plastic packaging in conjunction with ionizers and discovered that plastic packaging alone can determine the price difference between the ESD-systems. The experiment resulted in safe and approved readings, meaning that from an experimental perspective, the ionizer system and the current system do not expose products to any ESD-risk. The introduction of ionizers could lead to huge savings if they were to be used as a replacement option. The ionizer should not be implemented directly; more detailed studies need to be carried out before a new ESD-system is acquired. The company's humidity studies showed negative results, implying that the company could not carry out physical experiments concerning humidity. Several proposed improvements have been suggested regarding the current ESD-protection and ionizer system. The improvement proposals includes change of material from an economic and ecological sustainability perspective, and several proposals havebeen made regarding the working standards.
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Muthukrishnan, Swaminathan. "ESD Protected SiGe HBT RFIC Power Amplifiers". Thesis, Virginia Tech, 2005. http://hdl.handle.net/10919/31705.
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Over the last few decades, the susceptibility of integrated circuits to electrostatic discharge (ESD) induced damages has justified the use of dedicated on-chip protection circuits. Design of robust protection circuits remains a challenging task because ESD failure mechanisms have become more acute as device dimensions continue to shrink. A lack of understanding of the ESD phenomena coupled with the increased sensitivity of smaller devices and time-to-market demands has led to a trial-and-error approach to ESD-protected circuit design. Improved analysis capabilities and a systematic design approach are essential to accomplish the challenging task of providing adequate protection to core circuit(s).
The design of ESD protection circuitry for RFIC's has been relatively slow to evolve, compared to their digital counterparts, and is now emerging as a new design challenge in RF and high-speed mixed-signal IC development. Sub-circuits which are not embedded in a single System-on-Chip (SOC), such as RF Power amplifiers (PAs), are of particular concern as they are more susceptible to the various ESD events.
This thesis presents the development of integrated ESD protection circuitry for two RFIC Power Amplifier designs. A prototype PA for 2.4 GHz Wireless Local Area Network (WLAN) applications was redesigned to provide protection to the RF input and the PA Control pins. A relatively new technique known as the L-C tank approach was used to protect the RFinput while a standard diode ring approach was used to protect the control line. The protection techniques studied were subsequently extended to a completely protected three-stage PA targeting 1.9 GHz Digitally Enhanced Cordless Telephone (DECT) applications. An on-chip shunt-L-series-C input matching network was used to provide ESD protection to the input pin of the DECT PA. A much more area efficient (as compared to the diode ring technique) Zener diode approach was used to protect the control and signal lines. The PA's RF performance was virtually unaffected by the addition of the protection circuits.
Both PAs were designed in a commercially available 0.5 ìm SiGe-HBT process. The partially protected WLAN PA was fabricated and packaged in a 3mm x 3mm Fine Pitch Quad Flat Package FQFP-N 12 Lead package and had a measured ESD protection rating of ± 1kV standard Human Body Model (HBM) ESD test. The simulated DECT PA demonstrated +1.5kV/-4kV HBM performance.Master of Science
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Černá, Martina. "Překážky volného pohybu pracovníků v judikatuře ESD". Master's thesis, Vysoká škola ekonomická v Praze, 2009. http://www.nusl.cz/ntk/nusl-18117.
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The aim of my thesis is to acquaint the reader with the problematic of free movement of workers, both from the theoretical point of view and from practical point of view based on the European Court of Justice cases. In the theoretical part of the thesis, I focus on the characteristics of internal market and definition of free movement of persons and workers. I mention individual law regulations that significantly influence the problematic of free movement of persons. Further, I describe different exceptions from free movement of workers, mutual recognition of academic qualifications and social security regarding the movement of workers. And at last in my practical part, I analyze individual cases of ECJ which have had the most significant impact on the development of free movement of workers.
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Zupac, Dragan 1961. "ESD-induced noncatastrophic damage in power MOSFETs". Thesis, The University of Arizona, 1990. http://hdl.handle.net/10150/291470.
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Electrostatic discharge (ESD) may, depending on the energy of the pulse, cause either catastrophic failures or degradation of MOSFETs. Effects of noncatastrophic positive Human-Body Model (HBM) ESD stress at the gate of power MOSFETs are investigated in this work. Noncatastrophic damage is manifested in the form of positive charge trapping in the gate oxide. In p-channel devices used in this study, the charge injection and trapping occur predominantly in the gate oxide areas lying above the p-body region. In p-channel devices used, the charge is injected mainly from the p-drain region. Based on the polarity of the pulse and the regions observed to contribute to charge injection, a model of ESD-induced charge injection from the silicon into the oxide is proposed. Finally, the effects of noncatastrophic ESD events on the radiation response of n-channel power MOSFETs are reported.
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Cao, Yiqun [Verfasser], Stephan [Akademischer Betreuer] Frei i Bernd [Gutachter] Deutschmann. "High-voltage ESD structures and ESD protection concepts in smart power technologies / Yiqun Cao ; Gutachter: Bernd Deutschmann ; Betreuer: Stephan Frei". Dortmund : Universitätsbibliothek Dortmund, 2019. http://d-nb.info/1200209605/34.
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Escudié, Fabien. "Optimisation de modèles comportementaux de composants pour la prédiction de défaillances fonctionnelles et matérielles liées aux décharges électrostatiques (ESD)". Thesis, Toulouse 3, 2018. http://www.theses.fr/2018TOU30266/document.
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Les événements transitoires de forte puissance (EFT - Electrical Fast Transient) sont l'une des préoccupations des concepteurs de systèmes embarqués. Ils peuvent conduire au dysfonctionnement du système et sont à l'origine d'un grand nombre de défaillances matérielles et fonctionnelles. Notre étude est principalement portée sur l'impact des décharges électrostatique (ESD - Electro Static Discharge) sur l'électronique embarquée dans un véhicule. D'après une étude de Renault, un véhicule peut subir deux décharges par jour durant sa vie. Les ingénieurs systèmes ne disposent pas de moyen pour prédire l'impact de ces décharges dans les systèmes, et les solutions actuelles sont essentiellement basées sur l'expérience. Afin de prédire le chemin d'un ESD dans tout le système électronique et la stratégie de protection à adopter pour protéger les composants les plus sensibles, des recherches dans le monde entier sont en cours. Les travaux de recherche du groupe ESE du LAAS-CNRS ont mené à des méthodologies de modélisation de composant passif, de circuit intégré et de carte électronique en VHDL-AMS. Les circuits intégrés sont dotés d'un réseau de protection ESD interne qui permet de détourner le stress des zones critiques. La méthodologie développée au cours des précédentes années permet de modéliser le comportement de ce réseau de protection. Cependant, ces modèles sont rudimentaires, ils décrivent uniquement le niveau de déclenchement de la protection et son impédance quasi-statique en fonction du niveau de stress ESD. Aucune information sur le comportement transitoire de la protection n'est décrite dans le modèle. Il est donc difficile de prévoir certaines défaillances liées aux phénomènes transitoires de déclenchement des protections faisant apparaitre de très fortes surtensions ou des niveaux de courant mal évalués. Les différents aspects abordés durant cette thèse permettent de résoudre ces problèmes en proposant des modèles dynamiques, et différentes méthodes pour pouvoir extraire les paramètres des modèles.[...]Electrical Fast Transient (EFT) are one of the concerns of embedded system engineers. They can lead to system malfunction. EFT are the cause of a large number of hardware and software failures. Our study is mainly focused on the impact of Electro Static Discharge (ESD) on embedded electronic systems, focusing on car's applications. According to a Renault's study, a car can suffer two discharges per day during its entire life. System engineers do not have any tools to predict the ESD impact on the systems. In order to predict the ESD path throughout the electronic system and adjust the ESD protection strategy to provide proper protection for all critical components, some researches around the world are in process. The research results from ESE working group from the LAAS-CNRS laboratory, were mainly on passive components, integrated circuits and electronics boards modeling methods, implemented in VHDL-AMS language. Integrated circuits have an internal ESD protection network that helps to deflect the stress from critical areas. The methodology developed in the last few years allows to model the behavior of this protection network. However, these models are basically made, they are made of the triggering level of the protection and the impedance value of the component depending on the ESD stress amplitude. No information on the transient behavior of the protections is included in this model. It is not possible to predict some failures related to the transient phenomenon of the protection like triggering and turning on time that induce very high overvoltage or mismatch on the current levels estimation. The various topics covered during this thesis allows to solve these problems by using a, proposed dynamic model. Different methods are proposed to extract the parameters used into the dynamic model. One important point also aborted into this document is that the model have to be able to predict the soft failure which can appear in the system during an ESD stress.[...]
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Narasimha, Raju Divya. "Study of ESD effects on RF power amplifiers". Master's thesis, University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4993.
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Today, ESD is a major consideration in the design and manufacture of ICs. ESD problems are increasing in the electronics industry because of the increasing trend toward higher speed and smaller device sizes. There is growing interest in knowing the effects of ESD protection circuit on the performance of semiconductor integrated circuits (ICs) because of the impact it has on core RF circuit performance. This study investigated the impact of ESD protection circuit on RF Power amplifiers. Even though ESD protection for digital circuits has been known for a while, RF-ESD is a challenge. From a thorough literature search on prior art ESD protection circuits, Silicon controlled rectifier was found to be most effective and reliable ESD protection for power amplifier circuit. A SCR based ESD protection was used to protect the power amplifier and a model was developed to gain better understanding of ESD protected power amplifiers. Simulated results were compared and contrasted against theoretically derived equations. A 5.2GHz fully ESD protected Class AB power amplifier was designed and simulated using TSMC 0.18 micrometer] technology. Further, the ESD protection circuit was added to a cascoded Class-E power amplifier operating at 5.2 GHz. ADS simulation results were used to analyze the PA's RF performance degradation. Various optimization techniques were used to improve the RF circuit performance.ID: 029809372; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (M.S.)--University of Central Florida, 2011.; Includes bibliographical references.
M.S.
Masters
Electrical Engineering and Computer Science
Engineering and Computer Science
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Malobabic, Slavica. "Transient Safe Operating Area (TSOA) for ESD applications". Doctoral diss., University of Central Florida, 2012. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5420.
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A methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in Electrostatic Discharge (ESD) time frame is developed through measurements and Technology Computer Aided Design (TCAD). A set of parameters based on transient measurements are used to define Transient Safe Operating Area (TSOA). The parameters are then used to assess effectiveness of protection devices for output and input pins. The methodology for input pins includes establishing ESD design targets under Charged Device Model (CDM) type stress in low voltage MOS inputs. The methodology for output pins includes defining ESD design targets under Human Metal Model (HMM) type stress in high voltage Laterally Diffused MOS (LDMOS) outputs. First, the assessment of standalone LDMOS robustness is performed, followed by establishment of protection design guidelines. Secondly, standalone clamp HMM robustness is evaluated and a prediction methodology for HMM type stress is developed based on standardized testing. Finally, LDMOS and protection clamp parallel protection conditions are identified.ID: 031001296; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Adviser: Juin J. Liou.; Title from PDF title page (viewed March 7, 2013).; Thesis (Ph.D.)--University of Central Florida, 2012.; Includes bibliographical references (p. 252-262).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering
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Papoušek, Tomáš. "Omezení volného pohybu pracovníků v rámci rozhodnutí ESD". Master's thesis, Vysoká škola ekonomická v Praze, 2007. http://www.nusl.cz/ntk/nusl-2476.
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Cílem této práce je rozebrání základních principů fungování volného pohybu pracovníků se zaměřením na jeho jednotlivá omezení, a to ve vztahu k judikatuře Evropského soudního dvora. V práci jsou tak popsána jak přípustná tak zakázáná omezení.
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Běťák, Petr. "Modelování a návrh ESD ochran v integrovaných obvodech". Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-233447.
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The thesis introduces new semiconductor structures that are used as protections against Electrostatic Discharge occuring in integrated circuits. The fundamental structure for modeling and simulation has been lateral Silicon Controlled Rectifier. This SCR structure has been modificated to enable tuning of the triggering and holding voltages by changing geometrical mask dimensions. On the base of modeling and simulation the new proposed structures have been published. Also several protection structures have been designed to be manufactured and measured on a testchip. The final electrical behavior has been verified by measurement. Finally, the focus has been aided to protection circuit with bipolar transistor. This approach has been also simulated and verified by measurement. Advantages and disadvantages of the proposed protection structures are commented in the thesis.
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Nolhier, Nicolas. "Methodologie de conception des protections des circuits intégrés contre les décharges électostatiques". Habilitation à diriger des recherches, Université Paul Sabatier - Toulouse III, 2005. http://tel.archives-ouvertes.fr/tel-00265344.
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La problématique des agressions par décharges électrostatiques (ESD) est un facteur critique dans la fiabilité des circuits intégrés. Ce document effectue la synthèse des travaux menés au LAAS-CNRS dans ce domaine. Les points suivants seront plus particulièrement abordés : - L'étude des mécanismes physiques qui gèrent le comportement d'un composant lors d'une décharge ESD - La mise en place d'une méthodologie de conception de structures de protection - Son application au développement de solutions de protection innovantes La dernière partie de ce document propose les perspectives de cet axe de recherche qui sont principalement motivés par les progrès technologiques des circuits intégrés, l'évolution des normes de robustesse et l'extension de nos travaux au niveau du système.
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Bönisch, Sven Peter. "Die elektrostatische Entladung (ESD) bei kleinen Abständen und Spannungen". [S.l.] : [s.n.], 2004. http://deposit.ddb.de/cgi-bin/dokserv?idn=969940599.
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Zur, Nieden Friedrich [Verfasser]. "Charakterisierung und Modellierung von ESD-Prüfgeneratoren / Friedrich Zur Nieden". München : Verlag Dr. Hut, 2014. http://d-nb.info/1063221897/34.
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Mrňák, Petr. "Veřejná správa v judikatuře ESD a v tuzemské praxi". Master's thesis, Vysoká škola ekonomická v Praze, 2010. http://www.nusl.cz/ntk/nusl-75771.
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In my thesis I analyzed the characteristics of the legal concepts of bodies governed by public law and the activities in which they engage as public authorities, as used by law (both European and national) governing value added tax. I also analyzed the case law of the European Court of Justice relating to the issue of the bodies governed by public law and the activities in which they engage as public authorities in terms of value added tax. The characteristics of the concepts have been evaluated and sorted logically. In a separate part I examined the bodies governed by public law and their activities from an economic point of view. I have pondered whether it is necessary that these entities have a special position in the system of value added tax.
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Nikolaidis, Théodoros. "Optimisation des performances ESD de circuits intègres CMOS submicroniques". Grenoble INPG, 1995. http://www.theses.fr/1995INPG0185.
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Apres avoir presente les notions de base au sujet des decharges electrostatiques (esd) (origine des decharges electrostatiques, modeles de decharge, effet de snap-back et effet de deuxieme claquage, modelisation des effets esd, caracterisation et methodes d'analyse de defaillance ainsi que modes de defaillance), les structures de protection de base des deux procedes cmos de cinq cent et trois cent cinquante nanometres (diodes zener-ldd et transistors npn lateraux et nmos avec/sans ldd) ont ete analysees et optimisees a l'egard des contraintes esd. Ensuite, la performance esd de circuits integres avec des differentes configurations des etages d'entree/sortie utilisant ces structures de protection a ete egalement analysee et optimisee
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Alexis, Engström. "Utbildning och hållbar utveckling : En studie av innehåll och normativitet i utsagor om hållbar utveckling i utbildningssammanhang". Thesis, Uppsala universitet, Institutionen för pedagogik, didaktik och utbildningsstudier, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-233150.
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Inom utbildning och hållbar utveckling pågår en debatt om det är utbildningensroll att främja enskilda beteenden som av experter definieras som hållbara. Åsikterna kan delas upp i utbildning förhållbar utveckling och utbildning somhållbar utveckling, där den senare är skeptisk till experters förmåga att säkert veta om ett beteende är mer hållbartän ett annat och iställetförespråkar en pluralistisk och kritisk ingång där självständigt tänkande premieras. Valet mellan att främja eller attarbeta kritiskt mednormer har i denna uppsats sammanfattats underdilemmat med normativitet.Studienbestår av två delar: Den första undersöker vilket innehåll som ges till utbildning och hållbar utveckling i utsagor från utbildningsansvariga för lärarprogrammet vid Uppsala Universitet. Den andra undersöker hur innehålleti utbildning och hållbarutvecklingförhåller sig till dilemmat med normativitet som nämns ovan.De slutsatser som kan dras utifrånundersökningen äratt innehållet som detframkommer i utsagornakan sammanfattas i fem olika teman samtatt de temanahar mycket gemensamt med resultatfråntidigare studier. Det visar på att det har börjatväxa fram en ram för vad hållbar utveckling i utbildningssammanhang kan ges för innehåll. I utsagorna framkom även innehåll som skiljer sig från tidigare forskning, t.ex. att utgå från utbildning och hållbarutveckling som en tydlig kompetens kring vilken studenter kan specialisera sig utifrån framtida arbetstillfällen, samt att studenter i större grad kan påverka innehållet, och ansvara för formerna, isin egen utbildning. Resultatet visar även att utbildningen kan utformas på ett sätt som är både normativtoch pluralistiskt. Genom att ha en medveten ingång till i vilket sammanhang fakta omhållbara beteenden presenteras, kan studenterna ges en position där de själva har möjlighet att övervaka överförandet av normer. Genom detta tillsammans med ett diskussionsklimat där läraren är i bakgrunden och låter studenterna själva identifiera ohållbara utvecklingar och värden som ska bevaras,undviksobalanseni makt mellan läraren och studenterna och ett pluralistiskt utbildningsklimat skapas.
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Glaser, Ulrich. "Complex ESD protection elements and issues in decananometre CMOS technologies /". Zürich : ETH, 2007. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=16960.
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Ungru, Thomas [Verfasser]. "Influence of ESD on integrated circuits during operation / Thomas Ungru". München : Verlag Dr. Hut, 2019. http://d-nb.info/1184090548/34.
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Boldkhuyag, Enkhtuya. "Values and pro environmental behaviour among Mongolian adolescents:Implications for ESD". Thesis, Uppsala universitet, Institutionen för geovetenskaper, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-258952.
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The study aims to contribute in the understanding of key values and behaviours for Education for sustainable development and their correlations and to further develop knowledge about how they are distributed among upper secondary school students in relation to socio-demographic factors. There were 274 surveys collected in 5 different schools in Ulaanbaatar and analysed using ANOVA followed by Tukey test and Pearson’s correlation tests. The study supports the findings of previous research that universal, benevolence and traditional values are positively correlated with a positive environmental behaviour. The positive orientation towards sustainability suggest that the current adolescent Mongolian population can become potential environmental supporters with a strong motivation towards sustainable behaviour and attitudes. The demographic and social factors were weak in relation to value orientations, no significant difference observed in value orientation. There was a notable gender difference in pro environmental behaviour which aligned with many existing academic studies. Social factors in relation to environmentally friendly attitude suggested that pro environmental adolescents were somehow exposed to the natural environment and read books during their free time displayed increasingly positive behaviour toward the environment. Therefore this study emphasises the importance of encouraging informal outdoor activities and increasing the access and popularity of reading books among youths. These measures would also serve to strengthen the benevolence value and promote pro environmental behaviour.
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Romanescu, Sorin. "Modèle compact paramétrable du SCR pour applications ESD et RF". Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00648390.
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La protection contre les décharges électrostatiques (ESD) est un fait necessaire dans chaque circuit intégré. Elle se fait par le déploiement sur la puce d'un réseau de dispositifs spéciaux, à côtés des éléments fonctionnels. La demande pour des améliorations en continu dans la conception et la simulation de l'ESD apporte le besoin de modèles nouveaux et plus précises. La SCR (" Silicon Controlled Rectifier ") est l'un des dispositifs les plus efficaces de protection contre l'ESD. Un nouveau modèle électrique, qui peut être utilisé pour évaluer les structures de protection complexe dont il fait partie, a été développé au cours de cette thèse. Construit avec une forte relation entre les phénomènes physiques et ses équations, il a été parametrisé geometriquement, offrant la possibilité d'adapter et d'optimiser le dispositif selon le niveau de protection nécessaire. Par ailleurs, une étude à haute fréquence sur le SCR et la diode de protection ESD a été réalisé, conduisant à un modèle capable de prédire l'impact de ces dispositifs ont sur le circuit protégé.
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Pan, Zhihao [Verfasser]. "Modeling and optimization of discrete ESD protection devices / Zhihao Pan". München : Verlag Dr. Hut, 2015. http://d-nb.info/1074063724/34.
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Vicherek, Ondřej. "Vliv vybraných rozhodnutí ESD na formování společné obchodní politiky EU". Master's thesis, Vysoká škola ekonomická v Praze, 2015. http://www.nusl.cz/ntk/nusl-262003.
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The goal of my diploma thesis is to describe the influence of ECJ decision making on the common commercial policy ("CCP") of EU. Specifically my thesis examines what factors influence ECJ decision making about direct effect of trade agreements implementing CCP. These factors are applied on several treaties, where the court has not yet decided on their potential direct effect and on a present case at ECJ on direct effect of WTO treaties. With regard to the goal of my thesis an important part of my thesis deals with the development of ECJ decision making. Methods applied in my thesis are analysis and comparison of selected judgements that influence the CCP of EU. After proper analysis I found out that the main motiv behind ECJ decision making is that, if the negotiating position of EU is to be deteriorated, the ECJ is likely to find that the treaty does not have direct effect. Other factors are of secondary character. Examining the influence of decision making of ECJ on direct effect of trade agreements is important, because the role of ECJ influences the legal certainty of subjects about direct applicability of international trade treaties.
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Müller, Lutz. "Untersuchung und Modellierung elektrostatischer Entladungen (ESD) von elektrisch isolierenden Oberflächen". [S.l. : s.n.], 2004. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB11380441.
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Lin, Che-Shih, i 林哲仕. "Study on Modeling of ESD Protection Devices for Circuit-Level ESD Simulation". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/96451142963494812486.
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碩士國立交通大學
電機學院微電子奈米科技產業專班
95
In addition to high performance, low cost, and low power, reliability is also an important issue in the development of VLSI technologies. Damage caused by ESD (Electro-static Discharge) is a serious threat to VLSI reliability. It is well know that ESD failures constitute a major portion of customer returns, so it is important to provide ESD protection in the IC chip against ESD damages If an ESD stress current flows into internal circuits, it can cause internal damage. Therefore, it is necessary to predict ESD immunity, which depends on the circuit design and layout. At present, trial-and-error approaches still dominate in ESD design, which result resource-consuming iteration. ESD simulations for the protection circuits are effective for solving this problem. The purpose of thesis is to construct an ESD circuit simulation system based on the SPICE circuit simulator. Through the SPICE simulation, we can reduce design cycle. In our ESD protection network, we choose the diodes, BJT, and NMOS as ESD protection devices. We will model those devices corresponding to the experiment and implement the models to the ESD circuit simulation system.
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yi, Wang kuang, i 王光一. "ESD/TLP Measurement Iustruments and ESD Immunity Anaiysis in the Electronic Device". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/05938833068028418006.
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碩士大葉大學
電機工程學系碩士在職專班
93
ABSTRACT Reliability engineer of integrated circuit occupies a most important position when the accuracy of process got better and better . The improvement of the technical procedure will enhance the reliability of integrated circuit in design. There is another element to effect the reliability engineer when we enhances the yield. Though one of the factors is the ESD of destruction.it can be avoidable. There are many productions of the protection circuit of ESD in academic.but ESD protect the circuit and some elements which protect the circuit are often effected by the efficiency of ESD stress cause the circuit protection is useless. The reliable of the circuit protection element is queried. The thesis will use some ESD protection Devices to do ESP testing. Analyze anti ESD ability. Pick up element to avoid latch up effect . To analyze the reliable ability and ESD energy. we can use the TLP and ESD instruments which is similar to ESD stress to test the anti-static electricity ability. Prote element can maintain the voltage effectively. When the element of voltage value enter the collapse point effectively and maintain appropriate capacity of releasing the ESD. Furthermore, it also prevent the coming of second collapse point effectively. Therefore how to find and the first and second appropriate collapse point is very impertant. Analyzing the static electricity workable or not in a circuit.
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Lu, Hsueh-Meng, i 呂學銘. "New ESD Protection Circuits". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/22693499839469841539.
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碩士國立臺灣科技大學
電子工程系
92
Due to the area-efficient, the SCR has become the best choice for ESD protection circuits. However, the behaviors of latchup and higher trigger voltage are the limitations for SCR’s application. Therefore, it is needed to pay much attention to design better ESD protection circuits in deep-submicron CMOS IC. In this thesis, we have proposed two new ESD protection circuits based on SCR structure. The performance of these protection circuits is really excellent when ESD event happened. One of the protection circuits is a highly latchup-immune stacked-MOSFET with silicon controlled rectifier (SM-SCR) device. The latchup effect could be avoided by using the stacked-MOSFET to turn on/off the SCR. Meanwhile, a zener diode and gate-coupled transistor can lower SM-SCR trigger voltage. The other protection circuit is a highly latchup-free ESD protection circuit with silicon controlled rectifier (LFSCR) device to demonstrate the effective ESD protection effect. The mechanism is to turn on/off the SCR by two MOSFETs during an ESD event. During the ESD event, the PMOS transistor is utilized to turn on SCR and the NMOS transistor to turn off SCR. Therefore the latchup effect can be easily eliminated by this device. Besides, the purpose of the zener diode and gate-coupled transistor could lower the trigger voltage. The implementation of these two on-chip protection circuits has been fabricated through National Science Council Chip-Implementation-Center (CIC). These two ESD protection circuits have been applied for patents in R.O.C. and U.S.A.
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Liu, Rui-Hong, i 劉睿閎. "ESD Protection Designs for 2.4GHz T/R Switch Front-End Circuits". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/92182912861687902240.
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碩士國立交通大學
電子工程學系 電子研究所
104
As the CMOS technology develops so fast, radio-frequency integrated circuits (RF ICs) has been widely implemented in CMOS process. It has the advantage of a high integration and a low cost. Electrostatic discharge (ESD) has been one of the most serious reliability issues of CMOS processes, so ESD protection design is very important. However, undesirable parasitic effect is induced by the ESD protection design in RFICs. Consequently a successful RF ESD protection design needs well ESD protection ability and small parasitic effect. In this thesis, two RF ESD protection designs for T/R switch front-end circuit are proposed. The first one can reduce the parasitic effect and sustain ESD stress. The second one can sustain ESD stress without extra ESD protection device. Both ESD protection designs are applied to 2.4GHz T/R switch front-end circuit. An RF ESD protection design for traditional T/R switch front-end circuit is also proposed in this thesis. The number of the ESD protection devices is reduced in this design. Besides, silicon-controlled rectifier (SCR) is embedded in T/R switch, and the detection circuit, which is used in power-rail ESD clamp circuit, can sent trigger signals to trigger the SCR. The embedded SCR and parasitic diode can provide ESD discharge paths. Moreover, this ESD protection designs are applied to 2.4GHz traditional T/R switch front-end circuit.
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Feng, Yao-Wu, i 馮耀武. "ESD Characteristics of Diffusion Resistor and its Application in On-chip ESD Protection Design". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/10028854190621163628.
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碩士國立交通大學
電機學院碩士在職專班電子與光電組
97
The high current conduction in silicided N+ diffusion resistor and non-silicided N+ diffusion resistor under the 100nsec pulse condition had been characterized and modeled carefully in this work. We find the resistances of both types resistors change with the square root of the stress time. It induces the current decreasing and voltage increasing with the stress time. The root cause of the non-linear IV characteristics of the diffusion resistor under high current stress can be well explained by the Joule-heating induced the resistance change. In additional, we also find that these two diffusion resistors during high current stress will appear some different characteristics. Due to these different characteristics, the silicided device cannot use the same layout as the silicided blocking device on ESD protection design.
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Chuang, Che-Hao, i 莊哲豪. "ESD Protection Design with TVS (Transient Voltage Suppressor) to Meet System-Level ESD Specifications". Thesis, 2018. http://ndltd.ncl.edu.tw/handle/4h429h.
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Yeh, Shih-Ping, i 葉士平. "ESD Protection Technology for LCM". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/13313551003104927055.
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碩士逢甲大學
電子工程所
91
This thesis will discuss Liquid Crystal Display module (LCM) Electro-Static Discharge(ESD) protection techniques. In order to up-grade the protection capability of LCM ESD, Also to build up LCM ESD protection design rule. This thesis will also survey ESD protection techniques in the component level and system level. Such as : Human body model(HBM)、Machine model(MM)、Charge device model(CDM)、Air discharge model、Contact discharge model, and to compare the speciality and experiment method between component level and system level for which based on the capability of integrated circuits protection. Add special LCM ESD protection design to verify and find out the best design conditions for increase LCM ESD protection. In addition to build up LCM ESD standards, We will also build up testing equipment for LCM in the ESD protection. It is also hope the proposed testing equipment and the test procedure can be applied in the industry as a dedicate ESD standard for LCMS. The experiment condition is base on the LCM for mobil phone. The constructure is Liquid crystal display(LCD)、Driver IC and Flexiable Printed Circuit board(FPC). Different protection design such as : Power protectind design、Resist protection design、Guard-Ring protection design、Induction protection design and shield protection design and so on. Judging from the above testing design. It is work on the improvement of ESD protection, will make LCMs to simulate the above protection design and build up mobile phone and ESD testing equipment. It is to be mentioned in this thesis under single protection design for LCM ESD. The performance is not as good as a multi protection design. So, it is proved that ESD protection design works on overall protection program. The ESD protection mentioned in this thesis is patent pending. The last in this thesis pointed out the best design of LCM ESD protection, LCM ESD level standard and LCM ESD testing equipment and build up the standard for LCM ESD protection design and experiment.
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LI, CHENG-TAO, i 李承道. "The Near Field Measurement Technology for System Level ESD Testing and Optimization of ESD Protection". Thesis, 2018. http://ndltd.ncl.edu.tw/handle/8n3m95.
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碩士國立高雄大學
電機工程學系碩博士班
106
Consumer electronics products become more versatile and smaller in size, and the feature size of circuits becomes smaller, too. The main reason why the ability of resisting electrostatic discharge is weak is that the size of circuit is smaller. In the system level electrostatic discharge testing, the testing results of the Class B and the Class C are temporary failures. For engineers who design system level electrostatic discharge it is difficult to find broken circuit directly and it delay the schedule of new products development. If it can quickly find the location of broken circuit or discharge path by a detection method, it will not reduce the cost of product only. It can design guild rule for electrostatic discharge. For the above situation, this paper develops the time domain electrostatic discharge near field system. It combines time domain instrument with near field system to observe the magnetic field of DUT with time. In this paper, the circuit which has slot pattern is used to verify the measured results and observed the slot for impacting return current. After all, by researching the location of ferrite bead for optimizing electrostatic and signal integrity. In the future, it provides a new electrostatic discharge testing to find discharge path directly and establish the design guild for electrostatic discharge and power/signal integrity optimization.
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Tsai, Ming-Hsien, i 蔡銘憲. "Design of Electrostatic Discharge (ESD) Protection for RF Front-End Integrated Circuits". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/63142812027175306133.
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博士國立清華大學
電子工程研究所
99
By co-design methodology, this study focuses on ESD protection design techniques for RF front-end integrated circuits. In a wide frequency range (from a few GHz to millimeter wave up to V-band), the proposed circuits achieve excellent RF characteristics and high ESD protection level simultaneously. The design concept is to treat the ESD protection devices as a part of the input matching network to obtain the required ESD robustness without degrading the RF performance. For RF low-noise amplifiers (LNAs) operating at 5.8 GHz, three ESD protection topologies (dual-diode, modified-SCR, and modified-SCR with dual-diode) are investigated. We propose an ESD network with multiple ESD current paths, demonstrating a 4.3-A transmission line pulse (TLP) failure level, corresponding to a 6.5-kV human body model (HBM) protection level. In addition, a wideband LNA (2.6?{6.6 GHz) with shallow-trench-isolation (STI) diodes is realized. We propose a co-design methodology for the wideband LNA with ESD protection, demonstrating a 4-kV HBM ESD performance and no degradation on RF performance. Also, the chip area of ESD protection is much smaller compared to the published distributed ESD protection technique for wideband LNA applications. For millimeter-wave LNAs, the K-band and V-band LNAs using RF junction varactors with scalable models for ESD protection and noise optimization simultaneously are designed and realized. We propose of using the gate-source junction varactor used for noise optimization and charge device model (CDM) protection simultaneously, which has not been reported previously. A 24-GHz ESD-protected LNA presents a NF of 2.9 dB and a power gain of 15.2 dB, demonstrating a 2.7-A (corresponding to a 4-kV HBM) and an 11.4-A ESD protection levels using transmission line pulse (TLP) and very fast transmission line pulse (VFTLP) tests, respectively. In addition, the V-band LNA achieves a NF of 5.2 dB and a peak power gain of 10.9 dB at 51 GHz, achieving an over 2-kV ESD protection, and only 0.8-dB degradation for both NF and power gain compared with the reference design. Finally, an analog front-end circuit with dual-directional SCR ESD protection is designed and realized for passive UHF-band RFID tag. We propose a symmetrical dual-direction ESD protection technique, which is suitable for large signal swing of RFID tag application. The measured result shows ESD levels of 3.0-kV HBM and 200-V MM, respectively. The proposed ESD protection embedded in RFID tag becomes a must for yield improvement during antenna assembly or testing process.
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Jyh, Song Hung, i 宋弘智. "ESD Protection Circuit for RF Circuits". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/23574758446776708309.
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碩士大葉大學
電機工程學系碩士班
93
In this thesis, a electrostatic discharge(ESD) protection circuit has been designed for radio frequency(RF) power amplifier of DCS 1800 system. The TSMC 0.18um RF model, and Synopsys technology company's EDA tool have been used to simulation the class E Power Amplifier's RF parameter, and then, utilize HSPICE to simulate the ESD protection circuit. Finally, the ESD protection circuit has been added to class E power amplifier and to obtain the effect of ESD circuit on RF parameter, then adjust ESD protection circuit parameter to have less effect on RF parameters and can pass two thousand voltage of human body model(HBM) ESD stress.
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董順萍. "ESD Protection of Handset Video Products". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/44856322892750950042.
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Plachý, Robert. "Pojem pozitivní opatření v judikatuře ESD". Master's thesis, 2010. http://www.nusl.cz/ntk/nusl-297011.
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Positive Action in Case Law of the ECJ The general purpose of my thesis is to analyse a relevant sources of European Union law particularly the case law of the European Court of Justice relating to the issue of positive action measures and to find out, what attitude to judicial review ECJ applies in its decision- making in this specific area. The thesis is composed of three main chapters, each of them dealing with different aspects of positive action measures. First chapter is introductory and defines basic terminology used in the thesis. This chapter is subdivided into two different sections. Section one explains what the concept of positive action means including classification of its different types and provides justification of its application. Second section focuses on the relationship between positive action measures and the concepts of equality and non-discrimination. Second chapter examines the relevant provisions of EU law which deal with the positive action measures in different areas of application of EU law with special attention to the Charter of Fundamental Rights of the European Union. Third chapter is subdivided into three sections and provides an outline of relevant case law of ECJ in the area of judicial review of positive action measures. First two sections are intended to...
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Lai, Yu-Hsuan, i 賴玉瑄. "ESD Protection Design for Broadband Circuits". Thesis, 2019. http://ndltd.ncl.edu.tw/handle/7ed5x8.
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ren, chagn ming, i 張銘仁. "The Optimal Control Strategies of Clean room ESD/ESA Problems by DC Pulsed Ionizer". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/32769254570013426397.
Pełny tekst źródłaStreszczenie:
碩士南台科技大學
電機工程系
92
When environment fact is set, we demonstrate a set-by-step program, which we used to optimize the performance of a DC pulsed ionizer in a cleanroom environment. By sequentially choosing the appropriate pulsewidth time, magnitude, and (-v/+v) percentage output of emitter supply voltage, one can obtain the optimal voltage swing and decay time. The effectiveness of this strategy is validated through a three-month follow-up monitoring.
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Lee, Chien-Ming, i 李健銘. "ESD PROTECTION DESIGN FOR RADIO FREQUENCY CIRCUITS". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/52615812726859233645.
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碩士國立交通大學
電子工程系
90
To reduce the parasitic effect of the ESD protection circuit devoted to RF integrated circuits, there are three major designs proposed in this thesis. In the first part, the two-port GSG measurement setup in the radio-frequency region (~GHz) is used to measure the power gain S21 and noise figure from different ESD devices in 0.25-µm CMOS process. Therefore, we can get the relationship between RF performance and ESD level among different ESD devices. The most suitable ESD device for RF application can be selected from the measured data. The second part presents a state-of-art ESD protection design for RF circuit with a human-body-model (HBM) ESD robustness of 8kV. By including a turn-on efficient power-rails ESD clamp circuit into the RF circuit, the ESD protection devices of the RF input pin can be operated in the forward-biased conduction, rather than the traditional junction breakdown condition. Therefore, the dimension of ESD devices for the RF input pin can be further downsized to reduce the input capacitance loading for the RF signal. This design has been successfully applied in a 900-MHz RF receiver and fabricated in a 0.25-µm CMOS process with a thick top metal layer. The experimental results have confirmed that its ESD robustness is as high as 8kV under the HBM ESD test. In the third part, a new structure of ESD protection circuit for RF application is proposed. The series LC-tank is used to block the signal loss and noise figure from the ESD protection devices to the RF input pin. The inductor is made by the top thick metal, which is suitable to conduct ESD current. The experimental results have shown that the RF performance of ESD protection circuit with LC-tank is superior to that of the traditional ESD protection circuit with double diodes. The ESD protection circuit with LC-tank is more suitable for RF application when the operation frequency becomes higher. The research results of this thesis have been applied 3 U.S. patents. Moreover, the contents of this thesis had also published three conference papers. One paper had been presented in the 2002 IEEE RFIC Symposium, the second paper has been accepted by the 2002 VLSI Design/CAD Symposium, and the third paper has been submitted to 2002 Taiwan ESD Conference.
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Lee, Wei-Ju, i 李維如. "The Research of ESD Consumer’s Purchasing Factors". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/68063121247108393199.
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碩士國立中山大學
企業管理學系研究所
90
Electronic Software Distribution(ESD) sprung up in the U.S.A. from 1994. The business volume of global ESD market was 2.5 hundred million in 1996 and the growing rate was over 100% every year. ESD attains to maturity in the U.S.A. and Europe, but the concept of ESD is still in the initial stage in Taiwan. There are a few firms offering services in this scope. However, consumers do not understand ESD clearly. Furthermore, there are very few researches about ESD in Taiwan. All the circumstances are unfavorable for popularizing and promoting ESD in Taiwan. For the above mentioned reasons, this study will seek to further our understanding of consumers’ purchasing behavior and purchasing factors through ESD and how important the purchasing factors affect consumers’ behavior. This study got the purchasing factors of ESD by analyzing and generalizing the functions of distribution in the Web, the characteristics of Internet marketing and digital product, and the Internet consumers’ purchasing factors. After that, this study analyzed the importance of these ESD consumers, purchasing factors. A web survey was conducted on one ESD web site, called SoSoft.net. The total valid sample is 95 consisting of 37 ESD patrons and 58 ESD non-patrons. And the main findings of this research are as the following: 1.The purchasing frequency of the ESD patrons is unfixed, the rate of repurchase is high and the average amount of purchasing is medium. 2.The characteristics of the responded majority are young, highly educated, and are students or employees of the IT industries. 3.The ESD consumers had long histories of using Internet. They tend to be frequent and long hour Web surfers. About half of them have Broadband (ADSL) access to the Internet. 4.For the ESD patrons, six factors are extracted from the questions on ESD purchasing factors. The factors are “purchasing process”, “characters of Internet marketing”, “variety of service”, “option of products” and “transaction costs”. As for the ESD non-patrons, six factors are extracted from the questions on ESD purchasing factors as well. The factors are “design of the website content”, “characters of Internet marketing”, “distinctive products and service”, “efficiency of purchasing process” “Web security” and “availability of try-before-you-buy service”. 5.The ESD non-patrons are much more concerned with the security of payment and the privacy of personal data. 6.With ESD purchasing experience or not, the Consumers value all the purchasing factors with the same importance. 7.The ESD patrons’ concerns of “purchasing process”, “variety of service” and “option of products” are influenced by their different age. And their occupations influence their concerns about “variety of service”. As for ESD non-patrons, their gender and education influence their concerns about “distinctive products and service”. “efficiency of purchasing process” is influenced by the difference in monthly income. 8.The area of residence, Internet connection speed, and the period in history of contacting Internet do not influence the ESD consumers’ concerns of purchasing factors.
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Lee, Wen-Ming, i 李文明. "A Study of ESD Reliability Analysis in". Thesis, 2000. http://ndltd.ncl.edu.tw/handle/62021679566996546225.
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碩士大葉大學
電機工程研究所
88
The ESD reliability in power MOSFETs will be investigated in this thesis. The testing samples were 100V LD nMOS, 200V LD nMOS, which were designed and developed by ourself, and commercial ICs which were consisted of IRF640, RFW2N06RLE and RLP03N06CLE. From the experimental results, ESD zap pulses at the gate terminal will cause electrons or holes trapped in the gate oxide and lossing the Si-SiO2 interface integrity, especially for the 100V LD nMOS, 200V LD nMOS, and IRF640, in which they do not have any ESD protection circuit. Electrons or holes trapping in SiO2 layer will be caused the threshold voltage increasing or reduction, and even resulted in electron mobility degradation. The RFW2N06RLE and RLP03N06CLE power VDMOS ICs which with different kinds of ESD protection circuit are less influenced by ESD pulses experimentally. Moreover, in some situation the latent damage of electrostatic discharge in a power MOSFET can’t easily find out immediately. Eventually, in order to make sure a good reliability and long lifetime of power MOSFETs, the ESD protection circuit design to prevent ESD damages in a power MOSFET is necessary.
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Chen, Ming Hum, i 陳銘輝. "The ESD Protection Design of Lateral DMOSFETs". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/33355042408370259206.
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碩士大葉大學
電機工程學系碩士班
94
In recent years, many electric systems, such as automatic electronics, power switches, power rectifiers, and display drivers, have widely used power MOSFETs . In the future, the electric industry will develop power MOSFETs into high voltage, high current, and high speed switch modules. However, the problems of ESD still exist and are even more serious than intelligent circuit in low voltage process. Because electrical static discharge (ESD) problems are getting more and more serious, design of traditional ESD devices mostly utilizes trial and error, experimental measurements, or equal circuit simulations with SPICE to acquire proper protection devices. This research used computer simulation software TSUPREM-4 and MEDICI to simulate and improve the electrical property of device and to design a set of ESD protection circuits. Besides, this study also used the comparison results of the SCR layout parameters to make the electrical property of device performance meet the Design Window range and to reach the optimum of the ESD protection.
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Hsu, Pei-Fung, i 徐培峰. "Investigation on ESD Sensor by Liquid Crystal". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/wvkhn6.
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47
Lee, Zon-Lon, i 李宗隆. "ESD Impacts on Low Dropout Voltage Circuit". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/54058928376807814049.
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碩士國立交通大學
電機學院光電顯示科技產業專班
96
The thesis proposes a low-dropout (LDO) regulator with ESD Impacts. Thus, the content of this thesis contains two parts. The first part discusses the design of a low-dropout regulator. With the exponentially increasing of portable battery-powered electronic equipments, such as mobile phones, digital cameras and so on, power management has becoming more and more important and popular. The design of low dropout regulators is widely used in power management since it has a better load transient response, less output noise, and few off-chip components compared to the design of switch-mode regulators. Stability is an important issue in the design of LDO linear regulators. In the conventional architecture, the key factors affecting the system stability are the wide load current range and the value of the output capacitor. Therefore, there exist many proposed compensation techniques to stabilize and improve the whole system. According to the type of output capacitor, LDO regulators can be simply classified into two groups: LDOs with off-chip or on-chip output capacitor. These LDO linear regulators with off-chip capacitor need a large capacitance at output node to generate a dominant pole at low frequency to achieve the stability. They are mostly used for supplying the system with the characteristic of low quiescent current at light loads owing to the current efficient buffer used in the LDOs. The other LDO regulators use an on-chip small output capacitor based on the Miller-compensated technique. Thus, the capacitor can be integrated into the chip, which has the advantage of the saving the footprint area. This type of capacitor-free LDOs is well suited as a stable dc voltage supply for portable electronic devices. The second part of this thesis discusses how ESD impacts the low-dropout regulators. In some situation, the latent damage of electrostatic discharge in a power MOSFET can't easily find out immediately. Eventually, in order to make sure a good reliability and long lifetime of power MOSFETs, the ESD protection circuit design is needed to prevent ESD damages in a power MOSFET design. This thesis provides the reliability engineers of integrated circuit a most important concept of ESD design of power IC. The improvement of the ESD will enhance the reliability of integrated circuit in power IC designs.
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Tsai, Ming-Yuan, i 蔡明圜. "An ESD Protection Design of LCD Drivers". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/26217304903479450127.
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碩士國立聯合大學
電子工程學系碩士班
95
In recent years, industries of LCD (Liquid Crystal Display) be progressed very quickly. When dots per inch (dpi), brightness and responding speed of LCDs are improved in every generation, the LCD driver IC must develop in the trend of high frequency and high voltage. Thus, the LCD driver IC must be met with high speed scanning and fast driving properties. By using the high-voltage property of LDMOS to act as a high-voltage devices in LCD driver ICs, in which it will be protected with an adjusting parameter of SCR device. The process simulator (TSUPRE-4) and device simulator (MEDICI) are used to simulate and evaluate the electrical property of high-voltage power device and to design an ESD protection element in this thesis. Eventually, a suitable trigger voltage and high holding voltage of SCR is used to act as an ESD protector which is very conformable for the request of LCD driver ICs.
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Lai, Po-Ching, i 賴柏青. "Theoretical Analysis and Measurement for ESD Phenomenon". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/96040789048522761061.
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碩士國立中山大學
電機工程學系研究所
94
The trends of present design in electronic systems are towards high speed, small size, and lower voltage levels. The noise immunity of high speed digital circuit decreases. ESD problem becomes more and more important for electric products because of the triboelectricity caused by human body with synthetic material. In this thesis we introduce the phenomenon in real life ESD caused by a charged human body source. Then we provide a good measurement method of ESD which enhances the repetition that gives a reliable and accurate result. Finally we try to build the numerical model for the air and contact discharge simulation by FDTD to provide a good measurement validation.
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Yeh, Chun-Liang, i 葉俊良. "Design and Analysis of ESD Protection Circuit". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/74348641225871249510.
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碩士逢甲大學
電子工程所
93
In this proposal, we would be introducing a biasing circuit, which clamps the gate voltage when threshold reaches the maximum range. On the other hand, we use an N-WELL resistor to increase the resistance between gate and drain to allow ESD current flow to the wide bulk. This can improve the ESD protection level.