Rozprawy doktorskie: „Embedded computer systems”

1

Finney, James. "Autocoding methods for networked embedded systems". Thesis, University of Warwick, 2009. http://wrap.warwick.ac.uk/36892/.

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The volume and complexity of software is increasing; presenting developers with an ever increasing challenge to deliver a system within the agreed timescale and budget [1]. With the use of Computer-Aided Software Engineering (CASE) tools for requirements management, component design, and software validation the risks to the project can be reduced. This project focuses on Autocoding CASE tools, the methods used by such tools to generate the code, and the features these tools provide the user. The Extensible Stylesheet Language Transformation (XSLT) based autocoding method used by Rapicore in their NetGen embedded network design tool was known to have a number of issues and limitations. The aim of the research was to identify these issues and develop an innovative solution that would support current and future autocoding requirements. Using the literature review and a number of practical projects, the issues with the XSLT-based method were identified. These issues were used to define the requirements with which a more appropriate autocoding method was researched and developed. A more powerful language was researched and selected, and with this language a prototype autocoding platform was designed, developed, validated, and evaluated. The work concludes that the innovative use and integration of programmer-level Extensible Markup Language (XML) code descriptions and PHP scripting has provided Rapicore with a powerful and flexible autocoding platform to support current and future autocoding application requirements of any size and complexity.

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Thomas, Sam Lloyd. "Backdoor detection systems for embedded devices". Thesis, University of Birmingham, 2018. http://etheses.bham.ac.uk//id/eprint/8365/.

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A system is said to contain a backdoor when it intentionally includes a means to trigger the execution of functionality that serves to subvert its expected security. Unfortunately, such constructs are pervasive in software and systems today, particularly in the firmware of commodity embedded systems and “Internet of Things” devices. The work presented in this thesis concerns itself with the problem of detecting backdoor-like constructs, specifically those present in embedded device firmware, which, as we show, presents additional challenges in devising detection methodologies. The term “backdoor”, while used throughout the academic literature, by industry, and in the media, lacks a rigorous definition, which exacerbates the challenges in their detection. To this end, we present such a definition, as well as a framework, which serves as a basis for their discovery, devising new detection techniques and evaluating the current state-of-the-art. Further, we present two backdoor detection methodologies, as well as corresponding tools which implement those approaches. Both of these methods serve to automate many of the currently manual aspects of backdoor identification and discovery. And, in both cases, we demonstrate that our approaches are capable of analysing device firmware at scale and can be used to discover previously undocumented real-world backdoors.

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Tosun, Suleyman. "Reliability-centric system design for embedded systems". Related electronic resource: Current Research at SU : database of SU dissertations, recent titles available full text, 2005. http://wwwlib.umi.com/cr/syr/main.

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Van, Riet F. A. "LF : a language for reliable embedded systems". Thesis, Stellenbosch : Stellenbosch University, 2001. http://hdl.handle.net/10019.1/52322.

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Thesis (MSc)--University of Stellenbosch, 2001.
ENGLISH ABSTRACT: Computer-aided verification techniques, such as model checking, are often considered essential to produce highly reliable software systems. Modern model checkers generally require models to be written in eSP-like notations. Unfortunately, such systems are usually implemented using conventional imperative programming languages. Translating the one paradigm into the other is a difficult and error prone process. If one were to program in a process-oriented language from the outset, the chasm between implementation and model could be bridged more readily. This would lead to more accurate models and ultimately more reliable software. This thesis covers the definition of a process-oriented language targeted specifically towards embedded systems and the implementation of a suitable compiler and run-time system. The language, LF, is for the most part an extension of the language Joyce, which was defined by Brinch Hansen. Both LF and Joyce have features which I believe make them easier to use than other esp based languages such as occam. An example of this is a selective communication primitive which allows for both input and output guards which is not supported in occam. The efficiency of the implementation is important. The language was therefore designed to be expressive, but constructs which are expensive to implement were avoided. Security, however, was the overriding consideration in the design of the language and runtime system. The compiler produces native code. Most other esp derived languages are either interpreted or execute as tasks on host operating systems. Arguably this is because most implementations of esp and derivations thereof are for academic purposes only. LF is intended to be an implementation language. The performance of the implementation is evaluated in terms of practical metries such as the time needed to complete communication operations and the average time needed to service an interrupt.
AFRIKAANSE OPSOMMING: Rekenaar ondersteunde verifikasietegnieke soos programmodellering, is onontbeerlik in die ontwikkeling van hoogs betroubare programmatuur. In die algemeen, aanvaar programme wat modelle toets eSP-agtige notasie as toevoer. Die meeste programme word egter in meer konvensionele imperatiewe programmeertale ontwikkel. Die vertaling vanuit die een paradigma na die ander is 'n moelike proses, wat baie ruimte laat vir foute. Indien daar uit die staanspoor in 'n proses gebaseerde taal geprogrammeer word, sou die verwydering tussen model en program makliker oorbrug kon word. Dit lei tot akkurater modelle en uiteindelik tot betroubaarder programmatuur. Die tesis ondersoek die definisie van 'n proses gebaseerde taal, wat gemik is op ingebedde programmatuur. Verder word die implementasie van 'n toepaslike vertaler en looptyd omgewing ook bespreek. Die taal, LF, is grotendeels gebaseer op Joyce, wat deur Brinch Hansen ontwikkel is. Joyce en op sy beurt LF, is verbeterings op ander esp verwante tale soos occam. 'n Voorbeeld hiervan is 'n selektiewe kommunikasieprimitief wat die gebruik van beide toevoer- en afvoerwagte ondersteun. Omdat 'n effektiewe implementasie nagestreef word, is die taalontwerp om so nadruklik moontlik te wees, sonder om strukture in te sluit wat oneffektief is om te implementeer. Sekuriteit was egter die oorheersende oorweging in die ontwerp van die taal en looptyd omgewing. Die vertaler lewer masjienkode, terwyl die meeste ander implementasies van eSP-agtige tale geinterpreteer word of ondersteun word as prosesse op 'n geskikte bedryfstelsel- die meeste eSP-agtige tale word slegs vir akademiese doeleindes aangewend. LF is by uitstek ontwerp as implementasie taal. Die evaluasie van die stelsel se werkverrigting is gedoen aan die hand van praktiese maatstawwe soos die tyd wat benodig word vir kommunikasie, sowel as die gemiddelde tyd benodig vir die hantering van onderbrekings.

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Saha, Sankalita. "Design methodology for embedded computer vision systems". College Park, Md.: University of Maryland, 2007. http://hdl.handle.net/1903/7748.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2007.
Thesis research directed by: Dept. of Computer and Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

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Lessner, Dirk. "Network security for embedded systems /". [St. Lucia, Qld.], 2005. http://adt.library.uq.edu.au/public/adt-QU20060215.160952/index.html.

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Ackerman, M. C. (Marthinus Casper). "Kernel support for embedded reactive systems". Thesis, Stellenbosch : Stellenbosch University, 1993. http://hdl.handle.net/10019.1/58022.

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Thesis (MSc)--Stellenbosch University , 1993.
ENGLISH ABSTRACT: Reactive systems are event driven state machines which usually do not terminate, but remain in perpetual interaction with their environment. Such systems usually interact 'With devices which introduce a high degree of concurrency and some real time constraints to the system. Because of the concurrent nature of reactive systems they are commonly implemented as communicating concurrent processes on one or more processors. Jeffay introduces a design paradigm which requires consumer processes to consume messages faster than they are produced by producer processes. If this is guaranteed, the real time constraints of such .. system are always met, and the correctness of the process interaction is guaranteed in terms of the message passing semantics. I developed the ESE kernel, which supports Jeffay systems by providing lightweight processes which communicate over asynchronous channels. Processes are scheduled non-preemptively according to the earliest deadline first policy when they have messages pending on their input channels. The Jeffay design method and the ESE kernel have been found to be highly suitable to implement embedded reactive systems. The general requirements of embedded reactive systems, and kernel support required by such systems, are discussed.
AFRIKAANSE OPSOMMING: Reaktiewe stelsels is toeatandsoutomate wat aangedryf word deur gebeure in hul omgewins. So 'n stelsel termineer gewoonlik nie, maar bly in 'n voortdurende wisselwerking met toestelle in sy omgewing. Toestelle in die omgewing van 'n reaktiewe stelsel veroorsaak in die algemeen 'n hoë mate van gelyklopendheid in die stelsel, en plaas gewoonlik sekere intydse beperkings op die stelsel. Gelyklopende stelsels word gewoonlik as stelsel. van kommunikerende prosesse geïmplementeer op een of meer prosessors. Jeffay beskryf 'n ontwerpsmetodologie waarvolgens die ontvanger van boodskappe hulle vinniger moet verwerk as wat die sender hulle kan stuur. Indien hierdie gedrag tussen alle pare kommunikerende prosesse gewaarborg kan word, sal die stelsel altyd sy intydse beperkings gehoorsaam, en word die korrektheid van interaksies tussen prosesse deur die semantiek van die boodskapwisseling gewaarborg. Die "ESE" bedryfstelselkern wat ek ontwikkel het, ondersteun stelsels wat ontwerp en geïmplementeer word volgens Jeffay se metode. Prosesse kommunikeer oor asinkrone kanale, en die ontvanger van die boodskap met die vroegste keertyd word altyd eerste geskeduleer. Jeffay se ontwerpsmetode en die "ESE" kern blyk in die praktyk baie geskik te wees vir reaktiewe stelsels wat as substelsels van groter stelsels uitvoer. Die vereistes van reaktiewe substelsels, en die kemondersteuning wat daarvoor nodig is, word bespreek.

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8

Burgess, Peter. "A testbed for embedded systems". Thesis, University of St Andrews, 1994. http://hdl.handle.net/10023/13457.

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Testing and Debugging are often the most difficult phase of software development. This is especially true of embedded systems which are usually concurrent, have real-time performance and correctness constraints and which execute in the field in an environment which may not permit internal scrutiny of the software behaviour. Although good software engineering practices help, they will never eliminate the need for testing and debugging. This is because failings in the specification and design are often only discovered through testing and understanding these failings and how to correct them comes from debugging. These observations suggest that embedded software should be designed in a way which makes testing and debugging easier and that tools which support these activities are required. Due to the often hostile environment in which the finished embedded system will function, it is necessary to have a platform which allows the software to be developed and tested "in vitro". The Testbed system achieves these goals by providing dynamic modification and process migration facilities for use during development as well as powerful monitoring and background debugging support. These facilities are built on a basic run-time harness supporting an event-driven programming model with a global communication mechanism. This programming model is well suited to the reactive nature of embedded systems. The main research contributions of this work are in the areas of finding deadlock-free, path-optimal routings for networks and of dynamic modification with automated conversion of data which may include pointers.

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9

Wallace, Malcolm. "Functional programming and embedded systems". Thesis, University of York, 1995. http://etheses.whiterose.ac.uk/10807/.

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Cortés, Luis Alejandro. "A Petri Net based Modeling and Verification Technique for Real-Time Embedded Systems". Licentiate thesis, Linköping University, Linköping University, ESLAB - Embedded Systems Laboratory, 2001. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5751.

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Embedded systems are used in a wide spectrum of applications ranging from home appliances and mobile devices to medical equipment and vehicle controllers. They are typically characterized by their real-time behavior and many of them must fulfill strict requirements on reliability and correctness.

In this thesis, we concentrate on aspects related to modeling and formal verification of realtime embedded systems.

First, we define a formal model of computation for real-time embedded systems based on Petri nets. Our model can capture important features of such systems and allows their representations at different levels of granularity. Our modeling formalism has a welldefined semantics so that it supports a precise representation of the system, the use of formal methods to verify its correctness, and the automation of different tasks along the design process.

Second, we propose an approach to the problem of formal verification of real-time embedded systems represented in our modeling formalism. We make use of model checking to prove whether certain properties, expressed as temporal logic formulas, hold with respect to the system model. We introduce a systematic procedure to translate our model into timed automata so that it is possible to use available model checking ools. Various examples, including a realistic industrial case, demonstrate the feasibility of our approach on practical applications.

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Sundmark, Daniel. "Structural System-Level Testing of Embedded Real-Time Systems". Doctoral thesis, Västerås : School of Innovation, Design and Engineering, Mälardalen University, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-488.

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Koltes, Andreas. "Reconfigurable memory systems for embedded microprocessors". Thesis, University of Cambridge, 2015. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.709244.

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Carlson, Jan. "Event Pattern Detection for Embedded Systems". Doctoral thesis, Västerås : Department of Computer Science and Electronics, Mälardalen University, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-231.

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Hamette, Patrick de la. "Embedded stereo vision systems for mobile human-computer interaction /". Zürich : ETH, 2008. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=18075.

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Bartzoudis, Nikolaos. "Using embedded hardware monitor cores in critical computer systems". Thesis, Loughborough University, 2006. https://dspace.lboro.ac.uk/2134/33928.

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The integration of FPGA devices in many different architectures and services makes monitoring and real time detection of errors an important concern in FPGA system design. A monitor is a tool, or a set of tools, that facilitate analytic measurements in observing a given system. The goal of these observations is usually the performance analysis and optimisation, or the surveillance of the system. However, System-on-Chip (SoC) based designs leave few points to attach external tools such as logic analysers. Thus, an embedded error detection core that allows observation of critical system nodes (such as processor cores and buses) should enforce the operation of the FPGA-based system, in order to prevent system failures. The core should not interfere with system performance and must ensure timely detection of errors. This thesis is an investigation onto how a robust hardware-monitoring module can be efficiently integrated in a target PCI board (with FPGA-based application processing features) which is part of a critical computing system.

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Janapsatya, Andhi Computer Science &amp Engineering Faculty of Engineering UNSW. "Optimization of instruction memory for embedded systems". Awarded by:University of New South Wales. School of Computer Science and Engineering, 2005. http://handle.unsw.edu.au/1959.4/24210.

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This thesis presents methodologies for improving system performance and energy consumption by optimizing the memory hierarchy performance. The processor-memory performance gap is a well-known problem that is predicted to get worse, as the performance gap between processor and memory is widening. The author describes a method to estimate the best L1 cache configuration for a given application. In addition, three methods are presented to improve the performance and reduce energy in embedded systems by optimizing the instruction memory. Performance estimation is an important procedure to assess the performance of the system and to assess the effectiveness of any applied optimizations. A cache memory performance estimation methodology is presented in this thesis. The methodology is designed to quickly and accurately estimate the performance of multiple cache memory configurations. Experimental results showed that the methodology is on average 45 times faster compared to a widely used tool (Dinero IV). The first optimization method is a software-only method, called code placement, was implemented to improve the performance of instruction cache memory. The method involves careful placement of code within memory to ensure high cache hit rate when code is brought into the cache memory. Code placement methodology aims to improve cache hit rates to improve cache memory performance. Experimental results show that by applying the code placement method, a reduction in cache miss rate by up to 71%, and energy consumption reduction of up to 63% are observed when compared to application without code placement. The second method involves a novel architecture for utilizing scratchpad memory. The scratchpad memory is designed as a replacement of the instruction cache memory. Hardware modification was designed to allow data to be written into the scratchpad memory during program execution, allowing dynamic control of the scratchpad memory content. Scratchpad memory has a faster memory access time and a lower energy consumption per access compared to cache memory; the usage of scratchpad memory aims to improve performance and lower energy consumption of systems compared to system with cache memory. Experimental results show an average energy reduction of 26.59% and an average performance improvement of 25.63% when compared to a system with cache memory. The third is an application profiling method using statistical information to identify application???s hot-spots. Application profiling is important for identifying section in the application where performance degradation might occur and/or where maximum performance gain can be obtained through optimization. The method was applied and tested on the scratchpad based system described in this thesis. Experimental results show the effectiveness of the analysis method in reducing energy and improving performance when compared to previous method for utilizing the scratchpad memory based system (average performance improvement of 23.6% and average energy reduction of 27.1% are observed).

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Gaikwad, Anish Madhukar. "Development of a sag monitoring instrument based on an embedded system platform". Master's thesis, Mississippi State : Mississippi State University, 2002. http://library.msstate.edu/etd/show.asp?etd=etd-04032002-105918.

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Cortés, Luis Alejandro. "Verification and Scheduling Techniques for Real-Time Embedded Systems". Doctoral thesis, Linköping University, Linköping University, ESLAB, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5023.

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Embedded computer systems have become ubiquitous. They are used in a wide spectrum of applications, ranging from household appliances and mobile devices to vehicle controllers and medical equipment. This dissertation deals with design and verification of embedded systems, with a special emphasis on the real-time facet of such systems, where the time at which the results of the computations are produced is as important as the logical values of these results. Within the class of real-time systems two categories, namely hard real-time systems and soft real-time systems, are distinguished and studied in this thesis.

First, we propose modeling and verification techniques targeted towards hard real-time systems, where correctness, both logical and temporal, is of prime importance. A model of computation based on Petri nets is defined. The model can capture explicit timing information, allows tokens to carry data, and supports the concept of hierarchy. Also, an approach to the formal verification of systems represented in our modeling formalism is introduced, in which model checking is used to prove whether the system model satisfies its required properties expressed as temporal logic formulas. Several strategies for improving verification efficiency are presented and evaluated.

Second, we present scheduling approaches for mixed hard/soft real-time systems. We study systems that have both hard and soft real-time tasks and for which the quality of results (in the form of utilities) depends on the completion time of soft tasks. Also, we study systems for which the quality of results (in the form of rewards) depends on the amount of computation allotted to tasks. We introduce quasi-static techniques, which are able to exploit at low cost the dynamic slack caused by variations in actual execution times, for maximizing utilities/rewards and for minimizing energy.

Numerous experiments, based on synthetic benchmarks and realistic case studies, have been conducted in order to evaluate the proposed approaches. The experimental results show the merits and worthiness of the techniques introduced in this thesis and demonstrate that they are applicable on real-life examples.

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Pattnaik, Aliva. "Fault propagation analysis of large-scale, networked embedded systems". Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/42918.

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In safety-critical, networked embedded systems, it is important that the way in which a fault(s) in one component of the system can propagate throughout the system to other components is analyzed correctly. Many real-world systems, such as modern aircrafts and automobiles, use large-scale networked embedded systems with complex behavior. In this work, we have developed techniques and a software tool, FauPA, that uses those techniques to automate fault-propagation analysis of large-scale, networked embedded systems such as those used in modern aircraft. This work makes three main contributions. 1. Fault propagation analyses. We developed algorithms for two types of analyses: forward analysis and backward analysis. For backward analysis, we developed two techniques: a naive algorithm and an algorithm that uses Datalog. 2. A system description language. We developed a language that we call Communication System Markup Language (CSML) based on XML. A system can be specified concisely and at a high-level in CSML. 3. A GUI-based display of the system and analysis results. We developed a GUI to visualize the system that is specified in CSML. The GUI also lets the user visualize the results of fault-propagation analyses.

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Ispir, Mustafa. "Test Driven Development Of Embedded Systems". Master's thesis, METU, 2004. http://etd.lib.metu.edu.tr/upload/12605630/index.pdf.

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In this thesis, the Test Driven Development method (TDD) is studied for use in developing embedded software. The required framework is written for the development environment Rhapsody. Integration of TDD into a classical development cycle, without necessitating a transition to agile methodologies of software development and required unit test framework to apply TDD to an object oriented embedded software development project with a specific development environment and specific project conditions are done in this thesis. A software tool for unit testing is developed specifically for this purpose, both to support the proposed approach and to illustrate its application. The results show that RhapUnit supplies the required testing functionality for developing embedded software in Rhapsody with TDD. Also, development of RhapUnit is a successful example of the application of TDD.

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Schmitz, Marcus Thomas. "Energy minimisation techniques for distributed embedded systems". Thesis, University of Southampton, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.274048.

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Kim, Jeongwook. "Genetic algorithms for smart embedded systems". Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13886.

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Almeida, Jose Carlos Alves de. "Software architecture for distributed real-time embedded systems". Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1998. http://handle.dtic.mil/100.2/ADA355809.

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Thesis (M.S. in Computer Science) Naval Postgraduate School, September 1998.
"September 1998." Thesis advisor(s): Man-Tak Shing, Michael Holden. Includes bibliographical references (p. 121-123). Also available online.

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Hines, Kenneth J. "Coordination-centric debugging for heterogeneous distributed embedded systems /". Thesis, Connect to this title online; UW restricted, 2000. http://hdl.handle.net/1773/6914.

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Ortega, Ross Benito. "Communication synthesis and interface synthesis for embedded systems /". Thesis, Connect to this title online; UW restricted, 2000. http://hdl.handle.net/1773/6870.

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Okyay, Mehmet Onur Aytaç Sıtkı. "A portable real-time operating system for embedded platforms/". [s.l.]: [s.n.], 2004. http://library.iyte.edu.tr/tezler/master/bilgisayaryazilimi/T000477.doc.

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Brockway, Michael J. "A compositional analysis of broadcasting embedded systems". Thesis, Northumbria University, 2010. http://nrl.northumbria.ac.uk/2967/.

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This work takes as its starting point D Kendall's CANdle/bCANdle algebraic framework for formal modelling and specification of broadcasting embedded systems based on CAN networks. Checking real-time properties of such systems is beset by problems of state-space explosion and so a scheme is given for recasting systems specified in Kendall's framework as parallel compositions of timed automata; a CAN network channel is modelled as an automaton. This recasting is shown to be bi-similar to the original bCANdle model. In the recast framework,"compositionality" theorems allow one to infer that a model of a system is simulated by some abstraction of the model, and hence that properties of the model expressible in ACTL can be inferred from analogous properties of the abstraction. These theorems are reminiscent of "assume-guarantee" reasoning allowing one to build simulations component-wise although, unfortunately, components participating in a "broadcast" are required to be abstracted "atomically". Case studies are presented to show how this can be used in practice, and how systems which take impossibly long to model-check can tackled by compositional methods. The work is of broader interest also, as the models are built as UPPAAL systems and the compositionality theorems apply to any UPPAAL system in which the components do not share local variables. The method could for instance extend to systems using some network other than CAN, provided it can be modelled by timed automata. Possibilities also exist for building it into an automated tool, complementing other methods such as counterexample- guided abstraction refinement.

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Lee, Dongwon. "High-performance computer system architectures for embedded computing". Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/42766.

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The main objective of this thesis is to propose new methods for designing high-performance embedded computer system architectures. To achieve the goal, three major components - multi-core processing elements (PEs), DRAM main memory systems, and on/off-chip interconnection networks - in multi-processor embedded systems are examined in each section respectively. The first section of this thesis presents architectural enhancements to graphics processing units (GPUs), one of the multi- or many-core PEs, for improving performance of embedded applications. An embedded application is first mapped onto GPUs to explore the design space, and then architectural enhancements to existing GPUs are proposed for improving throughput of the embedded application. The second section proposes high-performance buffer mapping methods, which exploit useful features of DRAM main memory systems, in DSP multi-processor systems. The memory wall problem becomes increasingly severe in multiprocessor environments because of communication and synchronization overheads. To alleviate the memory wall problem, this section exploits bank concurrency and page mode access of DRAM main memory systems for increasing the performance of multiprocessor DSP systems. The final section presents a network-centric Turbo decoder and network-centric FFT processors. In the era of multi-processor systems, an interconnection network is another performance bottleneck. To handle heavy communication traffic, this section applies a crossbar switch - one of the indirect networks - to the parallel Turbo decoder, and applies a mesh topology to the parallel FFT processors. When designing the mesh FFT processors, a very different approach is taken to improve performance; an optical fiber is used as a new interconnection medium.

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Lim, Jun Bum. "RaPTEX: Rapid Prototyping Tool for Embedded Communication Systems". NCSU, 2007. http://www.lib.ncsu.edu/theses/available/etd-04262007-220713/.

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Advances in microprocessors, memory, and radio technology have enabled the emergence of embedded systems that rely on communication systems to exchange information and coordinate their activity in spatially distributed applications. Developing embedded communication systems that are efficient and reliable, is a challenge due to the trade-offs imposed by the conflicts between application requirements and hardware constraints. In this thesis, we present RaPTEX, an integrated development environment (IDE) for embedded communication systems. RaPTEX consists of three major subsystems: a graphical module to facilitate component composition, code generation with access to component-level parameters, and a performance evaluation framework for allowing system designers to explore what-if scenarios and clearly expose the trade-offs of their choices. We also present two case studies of developing wireless sensor network applications using RaPTEX.

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Hänninen, Kaj. "Introducing a Memory Efficient Execution Model in a Tool-Suite for Real-Time Systems /". Västerås : Department of Computer Science and Electronics, Mälardalen University, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-152.

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Chen, Dejiu. "Systems Modeling and Modularity Assessment for Embedded Computer Control Applications". Doctoral thesis, KTH, Maskinkonstruktion, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3792.

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AbstractThe development of embedded computer control systems(ECS) requires a synergetic integration of heterogeneoustechnologies and multiple engineering disciplines. Withincreasing amount of functionalities and expectations for highproduct qualities, short time-to-market, and low cost, thesuccess of complexity control and built-in flexibility turn outto be one of the major competitive edges for many ECS products.For this reason, modeling and modularity assessment constitutetwo critical subjects of ECS engineering.In the development ofECS, model-based design is currently being exploited in most ofthe sub-systems engineering activities. However, the lack ofsupport for formalization and systematization associated withthe overall systems modeling leads to problems incomprehension, cross-domain communication, and integration oftechnologies and engineering activities. In particular, designchanges and exploitation of "components" are often risky due tothe inability to characterize components' properties and theirsystem-wide contexts. Furthermore, the lack of engineeringtheories for modularity assessment in the context of ECS makesit difficult to identify parameters of concern and to performearly system optimization. This thesis aims to provide a more complete basis for theengineering of ECS in the areas of systems modeling andmodularization. It provides solution domain models for embeddedcomputer control systems and the software subsystems. Thesemeta-models describe the key system aspects, design levels,components, component properties and relationships with ECSspecific semantics. By constituting the common basis forabstracting and relating different concerns, these models willalso help to provide better support for obtaining holisticsystem views and for incorporating useful technologies fromother engineering and research communities such as to improvethe process and to perform system optimization. Further, amodeling framework is derived, aiming to provide a perspectiveon the modeling aspect of ECS development and to codifyimportant modeling concepts and patterns. In order to extendthe scope of engineering analysis to cover flexibility relatedattributes and multi-attribute tradeoffs, this thesis alsoprovides a metrics system for quantifying componentdependencies that are inherent in the functional solutions.Such dependencies are considered as the key factors affectingcomplexity control, concurrent engineering, and flexibility.The metrics system targets early system-level design and takesinto account several domain specific features such asreplication and timing accuracy. Keywords:Domain-Specific Architectures, Model-basedSystem Design, Software Modularization and Components, QualityMetrics.
QC 20100524

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Paci, Francesco <1985&gt. "Electronic Systems with High Energy Efficiency for Embedded Computer Vision". Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2017. http://amsdottorato.unibo.it/7920/1/PhDThesis.pdf.

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Electronic systems are now widely adopted in everyday use. Moreover, nowadays there is an extensive use of embedded wearable and portable devices from industrial to consumer applications. The growing demand of embedded devices and applications has opened several new research fields due to the need of low power consumption and real time responsiveness. Focusing on this class of devices, computer vision algorithms are a challenging application target. In embedded computer vision hardware and software design have to interact to meet application specific requirements. The focus of this thesis is to study computer vision algorithms for embedded systems. The presented work starts presenting a novel algorithm for an IoT stationary use case targeting a high-end embedded device class, where power can be supplied to the platform through wires. Moreover, further contributions focus on algorithmic design and optimization on low and ultra-low power devices. Solutions are presented to gesture recognition and context change detection for wearable devices, focusing on first person wearable devices (Ego-Centric Vision), with the aim to exploit more constrained systems in terms of available power budget and computational resources. A novel gesture recognition algorithm is presented that improves state of art approaches. We then demonstrate the effectiveness of low resolution images exploitation in context change detection with real world ultra-low power imagers. The last part of the thesis deals with more flexible software models to support multiple applications linked at runtime and executed on Cortex-M device class, supporting critical isolation features typical of virtualization-ready CPUs on low-cost low-power microcontrollers and covering some defects in security and deployment capabilities of current firmwares.

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Mendelsohn, Daniel L. M. Eng Massachusetts Institute of Technology. "An automatic grader for embedded systems education". Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/119535.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 65-66).
In this thesis, we introduce MicroGrader, an automated grader for embedded systems projects. The grader runs on a laptop or desktop computer, while the embedded system being evaluated runs on a microcontroller. By implementing a custom communication protocol between the grader and the embedded system, we enable the grader to inject test inputs and observe the resulting outputs. We describe a data structure for defining the technical requirements of an assignment. This data structure is meant to be simple to use, but highly expressive to allow for a wide range of possible assignments. We also outline the implementation of the MicroGrader system and the underlying communication protocol. We discuss the constraints that this implementation imposes on instructors. Finally, we describe a method of automatically constructing tests using a staff-built reference solution for a generic assignment.
by Daniel L. Mendelsohn.
M. Eng.

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34

Jain, Prabhat. "Software-assisted cache mechanisms for embedded systems". Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/42906.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (leaves 120-135).
Embedded systems are increasingly using on-chip caches as part of their on-chip memory system. This thesis presents cache mechanisms to improve cache performance and provide opportunities to improve data availability that can lead to more predictable cache performance. The first cache mechanism presented is an intelligent cache replacement policy that utilizes information about dead data and data that is very frequently used. This mechanism is analyzed theoretically to show that the number of misses using intelligent cache replacement is guaranteed to be no more than the number of misses using traditional LRU replacement. Hardware and software-assisted mechanisms to implement intelligent cache replacement are presented and evaluated. The second cache mechanism presented is that of cache partitioning which exploits disjoint access sequences that do not overlap in the memory space. A theoretical result is proven that shows that modifying an access sequence into a concatenation of disjoint access sequences is guaranteed to improve the cache hit rate. Partitioning mechanisms inspired by the concept of disjoint sequences are designed and evaluated. A profit-based analysis, annotation, and simulation framework has been implemented to evaluate the cache mechanisms. This framework takes a compiled benchmark program and a set of program inputs and evaluates various cache mechanisms to provide a range of possible performance improvement scenarios. The proposed cache mechanisms have been evaluated using this framework by measuring cache miss rates and Instructions Per Clock (IPC) information. The results show that the proposed cache mechanisms show promise in improving cache performance and predictability with a modest increase in silicon area.
by Prabhat Jain.
Ph.D.

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Swart, Riaan. "A language to support verification of embedded software". Thesis, Stellenbosch : Stellenbosch University, 2004. http://hdl.handle.net/10019.1/49823.

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Thesis (MSc)--University of Stellenbosch, 2004.
ENGLISH ABSTRACT: Embedded computer systems form part of larger systems such as aircraft or chemical processing facilities. Although testing and debugging of such systems are difficult, reliability is often essential. Development of embedded software can be simplified by an environment that limits opportunities for making errors and provides facilities for detection of errors. We implemented a language and compiler that can serve as basis for such an experimental environment. Both are designed to make verification of implementations feasible. Correctness and safety were given highest priority, but without sacrificing efficiency wherever possible. The language is concurrent and includes measures for protecting the address spaces of concurrently running processes. This eliminates the need for expensive run-time memory protection and will benefit resource-strapped embedded systems. The target hardware is assumed to provide no special support for concurrency. The language is designed to be small, simple and intuitive, and to promote compile-time detection of errors. Facilities for abstraction, such as modules and abstract data types support implementation and testing of bigger systems. We have opted for model checking as verification technique, so our implementation language is similar in design to a modelling language for a widely used model checker. Because of this, the implementation code can be used as input for a model checker. However, since the compiler can still contain errors, there might be discrepancies between the implementation code written in our language and the executable code produced by the compiler. Therefore we are attempting to make verification of executable code feasible. To achieve this, our compiler generates code in a special format, comprising a transition system of uninterruptible actions. The actions limit the scheduling points present in processes and reduce the different interleavings of process code possible in a concurrent system. Requirements that conventional hardware places on this form of code are discussed, as well as how the format influences efficiency and responsiveness.
AFRIKAANSE OPSOMMING: Ingebedde rekenaarstelsels maak deel uit van groter stelsels soos vliegtuie of chemiese prosesseerfasiliteite. Hoewel toetsing en ontfouting van sulke stelsels moeilik is, is betroubaarheid dikwels onontbeerlik. Ontwikkeling van ingebedde sagteware kan makliker gemaak word met 'n ontwikkelingsomgewing wat geleenthede vir foutmaak beperk en fasiliteite vir foutbespeuring verskaf. Ons het 'n programmeertaal en vertaler geïmplementeer wat as basis kan dien vir so 'n eksperimentele omgewing. Beide is ontwerp om verifikasie van implementasies haalbaar te maak. Korrektheid en veiligheid het die hoogste prioriteit geniet, maar sonder om effektiwiteit prys te gee, waar moontlik. Die taal is gelyklopend en bevat maatreëls om die adresruimtes van gelyklopende prosesse te beskerm. Dit maak duur looptyd-geheuebeskerming onnodig, tot voordeel van ingebedde stelsels met 'n tekort aan hulpbronne. Daar word aangeneem dat die teikenhardeware geen spesiale ondersteuning vir gelyklopendheid bevat nie. Die programmeertaal is ontwerp om klein, eenvoudig en intuïtief te wees, en om vertaaltyd-opsporing van foute te bevorder. Fasiliteite vir abstraksie, byvoorbeeld modules en abstrakte datatipes, ondersteun implementering en toetsing van groter stelsels. Ons het modeltoetsing as verifikasietegniek gekies, dus is die ontwerp van ons programmeertaal soortgelyk aan dié van 'n modelleertaal vir 'n modeltoetser wat algemeen gebruik word. As gevolg hiervan kan die implementasiekode as toevoer vir 'n modeltoetser gebruik word. Omdat die vertaler egter steeds foute kan bevat, mag daar teenstrydighede bestaan tussen die implementasie geskryf in ons implementasietaal, en die uitvoerbare masjienkode wat deur die vertaler gelewer word. Daarom poog ons om verifikasie van die uitvoerbare masjienkode haalbaar te maak. Om hierdie doelwit te bereik, is ons vertaler ontwerp om 'n spesiale formaat masjienkode te genereer bestaande uit 'n oorgangstelsel wat ononderbreekbare (atomiese) aksies bevat. Die aksies beperk die skeduleerpunte in prosesse en verminder sodoende die aantal interpaginasies van proseskode wat moontlik is in 'n gelyklopende stelsel. Die vereistes wat konvensionele hardeware aan dié spesifieke formaat kode stel, word bespreek, asook hoe die formaat effektiwiteit en reageerbaarheid van die stelsel beïnvloed.

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Yilmaz, Ozan. "Ethernet Based Real Time Communications For Embedded Systems". Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/12612136/index.pdf.

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Fast paced improvement of Ethernet technology has also received attention in the industry field like it did in other fields and ways of usage have started to be studied. As it is understood that the standard Ethernet protocols cannot be used due to the unsatisfied real time requirements, industrial and academic researchers have started to develop solutions to overcome this deficiency. In this thesis, the real hardware adaptations of Real Time Ethernet and RTXX protocol algorithms are implemented and their behaviors on the hardware are observed. Each parameter that affects the system&rsquo
s real time behavior is individually examined and the solution proposals are discussed.

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37

Ryu, Soojung. "Storage Management for Embedded SIMD Processors". Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/5122.

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SIMD parallelism offers a high performance and efficient execution approach for today's broad range of portable multimedia consumer products. However, new methods are needed to meet the complex demands of high performance, embedded systems. This research explores new storage management techniques for this focused but critical application. These techniques include memory design exploration based on the application retargeting technique, storage-based systolic instruction broadcast, and systolic virtual memory to improve both the performance and efficiency of embedded SIMD systems. For an efficient storage usage by memory design space exploration in embedded SIMD systems, an analysis method for assessing storage needs and costs of a given application automatically retargeted across a spectrum of storage configuration designs was developed. Using this technique, a SIMD processing element achieves optimal area and energy efficiency with a register file containing between 8 and 12 words for given workload. This configuration is between 15% and 25% more area and energy efficient than other memory configurations being considered. Systolic instruction broadcast is a high performance and area efficient instruction broadcasting scheme with short-wire interconnects by eliminating of wire latency bottleneck found in global instruction broadcast. Three implementation methods are defined and evaluated - software method, 2-write port register file method, and bypass method. In our evaluations, due to the system's short clock cycle time and scheduler, a speedup in system performance of up to 7.5 can be achieved by the year 2010. In addition, speedup of area efficiency also can be achieved up to 7.2 for a given workload. The ability of minimizing off-chip memory access latency while maximizing access frequency by scheduling techniques along with data prefetch techniques in systolic virtual memory mechanism was evaluated using our SIMD-systolic architecture simulator. Results show that, systolic virtual off-chip memory with shared address space can achieve over 50% higher area efficiency than that of an on-chip only system for a matrix multiplication application.

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38

Al-Hasawi, Waleed Isa. "Multiprocessor design for real-time embedded systems". Thesis, Loughborough University, 1987. https://dspace.lboro.ac.uk/2134/7474.

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Chou, Pai Hsiang. "Control composition and synthesis of distributed real-time embedded systems /". Thesis, Connect to this title online; UW restricted, 1998. http://hdl.handle.net/1773/6895.

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Khosla, Vikul. "A concurrent object-oriented approach for requirements analysis and design of embedded systems". Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-02132009-171547/.

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Lynch, Valerie Barbara. "An investigation into the value of embedded software". Thesis, University of Cambridge, 2014. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.648603.

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Groufsky, Michael Edward. "An embedded augmented reality system". Thesis, University of Canterbury. Electrical and Computer Engineer, 2011. http://hdl.handle.net/10092/6259.

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This report describes an embedded system designed to support the development of embedded augmented reality applications. It includes an integrated camera and built-in graphics acceleration hardware. An example augmented reality application serves as a demonstration of how these features are accessed, as well as providing an indication of the performance of the device. The embedded augmented reality development platform consists of the Gumstix Overo computer-on-module paired with the custom-built Overocam camera board. This device offers an ARM Cortex-A8 CPU running at 600 MHZ and 256 MB of RAM, along with the ability to capture VGA video at 30 frames per second. The device runs an operating system based on version 2.6.33 of the Linux kernel. The main feature of the device is the OMAP3530 multimedia applications processor from Texas Instruments. In addition to the ARM CPU, it provides an on-board 2D/3D graphics accelerator and a digital signal processor. It also includes a built-in camera peripheral interface, reducing the complexity of the camera board design. A working example of an augmented reality application is included as a demonstration of the device's capabilities. The application was designed to represent a basic augmented reality task: tracking a single marker and rendering a simple virtual object. It runs at around 8 frames per second when a marker is visible and 13 frames per second otherwise. The result of the project is a self-contained computing platform for vision-based augmented reality. It may either be used as-is or customised with additional hardware peripherals, depending on the requirements of the developer.

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Das, Hitesh K. "Extending UML to include security constraints for embedded systems". University of Cincinnati / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1456848089.

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Graham, Daniel George. "Enhancing The Sensing Capabilities of Mobile and Embedded Systems". W&M ScholarWorks, 2016. https://scholarworks.wm.edu/etd/1477067912.

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In this work, we aim to develop new sensors and sensing platforms that facilitate the development of new mobile and embedded devices. Mobile and embedded devices have become an integral part of our everyday lives and the sensing capabilities of these devices have improved throughout the years. Developing new and innovative sensors and sensing platforms will provide the building blocks for developing new sensing systems. In an effort to facilitate these innovations we have developed two new in-air sonar sensors and a new reconfigurable sensing platform. The first in-air sonar sensor is designed for ranging applications and uses the phone's microphone and rear speaker to generate a wide beam of sound. The second in-air sonar sensor is an external module which uses a narrow beam of sound for high resolution ranging. This ranging information is then combined with orientation data from the phone's gyroscope,magnetometer and accelerometer to generate a two dimensional map of a space. While researching ways of enhancing the sensing capabilities of mobile and embedded devices, we found that the process often requires developing new hardware prototypes. However, developing hardware prototypes is time-consuming. In an effort to lower the barrier to entry for small teams and software researchers, we have developed a new reconfigurable sensing platform that uses a code first approach to embedded design. Instead of designing software to run within the limited constraints of the hardware, our proposed code-first approach allows software researchers to synthesize the hardware configuration that is required to run their software.

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Gunupudi, Vandana Tate Stephen R. "Exploring trusted platform module capabilities a theoretical and experimental study /". [Denton, Tex.] : University of North Texas, 2008. http://digital.library.unt.edu/permalink/meta-dc-6101.

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Eisenstein, Ariana (Ariana J. ). "An FPGA platform for demonstrating embedded vision systems". Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/106024.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 73-75).
This thesis presents an FPGA platform that can be used to enable real-time embedded vision systems, specifically object detection. Interfaces are built between the FPGA and a high definition (1980 x 1080) HDMI camera, an off-chip DRAM, an FMC connector, an SD Card, and an HDMI display. The interface processing includes debayering for the camera input, arbitration for DRAM, and object annotation for the display. The platform must also handle the different clock frequencies of various interfaces. Real-time object detection at 30 frames per second is demonstrated by either connecting the platform to an object detection ASIC via the FMC connector, or directly implementing the object detection RTL on the FPGA. Using this platform, ASICs developed in the Energy-Efficient Multimedia Systems lab can be verified and benchmarked on both live video via the HDMI camera as well as pre-recorded media via an SD Card. Finally, a post-processing filter has been implemented on the FPGA to reduce false positives and interpolate missed object detections by leveraging temporal correlations.
by Ariana Eisenstein.
M. Eng.

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Zhu, Chunlin. "Classify and rank Daikon invariants on embedded systems /". View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?CSED%202009%20ZHUC.

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Næss, Eivind. "Configurable middleware-level intrusion detection support for embedded systems". Online access for everyone, 2004. http://www.dissertations.wsu.edu/Thesis/Spring2004/e%5Fnaess%5F051004.pdf.

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Hiromoto, Masayuki. "LSI design methodology for real-time computer vision on embedded systems". 京都大学 (Kyoto University), 2009. http://hdl.handle.net/2433/126476.

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Kyoto University (京都大学)
0048
新制・課程博士
博士(情報学)
甲第15012号
情博第371号
新制||情||68(附属図書館)
27462
UT51-2009-R736
京都大学大学院情報学研究科通信情報システム専攻
(主査)教授佐藤高史, 教授小野寺秀俊, 教授松山隆司, 准教授越智裕之
学位規則第4条第1項該当

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Waterman, Jason. "Coordinated Resource Management in Networked Embedded Systems". Thesis, Harvard University, 2012. http://dissertations.umi.com/gsas.harvard:10651.

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This dissertation shows that with simple programming abstractions, network-wide resource coordination is efﬁcient and useful for programming embedded sensor networks. Existing systems have focused primarily on managing resources for individual nodes, but a sensor network is not merely a collection of nodes operating independently: it must coordinate behavior across multiple nodes to achieve high efﬁciency. We need tools that can enable system-wide coordination at a higher level of abstraction than what exists today. We present three core contributions. The ﬁrst is a service called IDEA that enables networkwide energy management for sensor networks. It unites energy monitoring, load modeling, and distributed state sharing into a single service that facilitates distributed decision making. Using simulation and testbed results, we show that IDEA enables improvements in network lifetime of up to 35% over approaches that do not consider energy distribution. Our second contribution is Karma, a system for coordinating insect-sized robotic microaerial vehicle (MAV) swarms, an emerging class of mobile sensor networks. Karmas system architecture simpliﬁes the functionality of an individual MAV to a sequence of sensing and actuation commands called behaviors. Each behavior has an associated progress function, a measure of how much of that behavior has been completed. Programming is done by composing behaviors which are coordinated using input from the progress functions. Through simulation and testbed experiments, we demonstrate Karma applications can run on limited resources, are robust to individual MAV failure, and adapt to changes in the environment. Our ﬁnal contribution is Simbeeotic, a testbed for MAV coordination algorithms. MAV sensors must be codesigned with the software and coordination algorithms that depend on them. This requires a testbed capable of simulating sensors to evaluate them before actual hardware is available and the ability to test with real ﬂight dynamics for accurate control evaluation. In addition, simulation should be able to scale to hundreds or thousands of MAVs at a reduced level of ﬁdelity in order to test at scale. We demonstrate that Simbeeotic provides the appropriate level of ﬁdelity to evaluate prototype systems while maintaining the ability to test at scale.
Engineering and Applied Sciences

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