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Silva, Augusto Neutzling. "Syhthesis of thereshold logic based circuits". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/119435.
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Circuitos baseados em portas lógicas de limiar (threshold logic gates – TLG) vem sendo estudados como uma alternativa promissora em relação ao tradicional estilo lógico CMOS, baseado no operadores AND e OR, na construção de circuitos integrados digitais. TLGs são capazes de implementar funções Booleanas mais complexas em uma única porta lógica. Diversos novos dispositivos, candidatos a substituir o transistor MOS, não se comportam como chaves lógicas e são intrinsicamente mais adequados à implementação de TLGs. Exemplos desses dispositivos são os memristores, spintronica, diodos de tunelamento ressonante (RTD), autômatos celulares quânticos (QCA) e dispositivos de tunelamento de elétron único (SET). Para o desenvolvimento de um fluxo de projeto de circuitos integrados baseados em lógica threshold, duas etapas são fundamentais: (1) identificar se uma dada função Booleana corresponde a uma função lógica threshold (TLF), isto é, pode ser implementada em um único TLG e computar os pesos desse TLG; (2) se uma função não é identificada como TLF, outro método de síntese lógica deve construir uma rede de TLGs otimizada que implemente a função. Este trabalho propõe métodos para atacar cada um desses dois problemas, e os resultados superam os métodos do estado-da-arte. O método proposto para realizar a identificação de TLFs é o primeiro método heurístico capaz de identificar todas as funções de cinco e seis variáveis, além de identificar mais funções que os demais métodos existentes quando o número de variáveis aumenta. O método de síntese de redes de TLGs é capaz de sintetizar circuitos reduzindo o número de portas TLG utilizadas, bem como a profundidade lógica e o número de interconexões. Essa redução é demonstrada através da síntese dos circuitos de avaliação da MCNC em comparação com os métodos já propostos na literatura. Tais resultados devem impactar diretamente na área e desempenho do circuito.In this work, a novel method to synthesize digital integrated circuits (ICs) based on threshold logic gates (TLG) is proposed. Synthesis considering TLGs is quite relevant, since threshold logic has been revisited as a promising alternative to conventional CMOS IC design due to its suitability to emerging technologies, such as resonant tunneling diodes, memristors and spintronics devices. Identification and synthesis of threshold logic functions (TLF) are fundamental steps for the development of an IC design flow based on threshold logic. The first contribution is a heuristic algorithm to identify if a function can be implemented as a single TLG. Furthermore, if a function is not detected as a TLF, the method uses the functional composition approach to generate an optimized TLG network that implements the target function. The identification method is able to assign optimal variable weights and optimal threshold value to implement the function. It is the first heuristic algorithm that is not based on integer linear programming (ILP) that is able to identify all threshold functions with up to six variables. Moreover, it also identifies more functions than other related heuristic methods when the number of variables is more than six. Differently from ILP based approaches, the proposed algorithm is scalable. The average execution time is less than 1 ms per function. The second major contribution is the constructive process applied to generate optimized TLG networks taking into account multiple goals and design costs, like gate count, logic depth and number of interconnections. Experiments carried out over MCNC benchmark circuits show an average gate count reduction of 32%, reaching up to 54% of reduction in some cases, when compared to related approaches.
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Gaubatz, Donald Almo. "Logic programming analysis of asynchronous digital circuits". Thesis, University of Cambridge, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.386062.
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Liu, Tai-hung. "Logic synthesis for high-performance digital circuits /". Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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Xia, Yinshui. "Low power design techniques for digital logic circuits". Thesis, Edinburgh Napier University, 2003. http://researchrepository.napier.ac.uk/Output/6887.
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With the rapid increase in the density and the size of chips and systems, area and power dissipation become critical concern in Very Large Scale Integrated (VLSI) circuit design. Low power design techniques are essential for today's VLSI industry. The history of symbolic logic and some typical techniques for finite state machine (FSM) logic synthesis are reviewed. The state assignment is used to optimize area and power dissipation for FSMs. Two cost functions, targeting area and power, are presented. The Genetic Algorithm (GA) is used to search for a good state assignment to minimize the cost functions. The algorithm has been implemented in C. The program can produce better results than NOVA, which is integrated into SIS by DC Berkeley, and other publications both in area and power tested by MCNC benchmarks. Flip-flops are the core components of FSMs. The reduction of power dissipation from flip-flops can save power for digital systems significantly. Three new kinds of flip-flops, called differential CMOS single edge-triggered flip-flop with clock gating, double edge-triggered and multiple valued flip-flops employing multiple valued clocks, are proposed. All circuits are simulated using PSpice. Most researchers have focused on developing low-power techniques in AND/OR or NAND & NOR based circuits. The low power techniques for AND /XOR based circuits are still in their early stage of development. To implement a complex function involving many inputs, a form of decomposition into smaller subfunctions is required such that the subfunctions fit into the primitive elements to be used in the implementation. Best polarity based XOR gate decomposition technique has been developed, which targets low power using Huffman algorithm. Compared to the published results, the proposed method shows considerable improvement in power dissipation. Further, Boolean functions can be expressed by Fixed Polarity Reed-Muller (FPRM) forms. Based on polarity transformation, an algorithm is developed and implemented in C language which can find the best polarity for power and area optimization. Benchmark examples of up to 21 inputs run on a personal computer are given.
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Duncan, Austin H. "Logic Gates Using the Digilent Basys3". Digital Commons @ East Tennessee State University, 2015. https://dc.etsu.edu/honors/311.
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ENTC 3370 teaches students the basics of digital circuits. Until recently the students were taught using an analog device called a Protoboard. With the acquisition of the Digilent Basys3, a digital device, the class will begin to be taught using digital modeling techniques. This is a collection of lab activities designed to be used with the Basys3 within the class. The activities were designed in a way so that students with little programming knowledge could complete the tasks.
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Hacker, Charles Hilton, i n/a. "WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design". Griffith University. School of Engineering, 2001. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20050915.172404.
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This thesis presents an interactive computerised teaching suite developed for the design of combinatorial and sequential logic circuits. This suite fills a perceived gap in the currently available computer-based teaching software for digital logic design. Several existing digital logic educational software are available, however these existing programs were found to be unsuitable for our use in providing alternative mode subject delivery. This prompted the development of a Microsoft Windows TM tutorial suite, called WinLogiLab. WinLogiLab comprises of a set of tutorials that uses student provided input data, to perform the initial design steps for digital Combinatorial and Sequential logic circuits. The combinatorial tutorials are designed to show the link between Boolean Algebra and Digital Logic circuits, and follows the initial design steps: from Boolean algebra, truth tables, to Exact and the Heuristic minimisation techniques, to finally produce the combinatorial circuit. Similarly, the sequential tutorials can design simple State Machine Counters, and can model more complex Finite State Automata.
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Hacker, Charles. "WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design". Thesis, Griffith University, 2001. http://hdl.handle.net/10072/367209.
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This thesis presents an interactive computerised teaching suite developed for the design of combinatorial and sequential logic circuits. This suite fills a perceived gap in the currently available computer-based teaching software for digital logic design. Several existing digital logic educational software are available, however these existing programs were found to be unsuitable for our use in providing alternative mode subject delivery. This prompted the development of a Microsoft Windows TM tutorial suite, called WinLogiLab. WinLogiLab comprises of a set of tutorials that uses student provided input data, to perform the initial design steps for digital Combinatorial and Sequential logic circuits. The combinatorial tutorials are designed to show the link between Boolean Algebra and Digital Logic circuits, and follows the initial design steps: from Boolean algebra, truth tables, to Exact and the Heuristic minimisation techniques, to finally produce the combinatorial circuit. Similarly, the sequential tutorials can design simple State Machine Counters, and can model more complex Finite State Automata.Thesis (Masters)
Master of Philosophy (MPhil)
School of Engineering
Science, Environment, Engineering and Technology
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Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits". Ottawa, 1999.
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Keeble, Clifford George. "The synthesis of self-timed circuits by formal methods". Thesis, University of Southampton, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239920.
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Sah, Puja. "Implementing Digital Logic Design Concepts Using Paper Electronics". Thesis, University of North Texas, 2018. https://digital.library.unt.edu/ark:/67531/metadc1157633/.
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This thesis presents the implementation of some of the basic concepts of digital logic design in a fun and creative way with the help of paper electronics. This involves circuit building on paper using conductive tape or conductive ink and circuit components as electronics craft materials. Paper electronics toolkit called circuit sticker microcontroller which is deployed by a company named Chibitronics and AT89C51 microcontroller were used for the computational functioning of the circuits built on paper. This can be used to teach the fundamentals of digital logic design to the students in their early stage of studies in an attractive way and can help them them gain a better understanding. This thesis can also be helpful in grabbing the attention of high school students and motivate them towards choosing the engineering discipline for their higher studies.
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Machado, Lucas. "Logic decomposition and adaptive clocking for the optimization of digital circuits". Doctoral thesis, Universitat Politècnica de Catalunya, 2019. http://hdl.handle.net/10803/665978.
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Over the course of 60 years, since the invention of the integrated circuit (IC), exponential improvements in cost, performance and power consumption were observed. Such advances have been strongly linked with the continuous reduction of the dimensions in manufactured ICs, but this trend has shown decreasing benefits as fundamental limits are reached.
Notice that such tiny devices have increased variability, which generates unpredictable variations in the behavior of the manufactured devices. These uncertainties are typically addressed by defining margins on the clock period, estimated during the design phase. However, the overly conservative margins produce significant degradations in performance.
Additionally, the evolution that enabled circuits with increasingly higher density of components, also resulted in an extremely complex IC design. At every step, electronic design automation (EDA) tools are challenged to handle this increasing complexity, requiring more powerful techniques to comply with the specification constraints within an affordable runtime.
This thesis investigates alternatives in order to improve power, performance, area, and cost, using established IC manufacturing technologies. Advances in EDA are proposed in three distinct topics: area minimization using Boolean methods, area and delay reduction for designs based on fieldprogrammable gate array (FPGA), and an alternative clocking scheme to reduce timing margins.
The first contribution consists of a technology-independent method for area minimization of combinational logic. Local optimization is applied on and-inverter graphs (AIGs), performing multi-output Boolean decomposition using two-literal divisors, targeting node count reduction.
The second contribution regards two methods targeting technology mapping of FPGAs. On one hand, a functional decomposition approach, which uses the support size as cost function, exploring the inherent characteristics of FPGAs. On the other hand, an approach for recursive remapping, which reduces the structural bias of the subject graph, uses the mapping results as
cost function, and obtains significant reductions in area and delay.
The third contribution evaluates the dynamic variability mitigation and simplification of power delivery networks (PDNs) using an adaptive clocking scheme based on ring oscillator clocks (ROCs). The impact of the PDN parameters and ROC location is investigated, showing potential improvements in performance, leakage power and cost.A lo largo de los 60 años desde la invención del circuito integrado (CI), se han producido mejoras exponenciales en su coste, rendimiento y consumo de energía. Ese progreso esta fuertemente vinculado a la reducción continua de las dimensiones de fabricación de los circuitos integrados, pero esta tendencia ha ido mostrando menos beneficios a medida que se alcanzan límites fundamentales. Estos dispositivos minúsculos tienen una mayor variabilidad, lo que genera variaciones impredecibles en el comportamiento de los dispositivos fabricados. Estas incertidumbres generalmente se abordan mediante la definición de márgenes en el período de reloj, estimado durante la fase de diseño. Sin embargo, márgenes excesivamente conservadores producen degradaciones significativas en el rendimiento. Además, la evolución que permitió crear circuitos con una densidad de componentes cada vez mayor, también incrementado la complejidad de los CI. En cada paso del proceso de diseño, las herramientas de automatización de diseño electrónico (EDA) se enfrentan al desafío de manejar esta complejidad creciente, lo que requiere técnicas más potentes para cumplir con las restricciones impuestas por las especificaciónes dentro de un tiempo de ejecución asequible. Esta tesis investiga alternativas para mejorar el consumo de energía, el rendimiento, el área y el coste, utilizando las tecnologías de fabricación de CI ya establecidas. Los avances en EDA se proponen en tres temas distintos: minimización de área usando métodos booleanos, reducción de retardo y área para diseños basados en matrices de puertas programables (FPGA), y un esquema de reloj alternativo para reducir los márgenes de tiempo excesivamente conservadores. La primera contribución consiste en un método independiente de tecnología para minimizar el área de la lógica combinacional. Se aplica optimización local en grafos de AND-inversor, utilizando una descomposición Booleana de múltiples salidas con divisores de dos literales, con el objetivo de reducir la cantidad de nodos. La segunda contribución propone dos métodos para el mapeo tecnológico de los FPGA. Por un lado, un método de descomposición funcional, que utiliza el tamaño del soporte como función de coste, explorando las características inherentes de los FPGA. Por otro lado, un método de mapeo recursivo, que reduce la distorsión estructural del grafo sujeto, utiliza los resultados del mapeo como función de coste y obtiene reducciones significativas en área y retardo. La tercera contribución evalúa la mitigación de la variabilidad dinámica y la simplificación de la red de suministro de energía (PDN) utilizando un esquema de reloj adaptativo basado en un oscilador en anillo (ROC). Se investiga el impacto de los parámetros de la PDN y la ubicación del ROC, mostrando mejoras potenciales en el rendimiento, consumo estático y coste.
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Bataineh, Abdulla. "Parallel logic and interconnection simulation algorithms for high-speed digital circuits /". The Ohio State University, 1992. http://rave.ohiolink.edu/etdc/view?acc_num=osu148775943632878.
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Taber, Caleb N. "Conversion of Digital Circuits Labs". Digital Commons @ East Tennessee State University, 2016. https://dc.etsu.edu/honors/395.
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The engineering technology department at ETSU currently lacks a modern method to teach digital circuits. The aim of this thesis is to convert our current digital circuits labs to equivalent labs suited to run on the Basys 3. The Basys has several advantages over the aging NI Elvis boards (and now just breadboards) currently in use. The first advantage is that the Basys gives students a taste of FPGA programming without being overwhelmingly; like the systems currently in place for the digital signal processing class. The Basys is also a more modern system; our current integrated circuit and breadboard system is from the 70’s and has little to do with the modern world of electronics.
There are several major difficulties with moving towards the Basys 3. It requires several tweaks to the current computer security setting of the lab computers. The other issue to be solved is that very few people in the department have even an inkling of how to program in VHDL and most of them are outgoing students. This lack of skills could be a threat to the class but I have included an appendix and a few recommendations for books on the subject to ensure that system development can continue.
The other objective of this project was to see if there were ways to incorporate new educational techniques into the engineering technology curriculum. While there have been no actual tests on students, the groundwork has been laid to use some new ideas in the classroom. All of these new systems are designed to get students to think about how devices actually work and develop models to help them fully understand what is being taught.
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Herbert, J. M. J. "Application of formal methods to digital system design". Thesis, University of Cambridge, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.233985.
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Chenard, Jean-Samuel. "Hardware-based temporal logic checkers for the debugging of digital integrated circuits". Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=106282.
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Integrated circuit complexity is ever increasing and the debug process of modern devices pose important technical challenges and cause delays in production. A comprehensive Design-for-Debug methodology is therefore rapidly becoming a necessity. This thesis presents a comprehensive system-level approach to debugging based on insilicon hardware checkers. The proposed approach leverages existing assertion-based verification libraries by translating useful temporal logic statements into efficient hardware circuits. Those checker circuits are then integrated in the device as part of the memory map, so they can provide on-line monitoring and debug assistance in addition to accelerating the integration of performance monitoring counters. The thesis presents a set of enhancements to the translation process from temporal language to hardware, targeted such that an eventual debug process is made more efficient. Automating the integration of the checker's output and control structures is covered along with a practical method that allow transparent access to the resulting registers within a modern (Linux) operating system. Finally, a method of integration of the hardware checkers in future Network-on-Chip systems is proposed. The use of a quality metric encompassing test, monitoring and debug considerations is defined along with the necessary tool flow required to support theprocess.La complexité des circuits intégrés augmente sans cesse et à un tel point que le procéssus de déboggage pose de nombreux problèmes techniques et engendre des retards dans la production. Une approche d'ensemble de conception pour le déboggage (Design-for-Debug) devient donc rapidement une nécessité. Cette thèse propose une approche détaillée de niveau système, intégrant des circuits de surveillance sur puce. L'approche proposée s'appuie sur la réutilisation de déclarations écrites en language de logique temporelle afin de les transformer en circuits digitaux efficaces. Ces derniers seront intégrés à la puce à travers son interface d'image mémoire afin qu'ils puissent servir au processus de déboggage ainsi qu'à une utilisation dans le système lorsque la puce est intégrée dans son environement. Cette thèse présente une série d'ajout au procéssus de transformation d'instructions de logique temporelle de manière à faciliter le procéssus de déboggage. Une méthode qui automatise l'intégration des sorties et du contrôle des circuits de surveillance est présentée ainsi que la manière dont une utilisation de ces circuits peut être accomplie dans le contexte d'un système d'exploitation moderne (Linux). Finalement, une méthode globale d'intégration des circuits de vérification dans le contexte de systèmes basés sur les réseaux-sur-puce est présentée, accompagnée de la chaine d'outils requise pour supporter ce nouveau processus de conception. Cette méthode propose l'utilisation de facteurs de qualité de test, de surveillance et de déboggage (Test, Monitoring and Debug) permettant une meilleure sélection des circuits ainsi qu'une intégration plus efficace au niveau des resources matérielles.
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Nguyen, Loc Bao. "Logic design using programmable logic devices". PDXScholar, 1988. https://pdxscholar.library.pdx.edu/open_access_etds/4103.
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The Programmable Logic Devices, PLO, have caused a major impact in logic design of digital systems in this decade. For instance, a twenty pin PLO device can replace from three hundreds to six hundreds Transistor Transistor Logic gates, which people have designed with since the 60s. Therefore, by using PLD devices, designers can squeeze more features, reduce chip counts, reduce power consumption, and enhance the reliability of the digital systems.
This thesis covers the most important aspects of logic design using PLD devices. They are Logic Minimization and State Assignment. In addition, the thesis also covers a seldomly used but very useful design style, Self-Synchronized Circuits.
The thesis introduces a new method to minimize Two-Level Boolean Functions using Graph Coloring Algorithms and the result is very encouraging. The raw speed of the coloring algorithms is as fast as the Espresso, the industry standard minimizer from Berkeley, and the solution is equally good.
The thesis also introduces a rule-based state assignment method which gives equal or better solutions than STASH (an Intel Automatic CAD tool) by as much as twenty percent.
One of the problems with Self-Synchronized circuits is that it takes many extra components to implement the circuit. The thesis shows how it can be designed using PLD devices and also suggests the idea of a Clock Chip to reduce the chip count to make the design style more attractive.
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Henry, Michael B. "Emerging Power-Gating Techniques for Low Power Digital Circuits". Diss., Virginia Tech, 2011. http://hdl.handle.net/10919/29627.
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As transistor sizes scale down and levels of integration increase, leakage power has become a critical problem in modern low-power microprocessors. This is especially true for ultra-low-voltage (ULV) circuits, where high levels of leakage force designers to chose relatively high threshold voltages, which limits performance. In this thesis, an industry-standard technique known as power-gating is explored, whereby transistors are used to disconnect the power from idle portions of a chip. Present power-gating implementations suffer from limitations including non-zero off-state leakage, which can aggregate to a large amount of wasted energy during long idle periods, and high energy overhead, which limits its use to long-term system-wide sleep modes. As this thesis will show however, by vastly increasing the effectiveness of power-gating through the use of emerging technologies, and by implementing aggressive hardware-oriented power-gating policies, leakage in microprocessors can be eliminated to a large extent. This allows the threshold voltage to be lowered, leading to ULV microprocessors with both low switching energy and high performance.
The first emerging technology investigated is the Nanoelectromechnical-Systems (NEMS) switch, which is a CMOS-compatible mechanical relay with near-infinite off-resistance and low on-resistance. When used for power-gating, this switch completely eliminates off-state leakage, yet is compact enough to be contained on die. This has tremendous benefits for applications with long sleep times. For example, a NEMS-power-gated architecture performing an FFT per hour consumes 30 times less power than a transistor-power-gated architecture. Additionally, the low on-resistance can lower power-gating area overhead by 36-83\%.
The second technology targets the high energy overhead associated with powering a circuit on and off. This thesis demonstrates that a new logic style specifically designed for ULV operation, Sense Amplifier Pass Transistor Logic (SAPTL), requires power-gates that are 8-10 times smaller, and consumes up to 15 times less boot-up energy, compared to static-CMOS. These abilities enable effective power-gating of an SAPTL circuit, even for very short idle periods. Microprocessor simulations demonstrate that a fine-grained power-gating policy, along with this drastically lower overhead, can result in up to a 44\% drop in energy.
Encompassing these investigations is an energy estimation framework built around a cycle-accurate microprocessor simulator, which allows a wide range of circuit and power-gating parameters to be optimized. This framework implements two hardware-based power-gating schedulers that are completely invisible to the OS, and have extremely low hardware overhead, allowing for a large number of power-gated regions. All together, this thesis represents the most complete and forward-looking study on power-gating in the ULV region. The results demonstrate that aggressive power-gating allows designers to leverage the very low switching energy of ULV operation, while achieving performance levels that can greatly expand the capabilities of energy-constrained systems.Ph. D.
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Lammert, Adam Crawford. "Searching for Better Logic Circuits: Using Artificial Intelligence Techniques to Automate Digital Design". NCSU, 2006. http://www.lib.ncsu.edu/theses/available/etd-06072006-140938/.
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LAMMERT, ADAM CRAWFORD. Searching for Better Logic Circuits: Using Artificial Intelligence Techniques to Automate Digital Design. (Under the direction of Dr. Edward Willmore Davis Jr.) Logic circuits are at the core of modern computing. The process of designing circuits which are efficient is thus of critical importance. Usually, logic circuits are designed by human beings who have a specific repertoire of conventional design techniques. These techniques limit the solutions that may be considered during the design process in both form and quality. The limits guide designers through the immense realm of possible circuits, thus making the problem more manageable. Simultaneously, the limits sometimes eliminate from consideration circuits which are optimal in terms of size, depth, etc. By exploring the full range of possible solutions, circuits could be discovered which are superior to the best known human designs. Automated design techniques borrowed from artificial intelligence have allowed exactly that. Specifically, the application of genetic algorithms has allowed the creation of circuits which are substantially superior to the best known human designs. This paper expands on such previous research with a three-fold approach. This approach is comprised of (1) two distinct optimizations for the application of genetic algorithms to design, (2) the formulation and implementation of a systematic search technique to the problem and (3) a comparison of the relative merits of the optimized genetic algorithm and the systematic search technique. It is contended that both genetic algorithms and systematic search can be preferable depending on the situation at hand.
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Elliot, Ralph. "Some issues in the design of digital circuits using Occam and temperal logic". Thesis, University of East Anglia, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.253629.
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Hassoune, Ilham. "Design and optimization of digital circuits for low power and security applications". Université catholique de Louvain, 2006. http://edoc.bib.ucl.ac.be:81/ETD-db/collection/available/BelnUcetd-06292006-113241/.
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Since integration technology is approaching the nanoelectronics range, some practical limits are being reached. Leakage power is increasing more and more with the continuous scaling, and design of clock distribution systems needs to be reconsidered as it becomes difficult to deal with performance and power consumption specifications while keeping a correct synchronisation in modern multi-GHz systems. The ongoing technology trend will become difficult to maintain unless dedicated library cells, new logic styles and circuit methods are emerging to prevent the drawbacks of future nanoscale circuits. In this thesis we investigate a new class of dynamic differential logic family that features a self-timed operation and low output logic swing. The latter contributes to reduce dynamic power, while the self-timing scheme alleviates the drawbacks of synchronous circuits and systems. Furthermore, the dynamic and differential nature of LSCML class brings advantages in terms of reduction of the power consumption variation and thus gives LSCML an additional potential for implementation of secure encryption devices against attacks based on power analysis. We investigate dynamic and leakage power reduction at the cell level through the application of low-power low-voltage techniques to a new hybrid full adder structure. The 8b RCA circuit based on the ULPFA (ultra low power full adder) version of this full adder, achieves a total power and a leakage power, which are both reduced by 50% compared to the 8b RCA implemented with conventional static CMOS full adder, while featuring better power delay product.
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Holst, Stefan [Verfasser], i Hans-Joachim [Akademischer Betreuer] Wunderlich. "Efficient location-based logic diagnosis of digital circuits / Stefan Holst. Betreuer: Hans-Joachim Wunderlich". Stuttgart : Universitätsbibliothek der Universität Stuttgart, 2012. http://d-nb.info/1028799373/34.
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Battina, Brahmasree. "An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design". Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc799495/.
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Integrated Circuits (ICs) have a broad range of applications in healthcare, military, consumer electronics etc. The acronym VLSI stands for Very Large Scale Integration and is a process of making ICs by placing millions of transistors on a single chip. Because of advancements in VLSI design technologies, ICs are getting smaller, faster in speed and more efficient, making personal devices handy, and with more features. In this thesis work an interactive framework is designed in which the fundamental concepts of digital logic design and VLSI design such as logic gates, MOS transistors, combinational and sequential logic circuits, and memory are presented in a simple, interactive and user friendly way to create interest in students towards engineering fields, especially Electrical Engineering and Computer Engineering. Most of the concepts are explained in this framework by taking the examples which we see in our daily lives. Some of the critical design concerns such as power and performance are presented in an interactive way to make sure that students can understand these significant concepts in an easy and user friendly way.
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Davis, Justin S. "An FPGA-based digital logic core for ATE support and embedded test applications". Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15639.
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Roumeliotis, Emmanuel. "Multi-processor logic simulation at the chip level". Diss., Virginia Polytechnic Institute and State University, 1986. http://hdl.handle.net/10919/71180.
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This dissertation presents the design and development of a multi-processor logic simulator. After an introduction to parallel processing, the concept of distributed simulation is described as well as the possibility of deadlock in a distributed system. It is proven that the proposed system does not deadlock. Next, the modeling techniques are discussed along with the timing mechanisms used for logic simulation. A new approach, namely process oriented simulation is studied in depth. It is shown that modeling for this kind of simulation is more efficient regarding modeling ease, computer memory and simulation time, than existing simulation methods. The hardware design of the multi-processor system and the algorithms for synchronization and signal interchange between the processors are presented next. An algorithm for an efficient partitioning of the digital network to be simulated among the processors of the system is also described. Apart from the simulation of a single digital network, the simulator can also be used for fault simulation and design verification. Regarding fault simulation, the fault injection and fault detection techniques are presented. The experimental results obtained by running the multi-processor simulator are compared with the theoretical estimates as well as with results obtained by other multi-processor systems. The comparison shows that the proposed simulator exhibits the estimated performance. Finally, the design of a common bus interface is given. This interface will connect the processors of the system directly without the intervention of a hard disk which was used for the development and testing of the system.Ph. D.
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Silva, Jose Carlos da. "Conversor digital quaternario para analogico". [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260604.
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Orientador: Alberto Martins JorgeTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-04T16:28:44Z (GMT). No. of bitstreams: 1 Silva_JoseCarlosda_D.pdf: 8074106 bytes, checksum: 2f71934ce780079124988d97ff4b0521 (MD5) Previous issue date: 2005
Resumo: Neste trabalho é apresentada a lógica múltiplo valor como opção para substituir ou ser usada como interface com a lógica binária. A lógica múltiplo valor difere da lógica binária clássica devido ao fato que os seus dígitos estão além de zeros e uns. Utilizando a lógica múltiplo valor consegue-se comunicação em entre blocos ou com o mundo externo a um chip com menor número de interconexões, o que acarretará a diminuição da área do circuito integrado e redução de custos. Pesquisadores e industria caminham para a pesquisa e desenvolvimento de circuitos múltiplos valores, que podem substituir ou ser utilizados como interface com os circuitos de dois valores (binários). Este trabalh o apresenta o desenvolvido do projeto de um conversor digital quaternário para analógico que tem quatro entradas e resolução equivalente a um conversor digital binário para analógico de oito entradas. Este conversor foi confeccionado totalmente em tecnologia CMOS 0.35µm, tendo como resultado um protótipo de um circuito integrado múltiplo valor que contém todas as células de um conversor digital binário para analógico. Este conversor apresenta consumo de potência abaixo de 1mW, alimentação simples de 5V e compactação (900µm x 235µm)
Abstract: In this work is presented the multiple value logic as option to substitute or to be used as interface with the binary logic. The multiple value logic differs of the classic binary logic to the fact that its digits are beyond zeros and ones. Using the multiple logic value obtains communication in between blocks or with the external world to one chip with lesser number of interconnections, what it will cause the reduction of the area of the integrated circuit and reduction of costs. Researchers and industry walk for the research and development of multiple values circuits, that can substitute or be used as interface with the circuits of two values (binary). This work presents the developed one of the project of a quaternary digital to analog converter that it has four inputs and resolution equivalent to a binary digital to analog converter of eight inputs. This converter was confectioned totally in technology CMOS 0.35µm, having as resulted an prototype of an integrated circuit multiple value that contains all the cells of a binary digital to analog converter. This converter presents consumption of power below of 1mW, simple voltage of 5V and compacting (900µm x 235µm)
Doutorado
Eletrônica, Microeletrônica e Optoeletrônica
Doutor em Engenharia Elétrica
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Chakrapani, Lakshmi Narasimhan. "Probabilistic boolean logic, arithmetic and architectures". Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26706.
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Thesis (Ph.D)--Computing, Georgia Institute of Technology, 2009.Committee Chair: Palem, Krishna V.; Committee Member: Lim, Sung Kyu; Committee Member: Loh, Gabriel H.; Committee Member: Mudge, Trevor; Committee Member: Yalamanchili, Sudhakar. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Mozaffari, Mojaveri Seyed Nima. "DESIGN AND TEST OF DIGITAL CIRCUITS AND SYSTEMS USING CMOS AND EMERGING RESISTIVE DEVICES". OpenSIUC, 2018. https://opensiuc.lib.siu.edu/dissertations/1526.
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The memristor is an emerging nano-device. Low power operation, high density, scalability, non-volatility, and compatibility with CMOS Technology have made it a promising technology for memory, Boolean implementation, computing, and logic systems. This dissertation focuses on testing and design of such applications. In particular, we investigate on testing of memristor-based memories, design of memristive implementation of Boolean functions, and reliability and design of neuromorphic computing such as neural network. In addition, we show how to modify threshold logic gates to implement more functions. Although memristor is a promising emerging technology but is prone to defects due to uncertainties in nanoscale fabrication. Fast March tests are proposed in Chapter 2 that benefit from fast write operations. The test application time is reduced significantly while simultaneously reducing the average test energy per cell. Experimental evaluation in 45 nm technology show a speed-up of approximately 70% with a decrease in energy by approximately 40%. DfT schemes are proposed to implement the new test methods. In Chapter 3, an Integer Linear Programming based framework to identify current-mode threshold logic functions is presented. It is shown that threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. Experimental results show that many more functions can be implemented with predetermined hardware overhead, and the hardware requirement of a large percentage of existing threshold functions is reduced when comparing to the traditional CMOS-based threshold logic implementation. In Chapter 4, a new method to implement threshold logic functions using memristors is presented. This method benefits from the high range of memristor’s resistivity which is used to define different weight values, and reduces significantly the transistor count. The proposed approach implements many more functions as threshold logic gates when comparing to existing implementations. Experimental results in 45 nm technology show that the proposed memristive approach implements threshold logic gates with less area and power consumption. Finally, Chapter 5 focuses on current-based designs for neural networks. CMOS aging impacts the total synaptic current and this impacts the accuracy. Chapter 5 introduces an enhanced memristive crossbar array (MCA) based analog neural network architecture to improve reliability due to the aging effect. A built-in current-based calibration circuit is introduced to restore the total synaptic current. The calibration circuit is a current sensor that receives the ideal reference current for non-aged column and restores the reduced sensed current at each column to the ideal value. Experimental results show that the proposed approach restores the currents with less than 1% precision, and the area overhead is negligible.
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Breitkreutz-von, Gamm Stephan Verfasser], Doris [Akademischer Betreuer] [Schmitt-Landsiedel i György [Akademischer Betreuer] Csaba. "Perpendicular Nanomagnetic Logic: Digital Logic Circuits from Field-coupled Magnets / Stephan Breitkreutz-von Gamm. Gutachter: György Csaba ; Doris Schmitt-Landsiedel. Betreuer: Doris Schmitt-Landsiedel". München : Universitätsbibliothek der TU München, 2015. http://d-nb.info/1075596009/34.
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Ting, Darwin Ta-Yueh. "Reconfigurable Threshold Logic Gates Implemented in Nanoscale Double-Gate MOSFETs". Ohio University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1219672300.
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Teixeira, Marco Antonio. "Técnicas de reconfigurabilidade dos FPGAs da família APEX 20K - Altera". Universidade de São Paulo, 2002. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-11092002-164901/.
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Os dispositivos lógicos programáveis pertencentes à família APEX 20K, são configurados no momento da inicialização do sistema com dados armazenados em dispositivos especificamente desenvolvidos para esse fim. Esta família de FPGAs possui uma interface otimizada, permitindo também que microprocessadores os configure de maneira serial ou paralela, síncrona ou assíncronamente. Depois de configurados, estes FPGAs podem ser reconfigurados em tempo real com novos dados de configuração. A reconfiguração em tempo real conduz a inovadoras aplicações de computação reconfigurável. Os dispositivos de configuração disponíveis comercialmente, limitam-se a configurar os FPGAs apenas no momento da inicialização do sistema e sempre com o mesmo arquivo de configuração. Este trabalho apresenta a implementação de um controlador de configuração capaz de gerenciar a configuração e reconfiguração de múltiplos FPGAs, a partir de vários arquivos distintos de configuração. Todo o projeto é desenvolvido, testado e validado através da ferramenta EDA Quartus II, que propicia um ambiente de desenvolvimento integrado de projeto, compilação e síntese lógica, simulação e análise de tempo.The APEX 20K programmable logic devices family, are configured at system power-up with data stored in a specific serial configuration device. This family of FPGAs contain an optimized interface that permits microprocessors to configure APEX 20K devices serially or in parallel, and synchronously or asynchronously. After configured, it can be reconfigured in-circuit by resetting the device and loading new data. Real-time changes lead to innovative reconfigurable computing applications. The commercial available configuration devices limit to configure the APEX 20K devices only on the system power-up and always with the same configuration data file. This work shows a configuration controller implementation that can manage the configuration and reconfiguration of several FPGAs from multiple configuration files. The entire project is developed, tested and validated through the EDA tool Quartus II, that provide a integrated package with HDL and schematic design entry, compilation and logic synthesis, full simulation and worst-case timing analysis.
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Heim, Marcus Edwin Allan. "ANALYSIS OF MOS CURRENT MODE LOGIC (MCML) AND IMPLEMENTATION OF MCML STANDARD CELL LIBRARY FOR LOW-NOISE DIGITAL CIRCUIT DESIGN". DigitalCommons@CalPoly, 2015. https://digitalcommons.calpoly.edu/theses/1422.
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MOS current mode logic (MCML) offers low noise digital circuits that reduce noise that can cripple analog components in mixed-signal integrated circuits, when compared to CMOS digital circuits. An MCML standard cell library was developed for the Cadence Virtuoso Integrated Circuit (IC) design software that gives IC designers the ability to design complex, low noise digital circuits for use in mixed-signal and noise sensitive systems at a high level of abstraction, allowing them to get superior products to market faster than competitors. The MCML standard cell library developed and presented here allows for fast development of mixed signal circuits by providing quiet digital building block gates that reduce the simultaneous switching noise (SSN) by an order of magnitude over conventional CMOS based designs [3]. This thesis project developed the following digital gates in MCML as a standard cell library for general-purpose low noise and very low noise applications: inverter, buffer, NAND, AND, NOR, OR, XOR, NXOR, 2:1 MUX, CMOS to MCML, MCML to CMOS, and double edge triggered flip-flop (DETFF).
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Tang, Guang-ming. "Studies on Datapath Circuits for Superconductor Bit-Slice Microprocessors". 京都大学 (Kyoto University), 2016. http://hdl.handle.net/2433/217208.
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Machado, Lucas. "KL-cut based remapping". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2013. http://hdl.handle.net/10183/116138.
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Este trabalho introduz o conceito de cortes k e cortes kl sobre um circuito mapeado, em uma representação netlist. Esta nova abordagem é derivada do conceito de cortes k e cortes kl sobre AIGs (and inverter graphs), respeitando as diferenças entre essas duas formas de representar um circuito. As principais diferenças são: (1) o número de entradas em um nodo do grafo, e (2) a presença de inversores e buffers de forma explícita no circuito mapeado. Um algoritmo para enumerar cortes k e cortes kl é proposto e implementado. A principal motivação de usar cortes kl sobre circuitos mapeados é para realizar otimizações locais na síntese lógica de circuitos digitais. A principal contribuição deste trabalho é uma abordagem nova de remapeamento iterativo, utilizando cortes kl, reduzindo a área do circuito e respeitando as restrições de temporização do circuito. O uso de portas lógicas complexas pode potencialmente reduzir a área total de um circuito, mas elas precisam ser escolhidas corretamente de forma a manter as restrições de temporização do circuito. Ferramentas comerciais de síntese lógica trabalham melhor com portas lógicas simples e não são capazes de explorar eventuais vantagens em utilizar portas lógicas complexas. A abordagem proposta de remapeamento iterativo utilizando cortes kl é capaz de explorar uma quantidade maior de portas lógicas com funções lógicas diferentes, reduzindo a área do circuito, e mantendo as restrições de temporização intactas ao fazer uma checagem STA (análise temporal estática). Resultados experimentais mostram uma redução de até 38% de área na parte combinacional de circuitos para um subconjunto de benchmarks IWLS 2005, quando comparados aos resultados de ferramentas comerciais de síntese lógica. Outra contribuição deste trabalho é um novo modelo de rendimento (yield) para fabricação de circuitos integrados (IC) digitais, considerando problemas de resolução da etapa de litografia como uma fonte de diminuição do yield. O uso de leiautes regulares pode melhorar bastante a resolução da etapa de litografia, mas existe um aumento de área significativo ao se introduzir a regularidade. Esta é a primeira abordagem que considera o compromisso (trade off) de portas lógicas com diferentes níveis de regularidade e diferentes áreas durante a síntese lógica, de forma a melhorar o yield do projeto. A ferramenta desenvolvida de remapeamento tecnológico utilizando cortes kl foi modificada de forma a utilizar esse modelo de yield como função custo, de forma a aumentar o número de boas amostras (dies) por lâmina de silício (wafer), com resultados promissores.This work introduces the concept of k-cuts and kl-cuts on top of a mapped circuit in a netlist representation. Such new approach is derived from the concept of k-cuts and klcuts on top of AIGs (and inverter graphs), respecting the differences between these two circuit representations. The main differences are: (1) the number of allowed inputs for a logic node, and (2) the presence of explicit inverters and buffers in the netlist. Algorithms for enumerating k-cuts and kl-cuts on top of a mapped circuit are proposed and implemented. The main motivation to use kl-cuts on top mapped circuits is to perform local optimization in digital circuit logic synthesis. The main contribution of this work is a novel iterative remapping approach using klcuts, reducing area while keeping the timing constraints attained. The use of complex gates can potentially reduce the circuit area, but they have to be chosen wisely to preserve timing constraints. Logic synthesis commercial design tools work better with simple cells and are not capable of taking full advantage of complex cells. The proposed iterative remapping approach can exploit a larger amount of logic gates, reducing circuit area, and respecting global timing constraints by performing an STA (static timing analysis) check. Experimental results show that this approach is able to reduce up to 38% in area of the combinational portion of circuits for a subset of IWLS 2005 benchmarks, when compared to results obtained from logic synthesis commercial tools. Another contribution of this work is a novel yield model for digital integrated circuits (IC) manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the lithography, but it results in a significant area overhead by introducing regularity. This is the first approach that considers the tradeoff of cells with different level of regularity and different area overhead during the logic synthesis, in order to improve overall design yield. The technology remapping tool based on kl-cuts developed was modified in order to use such yield model as cost function, improving the number of good dies per wafer, with promising interesting results.
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Bhavnagarwala, Azeez Jenúddin. "Voltage scaling constraints for static CMOS logic and memory cirucits". Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15401.
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Sutton, Akil Khamisi. "Hardness assurance testing and radiation hardening by design techniques for silicon-germanium heterojunction bipolar transistors and digital logic circuits". Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29778.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Cressler, John; Committee Member: Deo, Chaitanya; Committee Member: Doolittle, Alan; Committee Member: Keezer, David; Committee Member: May, Gary; Committee Member: Papapolymerou, John. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Tran, Duc Anh. "Architecture hybride tolérante aux fautes pour l'amélioration de la robustesse des circuits et systèmes intégrés numériques". Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20132/document.
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L'évolution de la technologie CMOS consiste à la miniaturisation continue de la taille des transistors. Cela permet la réalisation de circuits et systèmes intégrés de plus en plus complexes et plus performants, tout en réduisant leur consommation énergétique, ainsi que leurs coûts de fabrication. Cependant, chaque nouveau noeud technologique CMOS doit faire face aux problèmes de fiabilité, dues aux densités de fautes et d'erreurs croissantes. Par conséquence, les techniques de tolérance aux fautes, qui utilisent des ressources redondantes pour garantir un fonctionnement correct malgré la présence des fautes, sont devenus indispensables dans la conception numérique. Ce thèse étudie une nouvelle architecture hybride tolérante aux fautes pour améliorer la robustesse des circuits et systèmes numériques. Elle s'adresse à tous les types d'erreur dans la partie combinatoire des circuits, c'est-à-dire des erreurs permanentes (« hard errors »), des erreurs transitoires (« SETs ») et des comportements temporels fautifs (« timing errors »). L'architecture proposée combine la redondance de l'information (pour la détection d'erreur), la redondance de temps (pour la correction des erreurs transitoires) et la redondance matérielle (pour la correction des erreurs permanentes). Elle permet de réduire considérablement la consommation d'énergie, tout en ayant une surface de silicium similaire comparée aux solutions existantes. En outre, elle peut également être utilisée dans d'autres applications, telles que pour traiter des problèmes de vieillissement, pour tolérer des fautes dans les architectures pipelines, et pour être combiné avec des systèmes avancés de protection des erreurs transitoires dans la partie séquentielle des circuits logiques (« SEUs »)Evolution of CMOS technology consists in continuous downscaling of transistor features sizes, which allows the production of smaller and cheaper integrated circuits with higher performance and lower power consumption. However, each new CMOS technology node is facing reliability problems due to increasing rate of faults and errors. Consequently, fault-tolerance techniques, which employ redundant resources to guarantee correct operations of digital circuits and systems despite the presence of faults, have become essential in digital design. This thesis studies a novel hybrid fault-tolerant architecture for robustness improvement of digital circuits and systems. It targets all kinds of error in combinational part of logic circuits, i.e. hard, SETs and timing errors. Combining information redundancy for error detection, timing redundancy for transient error correction and hardware redundancy for permanent error corrections, the proposed architecture allows significant power consumption saving, while having similar silicon area compared to existing solutions. Furthermore, it can also be used in other applications, such as dealing with aging phenomenon, tolerating faults in pipeline architecture, and being combined with advanced SEUs protection scheme for sequential parts of logic circuits
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Ho, Philip. "Investigation of Solution Space of Trees and DAGs for Realization of Combinational Logic in AT 6000 series FPGAs". PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4586.
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Various tree and Directed Acyclic Graph structures have been used for representation and manipulation of switching functions. Among these structures the Binary Decision DiagramJilave been the most widely used in logic synthesis. A BDD is a binary tree graph that represents the recursive execution of Shannon's expansion. A FDD is a directed function graph that represents the recursive execution of Reed Muller expansion. A family of decision diagrams for representation of Boolean function is introduced in this thesis. This family of Kronecker Functional Decision Diagrams (KFDD) includes the Binary Decision Diagrams (BDD) and Functional Decision Diagrams (FDD) as subsets. Due to this property, KFDDs can provide a more compact representation of the functions than either of the two above-mentioned decision diagrams. The new notion of permuted KFDD is introduced to generate a compact circuit in FPGAs to represent a switching function. A permuted tree search is a free search method which is not limited by the order of variable and the expansion tree as in the cases of KFDD, BDD and FDD. A family of decision diagrams and the theory developed for them are presented in this thesis. The family of permuted Kronecker Functional Decision Diagrams includes BODs and FDDs as subsets is incorporated into program RESPER. Due to this property, permuted KFDD can provide a more compact circuit realization in the multilevel circuit. The circuit obtained can be realized directly with FPGAs like AT 6000 series from Atmel. This algorithm is implemented on several MCNC benchmarks, the results compared with previous programs, TECHMAP and REMIT, are very encouraging. The main achievement of this thesis is the creation of the algorithm which applies a permuted tree search method combined with Davio Expansion and generates Directed Acyclic Graph which is next mapped to a compact circuit realization.
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Lee, Chris Y. "Full Custom VLSI Design of On-Line Stability Checkers". DigitalCommons@CalPoly, 2011. https://digitalcommons.calpoly.edu/theses/607.
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A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly.
A method for concurrent fault testing called On-line Stability Checking was introduced by Franco and McCluskey [10] to detect reliability failures. Reliability failures initially manifest themselves as delay faults and transient glitching, which become progressively larger over time due to the wearout of conducting metal lines, eventually leading to functional faults. Stability checkers periodically detect reliability failures by monitoring CUT output signals for unstable and late input signals over a time period after the sampling clock edge.
The checkers are tested by applying variable delayed input test patterns to emulate reliability failures. Consequently, configurable delay chains were incorporated into the system to provide variable delays on the input signal lines. The system also includes external test signal ports.
Circuit and layout designs were implemented in the Electric VLSI Design tool [12] and simulated with LTSPICE [13]. Electric provides Design Rule Checking (DRC) and Layout-versus-Schematic (LVS) utilities for verification. Each module was designed in a bottom-up, hierarchical cell-based approach. Functional simulation, DRC and LVS checks were performed at every subsequent higher cell layer in the design hierarchy. The final chip layout was taped out for fabrication on November 29, 2010 and finished parts were received on July 7, 2011 after two manufacturing delays.
Finished packaged parts were successfully verified for functionality based on SPICE simulations. The stability checkers were tested for flip-flop operation, glitch detection and late signal arrival detection. Configurable delay chains were tested to determine delay resolution and uniformity. Actual delay resolution and range measurements show a 3 to 4 times difference compared to simulated values.
The Electric design template created from this project includes basic CMOS logic gates with uniform standard cell heights. The template contains a 40-pin pad ring cell along with the individual pad ring components. EE 431 students would be able to create custom chips that are compatible for fabrication via the MOSIS MEP service. In future work, the template design library can be expanded to include more logic gate variants of various inputs and drive strengths as well as more complex functional modules.
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Inampudi, Sivateja. "Teaching Fundamentals of Digital Logic Design and VLSI Design Using Computational Textiles". Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc699874/.
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This thesis presents teaching fundamentals of digital logic design and VLSI design for freshmen and even for high school students using e-textiles. This easily grabs attention of students as it is creative and interesting. Using e-textiles to project these concepts would be easily understood by students at young age. This involves stitching electronic circuits on a fabric using basic components like LEDs, push buttons and so on. The functioning of these circuits is programmed in Lilypad Arduino. By using this method, students get exposed to basic electronic concepts at early stage which eventually develops interest towards engineering field.
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Dal, Bem Vinícius. "CMOS digital integrated circuit design faced to NBTI and other nanometric effects". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/37180.
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Esta dissertação explora os desafios agravados pela miniaturização da tecnologia na fabricação e projeto de circuitos integrados digitais. Os efeitos físicos do regime nanométrico reduzem o rendimento da produção e encurtam a vida útil dos dispositivos, restringindo a utilidade dos padrões de projeto convencionais e ameaçando a evolução da tecnologia CMOS como um todo. Nesta dissertação é exposta uma consistente revisão bibliográfica dos principais efeitos físicos parasitas presentes no regime nanométrico. Como o NBTI tem recebido destaque na literatura relacionada à confiabilidade de circuitos, este efeito de envelhecimento recebe destaque também neste texto, sendo explorado mais detalhadamente. Diversas técnicas de avaliação de redução do NBTI são demonstradas, sendo apresentados, em cada um destes tópicos, trabalhos desenvolvidos no âmbito desta dissertação e seus resultados. O circuito proposto como técnica de avaliação de NBTI permite uso de simulações elétricas para análise de degradação de circuitos. A análise da influência do rearranjo da estrutura de transistores para reduzir a degradação quanto ao NBTI apresenta bons resultados e não impede o uso de outras técnicas combinadas.This thesis explores the challenges worsened by the technology miniaturization in fabrication and design of digital integrated circuits. The physical effects of nanometric regime reduce the production yield and shorten the devices lifetime, restricting the usefulness of standard design flows and threatening the evolution of CMOS technologies. This thesis exposes a consistent bibliographic review about the main aggressive physical effects of nanometric regime. NBTI has received special attention in reliability literature, so this text follows the same strategy, deeply exploring this aging effect. A broad set of NBTI evaluation and mitigation techniques are explained, including developed works in each one of these categories. The proposed circuit as NBTI evaluation technique allows the use of electrical simulation for circuit degradation analysis. The analysis of the transistors arrangement restructuring as a technique for NBTI degradation reduction shows satisfactory results, while does not restrict the use of other combined techniques.
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Воргуль, О. В., І. В. Свид, О. В. Зубков i В. В. Семенець. "Teaching microcontrollers and FPGAs in Quarantine from Coronavirus: Challenges and Prospects". Thesis, MC&FPGA, 2020. https://mcfpga.nure.ua/conf/2020-mcfpga/10-35598-mcfpga-2020-005.
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Modern equipment is becoming more and more complex and education establishment must keep up with it and offer its contribution to the overall progress. The goal of this work is to find the way how to survive on self-isolation and teach microcontrollers and FPGAs. What challenges need to be overcome and what prospects may open up.
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Zaghloul, Yasser A. "Polarization based digital optical representation, gates, and processor". Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/43675.
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A complete all-optical-processing polarization-based binary-logic system, by which any logic gate or processor could be implemented, was proposed. Following the new polarization-based representation, a new Orthoparallel processing technique
that allows for the creation of all-optical-processing gates that produce a unique output once in a truth table, was developed. This representation allows for the implementation of all basic 16 logic gates, including the NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented, which opens the door for reconfigurable optical processors and programmable optical logic gates. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information.
The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. The Rail Road (RR) architecture for polarization optical processors (POP) is presented. All the control inputs are applied simultaneously, leading to a single time lag, which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step design algorithm is provided for the POP, and design reduction methodologies are discussed. The algorithm lends itself systematically to software programming and computer-assisted design.
A completely passive optical switch was also proposed. The switch is used to design completely passive optical gates, including the NAND gate, with their operational speeds only bound by the input beams prorogation delay. The design is used to demonstrate various circuits including the RS latch.
Experimental data is reported for the NAND and the Universal gate operating with different functionality. A minute error is recorded in different cases, which can be easily eliminated by a more dedicated manufacturing process. Finally, some field applications are discussed and a comparison between all proposed systems and the current semiconductor devices is conducted based on multiple factors, including, speed, lag, and heat generation.
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Figueiró, Thiago Rosa. "Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/27663.
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O emprego de ferramentas de automação de projetos de circuitos integrados permitiu que projetos complexos atingissem time-to-market e custos de produção factíveis. Neste contexto, o processo de síntese lógica é uma etapa fundamental no fluxo de projeto. O passo independente de tecnologia (parte do processo de síntese lógica, que é realizada sem considerar características físicas) é tradicionalmente realizado sobre equações. O desenvolvimento de novos algoritmos de otimização multi-nível recentemente migrou para o emprego de And-Inverter Graphs (AIGs). O número de nodos e a altura de um grafo apresentam melhor correlação com os resultados em área e atraso de um circuito, se comparados com as características de outras formas de representação. Neste trabalho, um algoritmo de síntese lógica independente de tecnologia, que funciona sobre uma estrutura de AIGs, é proposto. Uma nova abordagem para a construção de AIGs, baseada no novo paradigma de síntese chamado de composição funcional, é apresentado. Esta abordagem consiste em construir o AIG final através da associação de AIGs mais simples, em uma abordagem bottom-up. Durante a construção do grafo, o método controla as características dos grafos intermediários e finais, a partir da aplicação de uma função de custo, como forma de avaliação da qualidade desses AIGs. O objetivo é a minimização do número de nodos e da altura do AIG final. Este algoritmo de síntese lógica multi-objetivo apresenta características interessantes e vantagens quando comparado com abordagens tradicionais. Além disso, este trabalho apresenta a síntese de funções com múltiplas saídas em AIGs, o que melhora a característica de compartilhamento de estruturas, melhorando o circuito resultante. Resultados mostraram a melhora em torno de 5% em número de nodos, quando comparados com os resultados obtidos com a ferramenta ABC.The use of design automation tools has allowed complex projects to reach feasible time-to-market and cost parameters. In this context, logic synthesis is a critical procedure in the design flow. The technology independent step (part of the logic synthesis which is performed regardless any physical property) is traditionally performed over equations. The development of new multi-level optimization algorithms has recently shifted towards the use of And-Inverter-Graphs (AIGs). The number of nodes and the graphs depth in AIGs present better correlation with resulting circuit area and delay than any characteristic of other representations. In this work, a technology independent synthesis algorithm that works on top of an AIG data structure is proposed. A novel approach for AIG construction, based on a new synthesis paradigm called functional composition, is introduced. This approach consists in building the final AIG by associating simpler AIGs, in a bottom-up approach. The method controls, during the graphs construction, the characteristics of final and intermediate graphs by applying a cost function as a way to evaluate the quality of those AIGs. The goal is to minimize the number of nodes and the depth of the final AIG. This multi-objective synthesis algorithm has presented interesting features and advantages when compared to traditional approaches. Moreover, this work presents a method for AIGs construction for multiple output functions, which enhances structural sharing, improving the resulting circuit. Results have shown an improvement of around 5% in number of nodes when compared to ABC tool.
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Guardia, Filho Luiz Eduardo. "Sistema para controle de maquinas robotizadas utilizando dispositivos logicos programaveis". [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259017.
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Orientador: Marconi Kolm MadridDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-04T17:12:57Z (GMT). No. of bitstreams: 1 GuardiaFilho_LuizEduardo_M.pdf: 2405031 bytes, checksum: b724836217b8586950a9ffabcd235f35 (MD5) Previous issue date: 2005
Resumo: Este trabalho de mestrado teve o propósito de projetar e construir um sistema de hard-ware capaz de realizar o controle de máquinas robotizadas em tempo real. Foi dada uma abordagem usando técnicas de processamento paralelo e eletrônica reconfigurável com o uso de dispositivos lógicos programáveis. Mostrou-se em função dos resultados das implementações que o sistema proposto é eficiente para ser utilizado no controle de robôs baseado em modelos matemáticos complexos como cinemático direto/inverso, dinâmico e de visão artificial. Esse mesmo sistema prevê sua utilização para os quatro níveis hierárquicos envolvidos em plantas que se utilizam de controle automático: supervisão, tarefas, trajetória e servomecanismos. O sistema possui interfaces de comunicação USE e RS-232, conversores A/D e D/A, sistema de processamento de imagens (entradas e saídas de sinais de vídeo analógico), portas E/S, chaves e leds para propósito geral. A eficiência foi comprovada através de experimentações práticas utilizando sistemas robóticos reais como: sistema de um pêndulo acionado, robô redundante de 4GDL denominado Cobra, e solução em hardware de funções importantes no sentido da resolução dos modelos matemáticos em tempo real como funções transcendentais
Abstract: This work had as purpose the project and build of a hardware system with abilities to accomplish the real time control of robotic machines. It was given an approach using tech-niques of parallel processing and programmable electronics configuration with programmable logic devices. According to the implementation results, it was shown that this proposed sys-tem is efficient to be used for controlling robots based on complex mathematical models, like direct/inverse kinematics, dynamics and artificial vision. This system foresees its use for the four hierarchical levels involved in industrial plants that use automatic control: supervision, tasks, trajectory /path and servomechanisms. The system has USE and RS-232 communica-tion interfaces, A/D and D/A converters, image processing capabilities (with input/output for analog video signals), I/O ports, and switches and leds for general purpose. Its efficiency is demonstrated through practical experimentations using real robotic systems as: a driven pendu-lum system, a redundant 4 DOF robot called "Cobra", and a hardware solution for important functions in the sense of real time mathematical models computing, like the transcendental functions
Mestrado
Automação
Mestre em Engenharia Elétrica
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Marusiak, David. "MOS CURRENT MODE LOGIC (MCML) ANALYSIS FOR QUIET DIGITAL CIRCUITRY AND CREATION OF A STANDARD CELL LIBRARY FOR REDUCING THE DEVELOPMENT TIME OF MIXED-SIGNAL CHIPS". DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1363.
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Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with the transitions. Creating a noiseless standard cell library with MCML allows use of circuitry that uses low voltage switching with 1.5V between logic levels in a quiet or mixed-signal environment as opposed to the full rail to rail swinging of CMOS logic. This allows cohesive implementation with analog circuitry on the same chip due to constant current and lower switching ranges not creating rail noise during digital switching. Standard cells allow for the Cadence tools to automatically generate circuits and Cadence serves as the development platform for the MCML standard cells.
The theory surrounding MCML is examined along with current and future applications well-suited for MCML are researched and explored with the goal of highlighting valid candidate circuits for MCML. Inverters and NAND gates with varying current drives are developed to meet these specialized goals and are simulated to prove viability for quiet, mixed-signal applications. Analysis and results show that MCML is a superior implementation choice compared toCMOSfor high speed and mixed signal applications due to frequency independent power dissipation and lack of generated noise during operation. Noise results show rail current deviations of 50nA to 300nA during switching over an average operating current of 20µA to 80µA respectively. The multiple order of magnitude difference between noise and signal allow the MCML cells to dissipate constant power and thus perform with no noise added to a system. Additional simulated results of a 31-stage ring oscillator result in a frequency for MCML of 1.57GHz simulated versus the 150.35MHz that MOSIS tested on a fabricated 31-stage CMOS oscillator. The layouts designed for the standard cell library conform to existing On Semiconductor ami06 technology dimensions and allow for design of any logical function to be fabricated. The I/O signals of each cell operate at the same input and output voltage swings which allow seamless integration with each other for implementation in any logical configuration.
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Bortolon, Felipe Todeschini. "Static noise margin analysis for CMOS logic cells in near-threshold". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/178664.
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Os avanços na tecnologia de semicondutores possibilitou que se fabricasse dispositivos com atividade de chaveamento mais rápida e com maior capacidade de integração de transistores. Estes avanços, todavia, impuseram novos empecilhos relacionados com a dissipação de potência e energia. Além disso, a crescente demanda por dispositivos portáteis levaram à uma mudança no paradigma de projeto de circuitos para que se priorize energia ao invés de desempenho. Este cenário motivou à reduzir a tensão de alimentação com qual os dispositivos operam para um regime próximo ou abaixo da tensão de limiar, com o objetivo de aumentar sua duração de bateria. Apesar desta abordagem balancear características de performance e energia, ela traz novos desafios com relação a tolerância à ruído. Ao reduzirmos a tensão de alimentação, também reduz-se a margem de ruído disponível e, assim, os circuitos tornam-se mais suscetíveis à falhas funcionais. Somado à este efeito, circuitos com tensões de alimentação nestes regimes são mais sensíveis à variações do processo de fabricação, logo agravando problemas com ruído. Existem também outros aspectos, tais como a miniaturização das interconexões e a relação de fan-out de uma célula digital, que incentivam a avaliação de ruído nas fases iniciais do projeto de circuitos integrados Por estes motivos, este trabalho investiga como aprimorar a margem de ruído estática de circuitos síncronos digitais que irão operar em tensões no regime de tensão próximo ou abaixo do limiar. Esta investigação produz um conjunto de três contribuições originais. A primeira é uma ferramenta capaz de avaliar automaticamente a margem de ruído estática de células CMOS combinacionais. A segunda contribuição é uma metodologia realista para estimar a margem de ruído estática considerando variações de processo, tensão e temperatura. Os resultados obtidos mostram que a metodologia proposta permitiu reduzir até 70% do pessimismo das margens de ruído estática, Por último, a terceira contribuição é um fluxo de projeto de células combinacionais digitais considerando ruído, e uma abordagem para avaliar a margem de ruído estática de circuitos complexos durante a etapa de síntese lógica. A biblioteca de células resultante deste fluxo obteve maior margem de ruído (até 24%) e menor variação entre diferentes células (até 62%).The advancement of semiconductor technology enabled the fabrication of devices with faster switching activity and chips with higher integration density. However, these advances are facing new impediments related to energy and power dissipation. Besides, the increasing demand for portable devices leads the circuit design paradigm to prioritize energy efficiency instead of performance. Altogether, this scenario motivates engineers towards reducing the supply voltage to the near and subthreshold regime to increase the lifespan of battery-powered devices. Even though operating in these regime offer interesting energy-frequency trade-offs, it brings challenges concerning noise tolerance. As the supply voltage reduces, the available noise margins decrease, and circuits become more prone to functional failures. In addition, near and subthreshold circuits are more susceptible to manufacturing variability, hence further aggravating noise issues. Other issues, such as wire minimization and gate fan-out, also contribute to the relevance of evaluating the noise margin of circuits early in the design Accordingly, this work investigates how to improve the static noise margin of digital synchronous circuits that will operate at the near/subthreshold regime. This investigation produces a set of three original contributions. The first is an automated tool to estimate the static noise margin of CMOS combinational cells. The second contribution is a realistic static noise margin estimation methodology that considers process-voltage-temperature variations. Results show that the proposed methodology allows to reduce up to 70% of the static noise margin pessimism. Finally, the third contribution is the noise-aware cell design methodology and the inclusion of a noise evaluation of complex circuits during the logic synthesis. The resulting library achieved higher static noise margin (up to 24%) and less spread among different cells (up to 62%).
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Wan, Wei. "A New Approach to the Decomposition of Incompletely Specified Functions Based on Graph Coloring and Local Transformation and Its Application to FPGA Mapping". PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/4698.
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The thesis presents a new approach to the decomposition of incompletely specified functions and its application to FPGA (Field Programmable Gate Array) mapping. Five methods: Variable Partitioning, Graph Coloring, Bond Set Encoding, CLB Reusing and Local Transformation are developed in order to efficiently perform decomposition and FPGA (Lookup-Table based FPGA) mapping. 1) Variable Partitioning is a high quality hemistic method used to find the "best" partitions, avoiding the very time consuming testing of all possible decomposition charts, which is impractical when there are many input variables in the input function. 2) Graph Coloring is another high quality heuristic\ used to perform the quasi-optimum don't care assignment, making the program possible to accept incompletely specified function and perform a quasi-optimum assignment to the unspecified part of the function. 3) Bond Set Encoding algorithm is used to simplify the decomposed blocks during the process of decomposition. 4) CLB Reusing algorithm is used to reduce the number of CLBs used in the final mapped circuit. 5) Local Transformation concept is introduced to transform nondecomposable functions into decomposable ones, thus making it possible to apply decomposition method to FPGA mapping. All the above developed methods are incorporated into a program named TRADE, which performs global optimization over the input functions. While most of the existing methods recursively perform local optimization over some kinds of network-like graphs, and few of them can handle incompletely specified functions. Cube calculus is used in the TRADE program, the operations are global and very fast. A short description of the TRADE program and the evaluation of the results are provided at the_ end of the thesis. For many benchmarks the TRADE program gives better results than any program published in the literature.
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Zhuo, Yue. "Timing and Congestion Driven Algorithms for FPGA Placement". Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5423/.
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Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the location of each logic block. I present novel timing and congestion driven placement algorithms for FPGAs with minimal runtime overhead. By predicting the post-routing timing-critical edges and estimating congestion accurately, this algorithm is able to simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of the algorithm consists of a criticality-history record of connection edges and a congestion map. This approach is applied to the 20 largest Microelectronics Center of North Carolina (MCNC) benchmark circuits. Experimental results show that compared with the state-of-the-art FPGA place and route package, the Versatile Place and Route (VPR) suite, this algorithm yields an average of 8.1% reduction (maximum 30.5%) in the critical path delay and 5% reduction in channel width. Meanwhile, the average runtime of the algorithm is only 2.3X as of VPR.
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Webb, Robert L. "ASYNCHRONOUS MIPS PROCESSORS: EDUCATIONAL SIMULATIONS". DigitalCommons@CalPoly, 2010. https://digitalcommons.calpoly.edu/theses/381.
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The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous processor design, and propose a series of asynchronous designs to be used by students in tandem with traditional synchronous designs when taking an undergraduate computer architecture course.
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Benhaddou, Mohamed. "Définition d'une méthodologie de conception de circuits intégrés numériques indépendante de la technologie : application à la conception d'un processeur flou". Vandoeuvre-les-Nancy, INPL, 1995. http://www.theses.fr/1995INPL067N.
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Les technologies de fabrication de circuits intégrés numériques et les outils de CAO pour la conception de ceux-ci ont régulièrement évolué. La tendance actuelle est de décrire le comportement du concept à un niveau d'abstraction élevé à l'aide d'un langage de description du matériel standard comme Verilog ou VHDL, et laisser le soin aux outils de synthèse de générer les masques du circuit ou sa liste d'équipotentielles dans la bibliothèque d'un fondeur. Le problème est le prix élevé de ces outils de synthèse de haut niveau qui est dissuasif pour les PME/PMI. L’objectif de ce travail est de montrer que l'on peut démarrer le flot de conception d'un circuit par sa description comportementale de haut niveau et d'obtenir des circuits répondant au cahier des charges en utilisant deux outils de CAO abordables financièrement et répandus dans le commerce: Max+plus II pour le développement des circuits configurables et Solo 1400 pour le développement des circuits précaractérisés. Les outils de synthèse de haut niveau sont ainsi évités à l'aide d'un environnement de conception bâti autour de logiciels de portabilité entre les deux technologies et d'interfaçage entre les HDL de Max+plus II (AHDL) et Solo 1400 (model) et Verilog qui permet la modélisation des circuits intégrés numériques à différents niveaux d'abstraction. Cet environnement de conception est géré par une méthodologie simple, stricte et efficace. Un processeur flou a été conçu afin de valider la méthodologie de conception indépendante de la technologie proposée