Gotowe bibliografie tematyczne / Digital logic circuits

Gotowa bibliografia na temat „Digital logic circuits”

Autor: Grafiati
Data publikacji: 4 czerwca 2021
Data aktualizacji: 20 lutego 2023

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Artykuły w czasopismach na temat "Digital logic circuits"

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Hasuo, S., i T. Imamura. "Digital logic circuits". Proceedings of the IEEE 77, nr 8 (1989): 1177–93. http://dx.doi.org/10.1109/5.34118.

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Duncan, Philip N., Siavash Ahrar i Elliot E. Hui. "Scaling of pneumatic digital logic circuits". Lab on a Chip 15, nr 5 (2015): 1360–65. http://dx.doi.org/10.1039/c4lc01048e.

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We present strategies for scaling pneumatic logic circuits to smaller dimensions. Our process achieves order-of-magnitude increases in both circuit density and speed, enabling the construction of a 12-bit counter.
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Kamde, Shilpa, Jitesh Shinde, Sanjay Badjate i Pratik Hajare. "Comparative Analysis Domino Logic Based Techniques For VLSI Circuit". INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, nr 8 (21.03.2014): 3803–8. http://dx.doi.org/10.24297/ijct.v12i8.2998.

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Domino logic is a CMOS-based evolution of the dynamic logic techniques  based on either PMOS or NMOS transistors. Domino logic technique is widely used in modern digital VLSI circuit. Dynamic logic is twice as fast as static CMOS logic because it uses only N fast transistors. The Dynamic (Domino) logic circuit are often favored in high performance designs because of the high speed and low area advantage.Four different dynamic circuit techniques including Basic domino logic circuit are compared in this paper for low power consumption and speed of domino logic circuits. For digital circuit simulation used BSIM(Berkeley Short Channel IGFET ) Model because it control leakage current.
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Hou, Yue Wei, Xin Xu, Wei Wang, Xiao Bo Tian i Hai Jun Liu. "Titanium Oxide Memristor Based Digital Encoder Circuit". Applied Mechanics and Materials 644-650 (wrzesień 2014): 3430–33. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3430.

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Memristors have the ability to remember their last resistance and quickly switch between different states, such characteristics could make logic circuits simple in structure and fast in boolean computations. A kind of digital encoder circuit utilizing titanium oxide memristors is proposed. A logic NAND gate which acts as key part in the circuit is designed. The works in this letter also provide a practical approach for designing logic gate circuit with memristors.
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Raman, Karthik, i Andreas Wagner. "The evolvability of programmable hardware". Journal of The Royal Society Interface 8, nr 55 (9.06.2010): 269–81. http://dx.doi.org/10.1098/rsif.2010.0212.

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In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected ‘neutral networks’ in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 10 45 logic circuits (‘genotypes’) and 10 19 logic functions (‘phenotypes’). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry.
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Dokic, B. L. "A Review on Energy Efficient CMOS Digital Logic". Engineering, Technology & Applied Science Research 3, nr 6 (18.12.2013): 552–61. http://dx.doi.org/10.48084/etasr.389.

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Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in the behavior of digital circuits in sub-threshold and strong inversion. Therefore, synthesis of digital circuits is the same for both strong and weak operating modes. Analysis of the influence of the technology, MOS transistor threshold voltage (Vt) and power supply voltage (Vdd) on digital circuit power consumption and speed for both operating modes is given. It is shown that optimal power consumption (minimum power consumption for given speed) depends on optimal choice of threshold, and power supply voltage. Multi Vdd /Vt techniques are analyzed as well. A review and analysis of alternative logical circuit's topologies – pass logic (PL), complementary pass logic (CPL), push-pull pass logic (PPL) and adiabatic logic – is also given. As shown, adiabatic logic is the optimum choice regarding energy efficiency.
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Avdeev, N. A., i P. N. Bibilo. "Design of Digital Operational Units with Low Power Consumption". Programmnaya Ingeneria 12, nr 2 (16.03.2021): 63–73. http://dx.doi.org/10.17587/prin.12.63-73.

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The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take the aspect of power con­sumption into account and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following: the clock gating and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description of operational units with low power consumption implemented in the CMOS basis.
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Jóźwiak, Lech. "General Decomposition and Its Use in Digital Circuit Synthesis". VLSI Design 3, nr 3-4 (1.01.1995): 225–48. http://dx.doi.org/10.1155/1995/16259.

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Modem microelectronic technology.gives opportunities to build digital circuits of huge complexity and provides a wide diversity of logic building blocks. Although logic designers have been building circuits for many years, they have realized that advances in microelectronic technology are outstripping their abilities to make use of the created opportunities. In this paper, we present the fundamentals of a logic design methodology which meets the requirements of today's complex circuits and modem building blocks. The methodology is based on the theory of general full-decompositions which constitutes the theory of digital circuit structures at the highest abstraction level. The paper explains the theory and shows how it can be used for digital circuit synthesis. The decomposition methodology that is presented ensures “correctness by construction” and enables very effective and efficient post-factum validation. It makes possible extensive examination of the structural features of the required information processing in relation to a given set of objectives and constraints.
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Shukla, Vandana, O. P. Singh, G. R. Mishra i R. K. Tiwari. "Design and Implementation of Four Bit Binary Shifter Circuit Using Reversible Logic Approach". International Journal of Reconfigurable and Embedded Systems (IJRES) 4, nr 3 (1.11.2015): 213. http://dx.doi.org/10.11591/ijres.v4.i3.pp213-218.

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Shifter circuits are the key component of arithmetic logic unit as well as storage unit of any digital computing device. Designing these shifter circuits using reversible logic approach leads to create low power loss digital systems. Reversible circuit design approach is nowadays widely applicable in various disciplines such as Nanotechnology, Low power CMOS design, Optical computing etc. This paper presents two design approaches for four bit binary combinational shifter circuit with the help of different types of reversible logic gates. The proposed optimized design is simulated using Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency.
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Žemva, Andrej, Andrej Trost i Baldomir Zajc. "Educational Programmable System for Prototyping Digital Circuits". International Journal of Electrical Engineering & Education 35, nr 3 (lipiec 1998): 236–44. http://dx.doi.org/10.1177/002072099803500306.

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In this paper, we present an educational programmable system for prototyping digital circuits. The system is composed of the PC and the prototyping board composed of 3 FPGAs. PC is used for designing a digital circuit, programming the FPGAs, automatic generation of the interface logic and hardware verification of the designed circuit.
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Rozprawy doktorskie na temat "Digital logic circuits"

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Silva, Augusto Neutzling. "Syhthesis of thereshold logic based circuits". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/119435.

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Circuitos baseados em portas lógicas de limiar (threshold logic gates – TLG) vem sendo estudados como uma alternativa promissora em relação ao tradicional estilo lógico CMOS, baseado no operadores AND e OR, na construção de circuitos integrados digitais. TLGs são capazes de implementar funções Booleanas mais complexas em uma única porta lógica. Diversos novos dispositivos, candidatos a substituir o transistor MOS, não se comportam como chaves lógicas e são intrinsicamente mais adequados à implementação de TLGs. Exemplos desses dispositivos são os memristores, spintronica, diodos de tunelamento ressonante (RTD), autômatos celulares quânticos (QCA) e dispositivos de tunelamento de elétron único (SET). Para o desenvolvimento de um fluxo de projeto de circuitos integrados baseados em lógica threshold, duas etapas são fundamentais: (1) identificar se uma dada função Booleana corresponde a uma função lógica threshold (TLF), isto é, pode ser implementada em um único TLG e computar os pesos desse TLG; (2) se uma função não é identificada como TLF, outro método de síntese lógica deve construir uma rede de TLGs otimizada que implemente a função. Este trabalho propõe métodos para atacar cada um desses dois problemas, e os resultados superam os métodos do estado-da-arte. O método proposto para realizar a identificação de TLFs é o primeiro método heurístico capaz de identificar todas as funções de cinco e seis variáveis, além de identificar mais funções que os demais métodos existentes quando o número de variáveis aumenta. O método de síntese de redes de TLGs é capaz de sintetizar circuitos reduzindo o número de portas TLG utilizadas, bem como a profundidade lógica e o número de interconexões. Essa redução é demonstrada através da síntese dos circuitos de avaliação da MCNC em comparação com os métodos já propostos na literatura. Tais resultados devem impactar diretamente na área e desempenho do circuito.
In this work, a novel method to synthesize digital integrated circuits (ICs) based on threshold logic gates (TLG) is proposed. Synthesis considering TLGs is quite relevant, since threshold logic has been revisited as a promising alternative to conventional CMOS IC design due to its suitability to emerging technologies, such as resonant tunneling diodes, memristors and spintronics devices. Identification and synthesis of threshold logic functions (TLF) are fundamental steps for the development of an IC design flow based on threshold logic. The first contribution is a heuristic algorithm to identify if a function can be implemented as a single TLG. Furthermore, if a function is not detected as a TLF, the method uses the functional composition approach to generate an optimized TLG network that implements the target function. The identification method is able to assign optimal variable weights and optimal threshold value to implement the function. It is the first heuristic algorithm that is not based on integer linear programming (ILP) that is able to identify all threshold functions with up to six variables. Moreover, it also identifies more functions than other related heuristic methods when the number of variables is more than six. Differently from ILP based approaches, the proposed algorithm is scalable. The average execution time is less than 1 ms per function. The second major contribution is the constructive process applied to generate optimized TLG networks taking into account multiple goals and design costs, like gate count, logic depth and number of interconnections. Experiments carried out over MCNC benchmark circuits show an average gate count reduction of 32%, reaching up to 54% of reduction in some cases, when compared to related approaches.
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Gaubatz, Donald Almo. "Logic programming analysis of asynchronous digital circuits". Thesis, University of Cambridge, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.386062.

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Liu, Tai-hung. "Logic synthesis for high-performance digital circuits /". Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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Xia, Yinshui. "Low power design techniques for digital logic circuits". Thesis, Edinburgh Napier University, 2003. http://researchrepository.napier.ac.uk/Output/6887.

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With the rapid increase in the density and the size of chips and systems, area and power dissipation become critical concern in Very Large Scale Integrated (VLSI) circuit design. Low power design techniques are essential for today's VLSI industry. The history of symbolic logic and some typical techniques for finite state machine (FSM) logic synthesis are reviewed. The state assignment is used to optimize area and power dissipation for FSMs. Two cost functions, targeting area and power, are presented. The Genetic Algorithm (GA) is used to search for a good state assignment to minimize the cost functions. The algorithm has been implemented in C. The program can produce better results than NOVA, which is integrated into SIS by DC Berkeley, and other publications both in area and power tested by MCNC benchmarks. Flip-flops are the core components of FSMs. The reduction of power dissipation from flip-flops can save power for digital systems significantly. Three new kinds of flip-flops, called differential CMOS single edge-triggered flip-flop with clock gating, double edge-triggered and multiple valued flip-flops employing multiple valued clocks, are proposed. All circuits are simulated using PSpice. Most researchers have focused on developing low-power techniques in AND/OR or NAND & NOR based circuits. The low power techniques for AND /XOR based circuits are still in their early stage of development. To implement a complex function involving many inputs, a form of decomposition into smaller subfunctions is required such that the subfunctions fit into the primitive elements to be used in the implementation. Best polarity based XOR gate decomposition technique has been developed, which targets low power using Huffman algorithm. Compared to the published results, the proposed method shows considerable improvement in power dissipation. Further, Boolean functions can be expressed by Fixed Polarity Reed-Muller (FPRM) forms. Based on polarity transformation, an algorithm is developed and implemented in C language which can find the best polarity for power and area optimization. Benchmark examples of up to 21 inputs run on a personal computer are given.
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Duncan, Austin H. "Logic Gates Using the Digilent Basys3". Digital Commons @ East Tennessee State University, 2015. https://dc.etsu.edu/honors/311.

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ENTC 3370 teaches students the basics of digital circuits. Until recently the students were taught using an analog device called a Protoboard. With the acquisition of the Digilent Basys3, a digital device, the class will begin to be taught using digital modeling techniques. This is a collection of lab activities designed to be used with the Basys3 within the class. The activities were designed in a way so that students with little programming knowledge could complete the tasks.
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Hacker, Charles Hilton, i n/a. "WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design". Griffith University. School of Engineering, 2001. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20050915.172404.

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This thesis presents an interactive computerised teaching suite developed for the design of combinatorial and sequential logic circuits. This suite fills a perceived gap in the currently available computer-based teaching software for digital logic design. Several existing digital logic educational software are available, however these existing programs were found to be unsuitable for our use in providing alternative mode subject delivery. This prompted the development of a Microsoft Windows TM tutorial suite, called WinLogiLab. WinLogiLab comprises of a set of tutorials that uses student provided input data, to perform the initial design steps for digital Combinatorial and Sequential logic circuits. The combinatorial tutorials are designed to show the link between Boolean Algebra and Digital Logic circuits, and follows the initial design steps: from Boolean algebra, truth tables, to Exact and the Heuristic minimisation techniques, to finally produce the combinatorial circuit. Similarly, the sequential tutorials can design simple State Machine Counters, and can model more complex Finite State Automata.
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Hacker, Charles. "WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design". Thesis, Griffith University, 2001. http://hdl.handle.net/10072/367209.

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This thesis presents an interactive computerised teaching suite developed for the design of combinatorial and sequential logic circuits. This suite fills a perceived gap in the currently available computer-based teaching software for digital logic design. Several existing digital logic educational software are available, however these existing programs were found to be unsuitable for our use in providing alternative mode subject delivery. This prompted the development of a Microsoft Windows TM tutorial suite, called WinLogiLab. WinLogiLab comprises of a set of tutorials that uses student provided input data, to perform the initial design steps for digital Combinatorial and Sequential logic circuits. The combinatorial tutorials are designed to show the link between Boolean Algebra and Digital Logic circuits, and follows the initial design steps: from Boolean algebra, truth tables, to Exact and the Heuristic minimisation techniques, to finally produce the combinatorial circuit. Similarly, the sequential tutorials can design simple State Machine Counters, and can model more complex Finite State Automata.
Thesis (Masters)
Master of Philosophy (MPhil)
School of Engineering
Science, Environment, Engineering and Technology
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Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits". Ottawa, 1999.

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Keeble, Clifford George. "The synthesis of self-timed circuits by formal methods". Thesis, University of Southampton, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239920.

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Sah, Puja. "Implementing Digital Logic Design Concepts Using Paper Electronics". Thesis, University of North Texas, 2018. https://digital.library.unt.edu/ark:/67531/metadc1157633/.

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This thesis presents the implementation of some of the basic concepts of digital logic design in a fun and creative way with the help of paper electronics. This involves circuit building on paper using conductive tape or conductive ink and circuit components as electronics craft materials. Paper electronics toolkit called circuit sticker microcontroller which is deployed by a company named Chibitronics and AT89C51 microcontroller were used for the computational functioning of the circuits built on paper. This can be used to teach the fundamentals of digital logic design to the students in their early stage of studies in an attractive way and can help them them gain a better understanding. This thesis can also be helpful in grabbing the attention of high school students and motivate them towards choosing the engineering discipline for their higher studies.
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Książki na temat "Digital logic circuits"

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J, Adam L., red. Digital circuits. London: E. Arnold, 1990.

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Digital circuits: Logic and design. New York: M. Dekker, 1985.

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1930-, Pierce Bill, red. Digital logic: Circuits and systems. Albany, N.Y: Delmar Publishers, 1988.

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Langholz, Gideon. Digital logic design. Dubuque, Iowa: Wm. C. Brown, 1988.

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Abraham, Kandel, i Mott Joe L, red. Digital logic design. Dubuque, Iowa: Wm. C. Brown, 1988.

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Bogart, Theodore F. Introduction to digital circuits. Lake Forest: McGraw, 1992.

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Introduction to digital circuits. Lake Forest, Ill: Glencoe, 1992.

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J, Martin Alain, red. Asynchronous pulse logic. Boston: Kluwer Academic Publishers, 2002.

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Mims, Forrest M. Engineer's mini-notebook: Digital logic circuits. Ft. Worth, Tex: Radio Shack], 1986.

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T, Radhakrishnan, red. Digital logic and computer organization. New Delhi: Prentice Hall of India (P) Ltd., 2006.

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Części książek na temat "Digital logic circuits"

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Nixon, Mark S. "Logic Circuits". W Introductory Digital Design, 49–84. London: Macmillan Education UK, 1995. http://dx.doi.org/10.1007/978-1-349-13508-0_3.

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Chalk, B. S. "Digital Logic Circuits". W Computer Organisation and Architecture, 8–22. London: Macmillan Education UK, 1996. http://dx.doi.org/10.1007/978-1-349-13871-5_2.

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Tooley, Mike. "Logic Circuits". W Aircraft Digital Electronic and Computer Systems, 70–94. Wyd. 3. London: Routledge, 2022. http://dx.doi.org/10.1201/9781003215516-5.

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Stonham, T. J. "Practical Digital Circuits". W Digital Logic Techniques, 145–60. Boston, MA: Springer US, 1987. http://dx.doi.org/10.1007/978-1-4615-6856-8_7.

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Stonham, T. J. "Design of Sequential Logic Circuits". W Digital Logic Techniques, 82–114. Boston, MA: Springer US, 1987. http://dx.doi.org/10.1007/978-1-4615-6856-8_5.

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Hajji, Bekkay, Adel Mellit i Loubna Bouselham. "Sequential Logic Circuits". W A Practical Guide for Simulation and FPGA Implementation of Digital Design, 119–73. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-0615-2_4.

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Hajji, Bekkay, Adel Mellit i Loubna Bouselham. "Combinational Logic Circuits". W A Practical Guide for Simulation and FPGA Implementation of Digital Design, 45–118. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-0615-2_3.

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Chakradhar, Srimat T., Vishwani D. Agrawal i Michael L. Bushneil. "Logic Circuits and Testing". W Neural Models and Algorithms for Digital Testing, 9–19. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3958-2_2.

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Barrett, Steven F. "Fuzzy Logic". W Synthesis Lectures on Digital Circuits & Systems, 123–47. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-21877-4_5.

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LaMeres, Brock J. "Digital Circuitry and Interfacing". W Introduction to Logic Circuits & Logic Design with Verilog, 37–80. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-53883-9_3.

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Streszczenia konferencji na temat "Digital logic circuits"

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Chen, J. E., Chung Len Lee, Wen Zen Shen i Beyin Chen. "Fanout fault analysis for digital logic circuits". W Proceedings of the Fourth Asian Test Symposium. IEEE, 1995. http://dx.doi.org/10.1109/ats.1995.485313.

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Soeleman, Hendrawan, i Kaushik Roy. "Ultra-low power digital subthreshold logic circuits". W the 1999 international symposium. New York, New York, USA: ACM Press, 1999. http://dx.doi.org/10.1145/313817.313874.

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Sziray, Jozsef. "Test calculation for logic and short-circuit faults in digital circuits". W 2012 IEEE 16th International Conference on Intelligent Engineering Systems (INES). IEEE, 2012. http://dx.doi.org/10.1109/ines.2012.6249815.

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Yang, Xiangning, Eric Weglarz i Kewal Saluja. "On NBTI Degradation Process in Digital Logic Circuits". W 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07). IEEE, 2007. http://dx.doi.org/10.1109/vlsid.2007.117.

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Shreya, Sonal, i Rajeevan Chandel. "Performance analysis of CNTFET based digital logic circuits". W 2014 Students Conference on Engineering and Systems (SCES). IEEE, 2014. http://dx.doi.org/10.1109/sces.2014.6880063.

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Smith, S. Desmond. "Demonstration of a simple optical finite state machine and restoring all-optical digital logic". W OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1986. http://dx.doi.org/10.1364/oam.1986.we3.

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We reported the first digital all-optical circuits using steady-state continuous-mode optically bistable devices which can be optically biased and held close to switchpoint and which give an incremental change of output sufficient to switch succeeding elements.1,2 These circuits have been demonstrated using cascadable elements constructed, respectively, from InSb (using electronic nonlinearities) and ZnSe refractive interferometric devices. This approach derives from the original (1979) observations of steady-state optical bistability3 and gain in an optical transphasor.4 Cascadability, fan-out, and fan-in are essential elements of an all-optical digital parallel computer in which, in the first instance, the opportunity provided for massive parallelism through the simplicity of optical interconnects is seen as one of the prime routes to be investigated toward realizing very high logic rates. With the requirement for restoring logic that there be gain in addition to regions of valid logic-0 and valid logic-1, we show that for digital optics this can be readily achieved by the technique of hold-and-switch. The use of off-axis address for the holding (or optical bias) and signal beams allows digital circuits to be constructed with the required features of restoring logic which can be infinitely extensible given sufficient supply of separately holding beams which can be construed as the power supplies of ensuing circuit elements.5
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Joo-Young Kim i Hoi-Jun Yoo. "Bitwise Competition Logic for compact digital comparator". W 2007 IEEE Asian Solid-State Circuits Conference. IEEE, 2007. http://dx.doi.org/10.1109/asscc.2007.4425682.

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Avedillo, M. J., i J. M. Quintana. "A threshold logic synthesis tool for RTD circuits". W Euromicro Symposium on Digital System Design, 2004. DSD 2004. IEEE, 2004. http://dx.doi.org/10.1109/dsd.2004.1333337.

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Ghasemi, Mehdi, Mohammad Hossein Moaiyeri i Keivan Navi. "Analytical performance evaluation of molecular logic circuits". W 2012 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS). IEEE, 2012. http://dx.doi.org/10.1109/cads.2012.6316428.

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Chan-Geun Yoon, Tae-Won Ahn i Ho-Bum Song. "A fast response digital logic tone detector". W 48th Midwest Symposium on Circuits and Systems, 2005. IEEE, 2005. http://dx.doi.org/10.1109/mwscas.2005.1594083.

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Raporty organizacyjne na temat "Digital logic circuits"

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Reddy, Sudhakar M. On Timing Faults in Digital Logic Circuits. Fort Belvoir, VA: Defense Technical Information Center, sierpień 1993. http://dx.doi.org/10.21236/ada268714.

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