Rozprawy doktorskie na temat „CONTINOUS TIME CIRCUITS”

Thesis (Ph. D.)--Massachusetts Institute of Technology, School of Architecture and Planning, Program in Media Arts and Sciences, 2003.
Vita.
Includes bibliographical references (p. 205-209).
This thesis proposes an alternate paradigm for designing computers using continuous-time analog circuits. Digital computation sacrifices continuous degrees of freedom. A principled approach to recovering them is to view analog circuits as propagating probabilities in a message passing algorithm. Within this framework, analog continuous-time circuits can perform robust, programmable, high-speed, low-power, cost-effective, statistical signal processing. This methodology will have broad application to systems which can benefit from low-power, high-speed signal processing and offers the possibility of adaptable/programmable high-speed circuitry at frequencies where digital circuitry would be cost and power prohibitive. Many problems must be solved before the new design methodology can be shown to be useful in practice: Continuous-time signal processing is not well understood. Analog computational circuits known as "soft-gates" have been previously proposed, but a complementary set of analog memory circuits is still lacking. Analog circuits are usually tunable, rarely reconfigurable, but never programmable. The thesis develops an understanding of the convergence and synchronization of statistical signal processing algorithms in continuous time, and explores the use of linear and nonlinear circuits for analog memory. An exemplary embodiment called the Noise Lock Loop (NLL) using these design primitives is demonstrated to perform direct-sequence spread-spectrum acquisition and tracking functionality and promises order-of-magnitude wins over digital implementations. A building block for the construction of programmable analog gate arrays, the "soft-multiplexer" is also proposed.
by Benjamin Vigoda.
Ph.D.

The growing interest in programmable analog circuits has led to the development of Field Programmable Analog Arrays (FPAAs). An FPAA consists of: 1) a programmable cell that can be reconfigured to perform several analog functions. 2) an architecture that interconnects a number of copies of the programmable cell. In this thesis, the full monolithic circuit implementation of the analog part of the programmable cell is presented. Chapter I gives an introduction to the idea of FPAA and introduces the FPAA architecture and the cell block diagram. Chapter II deals with the design and verification of a differential current-mode four-quadrant multiplier. The weighting-summing circuit with the normalizing stage is discussed in Chapter III. Chapter IV presents the design of a current-mode low-voltage programmable integratorgain circuit. Programmability was achieved by changing the bias current in the designed circuits; no analog switches were used in the signal path. This shows no effect on the performance of the circuits. The presented programming method, however, relies on the availability of a programmable current source with a storage capability. The design of this current source is discussed in chapter V. Conclusions are summarized in Chapter VI. The presented designs throughout the whole thesis were supported by detailed analytical derivations with the necessary SPICE simulations to verify the performance.

Many modern communication systems use orthogonal frequency division multiplexing (OFDM) and discrete multi-tone (DMT) as modulation schemes where high data rates are transmitted over a wide frequency band in multiple orthogonal subcarriers. Due to the many advantages, such as flexibility, good noise immunity and the ability to be optimized for medium conditions, the use of DMT and OFDM can be found in digital video broadcasting, local area wireless network (IEEE 802.11a), asymmetric digital subscriber line (ADSL), very high bit rate DSL (VDSL) and power line communications (PLC). However, a major challenge is the design of the analog frontend; for these systems a large dynamic range is required due to the significant peak to average ratio of the resulting signals. In receivers, very demanding high-performance analog filters are typically used to block interferers and provide anti-aliasing before the subsequent analog to digital conversion stage. For frequencies higher than 10MHz, Gm-C filter implementations are generally preferred due to the more efficient operation of wide-band operational transconductance amplifiers (OTA). Nevertheless, the inherent low-linearity of open-loop operated OTA limits the dynamic range. In this dissertation, three different proposed OTA linearity enhancement techniques for the design of high frequency and high dynamic range are presented. The techniques are applied to two filter implementations: a 20MHz second order tunable filter and a 30MHz fifth order elliptical low-pass filter. Simulation and experimental results show a spurious free dynamic range (SFDR) of 65dB with a power consumption of 85mW. In a figure of merit where SFDR is normalized to the power consumption, this filter is 6dB above the trend-line of recently reported continuous time filters.

Cette thèse aborde l’encodage de degrés de liberté continus temps-fréquence de photon uniques. Les similitudes mathématiques avec les quadratures du champ électromagnétique amène à généraliser des protocoles exprimées dans ces variables dans notre encodage. On introduit un nouveau type de qubit robuste contre des erreurs du type déplacement dans l’espace des phases temps-fréquence. Un nouvel espace des phases doublement cylindriques est étudié et est une représentation particulièrement adaptée pour des états ayant une symétrie de translation. On étudie également comment construire une distribution de phase fonctionnelle permettant de décrire un état quantique possédant des degrés de libertés continus spectraux et en quadrature
This thesis tackles the time-frequency continuous variables degree of freedom encoding of single photons and examine the formal mathematical analogy with the quadrature continuous variables of the electromagnetic field. We define a new type of qubit which is robust against time-frequency displacement errors. We define a new double-cylinder phase space which is particularly adapted for states which have a translational symmetry. We also study how to build a functional phase space distribution which allows to describe a quantum state with spectral and quadrature continuous variables degrees of freedom

Integrated high-Q continuous-time filters require adaptive tuning circuits that will correct the filter parameters such as center frequency and quality factor (Q). Three different automatic tuning techniques are introduced. In all of the proposed methods, frequencyand quality factor tuning loops are controlled digitally, providing stable tuning by activating only one loop at a given time. In addition, a direct relationship between passband gain and quality factor is not required, so the techniques can be applied to active LC filters as well as Gm-C filters. The digital-tuning method based on phase comparison was verified with 1% tuning accuracy at 5.5 MHz for Q of 20. It uses phase information for both Q and center-frequency tuning. The filter output phase is tuned to the known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase comparisons. The second method, high-order digital tuning based on phase comparison, is an extension of the previous technique to high-order analog filters without depending on the master-slave approach. Direct tuning of the overall filter response is achieved without separating individual biquad sections, eliminating switches and their parasitics. The tuning system was verified with a prototype 6th order bandpass filter at 19 MHz with 0.6 MHz bandwidth, which was fabricated in a conventional 0.5 [mu]m CMOS technology. Analysis of different practical limitations is also provided. Finally, the digital-tuning method based on magnitude comparison is proposed for second-order filters for higher frequency operations. It incorporates a frequency synthesizer to generate reference signals, an envelope detector and a switched comparator to compare output magnitudes at three reference frequencies. The theoretical analysis of the technique and the simulation results are provided.

Ce travail de thèse porte sur le développement d’une méthodologie efficace pour la conception analogique, des algorithmes et des outils correspondants qui peuvent être utilisés dans la conception dynamique de fonctions linéaires à temps continu. L’objectif principal est d’assurer que les performances pour un système complet peuvent être rapidement investiguées, mais avec une précision comparable aux évaluations au niveau transistor.Une première direction de recherche a impliqué le développement de la méthodologie de conception basée sur le processus d'optimisation automatique de cellules au niveau transistor et la synthèse de macro-modèles analogiques de haut niveau dans certains environnements comme Mathworks - Simulink, VHDL-AMS ou Verilog-A. Le processus d'extraction des macro-modèles se base sur un ensemble complet d'analyses (DC, AC, transitoire, paramétrique, Balance Harmonique) qui sont effectuées sur les schémas analogiques conçues à partir d’une technologie spécifique. Ensuite, l'extraction et le calcul d'une multitude de facteurs de mérite assure que les modèles comprennent les caractéristiques de bas niveau et peuvent être directement régénéré au cours de l'optimisation.L'algorithme d'optimisation utilise une méthode bayésienne, où l'espace d’évaluation est créé à partir d'un modèle de substitution (krigeage dans ce cas), et la sélection est effectuée en utilisant le critère d’amélioration (Expected Improvement - EI) sujet à des contraintes. Un outil de conception a été développé (SIMECT), qui a été intégré comme une boîte à outils Matlab, employant les algorithmes d’extraction des macro-modèles et d'optimisation automatique
The aim of this thesis is to establish an efficient analog design methodology, the algorithms and the corresponding design tools which can be employed in the dynamic conception of linear continuous-time (CT) functions. The purpose is to assure that the performance figures for a complete system can be rapidly investigated, but with comparable accuracy to the transistor-level evaluations. A first research direction implied the development of the novel design methodology based on the automatic optimization process of transistor-level cells using a modified Bayesian Kriging approach and the synthesis of robust high-level analog behavioral models in environments like Mathworks – Simulink, VHDL-AMS or Verilog-A.The macro-model extraction process involves a complete set of analyses (DC, AC, transient, parametric, Harmonic Balance) which are performed on the analog schematics implemented on a specific technology process. Then, the extraction and calculus of a multitude of figures of merit assures that the models include the low-level characteristics and can be directly regenerated during the optimization process.The optimization algorithm uses a Bayesian method, where the evaluation space is created by the means of a Kriging surrogate model, and the selection is effectuated by using the expected improvement (EI) criterion subject to constraints.A conception tool was developed (SIMECT), which was integrated as a Matlab toolbox, including all the macro-models extraction and automatic optimization techniques

High-performance, high-frequency operational transconductance amplifiers (OTAs) are very important elements in the design of high-frequency continuous-time integrated analog signal processing circuits, because resistors, inductors, integrators, mutators, buffers, multipliers, and filters can be built by OTAs and capacitors. The critical considerations for OTA design are linearity, tuning, frequency response, output impedance, power supply rejection (PSR) and common-mode rejection (CMR). For linearity considerations, two different methods are proposed. One uses cross-coupled pairs (CMOS or NMOS), producing OTAs with very high linearity but either the input range is relatively small or the CMR to asymmetrical inputs is poor. Another employs multiple differential pairs (current addition or subtraction), producing OTAs with high linearity over a very large input range. So, there are tradeoffs among the critical considerations. For different applications, different OTAs should be selected. For consideration of frequency response, the first reported GaAs OTA was designed for achieving very-high-frequency performance, instead of using AC compensation techniques. GaAs is one of the fastest available technologies, but it was new and less mature than silicon when we started the design in 1989. So, there were several issues, such as low output impedance, no P-channel devices, and Schottky clamp. To overcome these problems, new techniques are proposed, and the designed OTA has comparable performance to a CMOS OTA. For PSR and CMR considerations, a fully balanced circuit structure is employed with a common-mode feedback (CMF) circuit used to stabilize the DC output voltages. To reduce the interaction of the operation of CMF and tuning of OTAs, three improved versions of the CMF circuits used in operational amplifiers are proposed. With the designed OTAs, a I GHz GaAs inductor with small parasitics is designed using the proposed procedure to reduce high-frequency effects. Two CMOS high-order, high-frequency filters are designed: one in cascade structure and one in LC ladder form. Also, a 200 MHz third-order elliptic GaAs filter is designed with special consideration of very-high-frequency parasitics. All circuits were fabricated and measured. The experimental results were used to verify the designs.

The expanding wireless market has resulted in complex integrated transceivers that involve RF, analog and mixed-signal circuits, resulting in expensive and complicated testing. The most important challenges that test engineering faces today are (1) providing a fast and accurate fault-diagnosis and performance characterization so as to accelerate the time-to-market and (2) providing an inexpensive test strategy that can be integrated with the design so as to aid the high-volume manufacturing process. The first part of the research focuses on the design of an RMS detector for built-in-self-test (BIST) of an RF integrated transceiver that can directly provide information at various test points in the design. A cascode low noise amplifier (LNA) has been chosen as the device under test (DUT). A compact (< 0.031 mm2) RF RMS detector with negligible input capacitance (< 13 fF) has been implemented in 0.35 µm CMOS technology along with the DUT. Experimental results are currently being assimilated and compared with the simulation results. Frequency limitations were encountered during the testing process due to unexpected increase in the value of the N-well resistors. All other problems faced during the testing, as well as the results obtained so far, are presented in this thesis. In the second part of the research, the use of the RMS detector for BIST has been extended to a continuous-time high-frequency boost-filter. The proposed HF RMS detector has been implemented along with a 24 dB 350 MHz boost filter as the DUT on 0.35 µm CMOS technology. The HF RMS detector occupies 0.07 mm2 and has an input capacitance of 7 fF. The HF RMS detector has a dynamic range greater than 24 dB starting from -38 dBm of input power. The bandwidth and boost of the filter have been accurately estimated in simulation using the HF RMS detector. The sensitivity of an intermediate band pass node of the filter has also been monitored to predict the filter's sensitivity to Q errors. The final part of the research describes the design of a single-ended to differential converter for use in a broadband transceiver operating from 50-850 MHz. This circuit is used as the second stage in the transceiver after the LNA. The design has been simulated on a 0.35 um CMOS process and has a power consumption of 13.5 mW and less than 8 dB of noise figure over the entire band. It is capable of driving a 500fF load with less than 1dB of gain ripple over the entire band (50-850 MHz).

Automatic synthesis of digital VLSI layout has been available for many years. It has become a necessary part of the design industry as the window of time from conception to production shrinks with ever increasing competition. However, automatic synthesis of analog VLSI layout remains rare. With digital circuits, there is often room for signal drift. In a digital circuit, a signal can drift within a range before hitting the threshold which triggers a change in logic state. The effect of parasitic capacitances for the most part, hinders the timing margins of the signal, but not its functionality. The logic functionality is protected by the inherent noise immunity of digital circuits. With analog circuits, however, there is little room for drift. Parasitic influence directly affects signal integrity and the functionality of the circuit. The underlying problem automatic VLSI layout programs face is how to minimize this influence. This thesis describes a software tool that was written to show that the minimization of parasitic influence is possible in the case of automatic layout of continuous-time filters using transconductance-capacitor methods.

Cette thèse s'intéresse à la simulation temps-réel de circuit audio nonlinéaires. Dans cette thèse, nous utilisons le formalisme des systèmes Hamiltoniens à ports (SHP) pour garantir le bilan de puissance et la passivité. De plus, nous adoptons un cadre fonctionnel à temps continu pour représenter des signaux "analogiques virtuels" et nous proposons d'approximer les solutions par projection sur des trames temporelles. En tant que résultat principal, nous établissons une condition suffisante sur les projecteurs de sorte à obtenir des trajectoires à bilan de puissance garanti. Notre but est double: premièrement, pour gérer l'expansion de bande-passante causée par les nonlinéarités, nous considérons des méthodes numériques traitant des signaux à bande non-limitée qui à la place ont un "taux d'innovation borné"; Deuxièmement, pour revenir dans le domaine des signaux à bande limitée, nous concevons des "convertisseurs analogique-numérique virtuels" Plusieurs méthodes numériques sont construites afin d'être à bilan de puissance garanti, avec une précision d'ordre élevé et un un ordre de régularité contrôlable. Leurs propriétés sont étudiées: existence et unicité, ordre de précision, dispersion, mais aussi, résolution fréquentielle au delà de la fréquence de Nyquist, rejet du repliement ainsi que noyaux reproduisants et noyaux de Peano. Cette approche révèle des ponts entre l'analyse numérique, le traitement du signal et la théorie de l'échantillonnage généralisé en mettant en relation la précision, la propriété de reproduction des polynômes, la bande passante ou les bancs de filtre de Legendre, etc. Nous exposons un cadre systématique pour transformer des schémas électronique en équations puis en simulations. Ce cadre est ensuite appliqué à des circuits audio représentatifs, contenant à la fois des équations différentielles ordinaires et des équation algebro-différentielles. Un travail spécifique est dédié à la modélisation SHP des amplificateurs opérationnels. Enfin, nous revisitons la modélisation des SHP dans le cadre de l'algèbre géométrique, ce qui ouvre des perspectives pour l'encodage de la structure géométrique des équations
This work addresses the real-time simulation of nonlinear audio circuits. In this thesis, we use the port-Hamiltonian (pH) formalism to guarantee power balance and passivity. Moreover, we adopt a continuous-time functional framework to represent "virtual analog" signals and propose to approximate solutions by projection over time frames. As a main result, we establish a sufficient condition on projectors to obtain time-continuous power-balanced trajectories. Our goal is twofold: first, to manage frequency-bandwidth expansion due to nonlinearities, we consider numerical engines processing signals that are not bandlimited but, instead, have a "finite rate of innovation"; second, to get back to the bandlimited domain, we design "virtual analog-to-digital converters". Several numerical methods are built to be power-balanced, high-order accurate, with a controllable regularity order. Their properties are studied: existence and uniqueness, accuracy order and dispersion, but also, frequency resolution beyond the Nyquist frequency, aliasing rejection, reproducing and Peano kernels. This approach reveals bridges between numerical analysis, signal processing and generalised sampling theory, by relating accuracy, polynomial reproduction, bandwidth, Legendre filterbanks, etc. A systematic framework to transform schematics into equations and simulations is detailed. It is applied to representative audio circuits (for the UVI company), featuring both ordinary and differential-algebraic equations. Special work is devoted to pH modelling of operational amplifiers. Finally, we revisit pH modelling within the framework of Geometric Algebra, opening perspectives for structure encoding

This research focuses on biologically inspired audio signal processing using programmable analog circuitry. This research is inspired by the biology of the human cochlea since biology far outperforms any engineered system at converting audio signals into meaningful electrical signals. The human cochlea efficiently decomposes any sound into the respective frequency components by harnessing the resonance nature of the basilar membrane, essentially forming a bank of bandpass filters. In a similar fashion, this work revolves around developing a filter bank composed of continuous-time, low-power, analog bandpass filters that serve as the core front end to this silicon audio-processing system. Like biology, the individual bandpass filters are tuned to have narrow bandwidths, moderate amounts of resonance, and exponentially spaced center frequencies. This audio front end serves to efficiently convert incoming sounds into information useful to subsequent signal-processing elements, and it does so by performing a frequency decomposition of the waveform with extremely low-power consumption and real-time operation. To overcome mismatch and offsets inherent in CMOS processes, floating-gate transistors are used to precisely tune the time constants in the filters and to allow programmability of analog components.

La presente tesis buscó analizar y aplicar herramientas de productividad y mejora en el proceso de ensamblaje de mangueras hidráulicas en la empresa Contix S.A. La propuesta de mejora continua tuvo como objetivos: reducir los tiempos de entrega del producto final del proceso de ensamblaje; analizar, identificar y mejorar las demoras en los tiempos de operación, proponer una adecuada distribución de planta y minimizar las fallas de las máquinas. Además, se utilizó técnicas de ingeniería, como por ejemplo; diagrama de actividades, diagrama de flujo, diagrama de recorrido. También el estudio de tiempo es fundamental para establecer los tiempos necesarios para cada operación. Con estos métodos y herramientas de ingeniería se logró cumplir con el tiempo de entrega de los productos ensamblados y tener una distribución de planta ordenada que permitió una mayor fluidez de los operarios y del producto. Como resultado más importante se obtuvo un aumento en la productividad de 52%, consiguiendo reducir el tiempo de entrega del producto. Por consiguiente, aumentando la satisfacción del cliente. The following thesis seeks to analyze and apply productivity tools, in order to improve the assembly process of hydraulic hoses in the Company Contix S.A. The improvement proposal continue aims to reduce the delivery time of the final product of the assembly process; analyze, identify and improve the delays in the operation times. To propose an appropriate distribution of plant and to minimize the machines’ failures. In addition, engineering techniques will be used, such as; Activity Diagram (UML), Flow Diagram (or Flowchart), Circuit Diagram. It is also crucial the Study of time for determining the time required for each operation. These methods and engineering tools will allow to comply with the assembled products’ delivery time and also have an orderly distribution plant allowing greater fluidity of operators and product. As the most important result, an improved productivity of 52% will be achieved, reducing the delivery time of the product. As a result, the increase of customer satisfaction.

Au cours des dernières années, le réseau électrique connait une transformation rapide avec la pénétration massive des unités de production renouvelables et distribuées. Le concept de microgrids (micro-réseau électrique) est un élément clés de cette transition énergétique. Ces micro-réseaux sont constitués par un ensemble de plusieurs unités de production distribuées (DGUs), d'unités de stockage (SUs) et de charges interconnectées par des lignes électriques. Un microgrid peut être installé dans plusieurs endroits, par exemple dans des maisons, des hôpitaux, des quartiers, etc. et fonctionne soit en mode connecté au réseau principale, soit en mode isolé (autonome). Les microgrids sont confrontés à plusieurs défis liés à la garantie de la stabilité, la cybersécurité, l'optimisation des coûts énergétiques, la gestion de l'énergie, la qualité de l'énergie, etc. Dans ce travail, nous concentrons notre attention sur le contrôle des microgrids à courant continu en mode de fonctionnement autonome. La principale contribution de cette thèse est l’établissement de lois de commande par retour d’état distribuées assurant un partage de courant proportionnel entre les unités de production, une régulation de la tension moyenne des lignes et un équilibrage simultané des états de charge des éléments de stockage. En partant de l'hypothèse que les agents (DGU ou SU) ont les mêmes paramètres physiques, la preuve de la convergence exponentielle et globale est donnée en l’absence d’une connaissance de la charge présente sur le réseau. La thèse est divisée en trois parties. La première partie présente le concept des microgrids, un état de l’art sur leurs stratégies de contrôle et les préliminaires mathématiques nécessaires tout au long du manuscrit. La deuxième partie constitue la contribution théorique de cette thèse et aborde la synthèse de lois de contrôle distribuées, garantissant les objectifs envisagés en l’absence d’une connaissance de la charge variable sur le réseau et même en cas de perturbation constantes au niveau de l’entrée de commande. Cette garantie est apportée en considérant trois actions intégrales distribuées de type consensus. Dans la troisième partie, les contrôleurs proposés sont évalués dans différents scénarios par le biais de simulation Matlab/Simulink et de tests Hardware-in-the-Loop (HIL) en temps réel. Les résultats montrent que les objectifs de contrôle sont atteints avec succès, ce qui illustre l'efficacité de la méthodologie de contrôle proposée
In recent years, the power grid has undergone a rapid transformation with the massive penetration of renewable and distributed generation units. The concept of microgrids is a key element of this energy transition. Microgrids are made up of a set of several distributed generation units (DGUs), storage units (SUs) and loads interconnected by power lines. A microgrid can be installed in several locations, for example in houses, hospitals, a neighborhood or village, etc., and operates either in connected mode to the main grid or in isolated (autonomous) mode. Microgrids are facing several challenges related to stability assurance, cyber-security, energy cost optimization, energy management, power quality, etc. In this work, we focus our attention on the control of islanded direct current microgrids. The main contribution is the design of a new distributed control approach to provably achieve current sharing, average voltage regulation and state-of-charge balancing simultaneously with global exponential convergence. The main tools are consensus in multi-agent systems, passivity, Lyapunov stability, linear matrix inequalities, etc. The thesis is divided into three parts. The First part presents the concept of microgrids, a literature review of their control strategies and the mathematical preliminaries required throughout the manuscript. The second part deals with the design of the proposed distributed control approach to achieve the considered objectives. The system is augmented with three distributed consensus-like integral actions, and a distributed-based static state feedback control architecture is proposed. Starting from the assumption that the agents (DGUs or SUs) have the same physical parameters, we provide proof of global exponential convergence. Moreover, the proposed control approach is distributed, i.e., each agent exchange relative information with only its neighbors through sparse communication networks. The proposed controllers do not need any information about the parameters of the power lines neither the topology of the microgrid. The control objectives are reached despite the unknown load variation and constant disturbances. In the third part, the proposed distributed controllers are assessed in different scenarios through Matlab/Simulink simulation and real-time Hardware-in-the-Loop experiment. The results show that the control objectives are successfully achieved, illustrating the effectiveness of the proposed control methodology

Over the year of time, the evolution of modern application of signal processing has followed the trends of so called current mode, when signals, representing the information being processed, are in the form of current. In contrast to the conventional mode which utilized electric voltage, the current mode circuit can exhibit higher bandwidth, better signal linearity, higher slew rate and lower power consumption. Since they are designed for lower voltage swings, smaller supply voltage can be used. The current differencing buffered (CDBA) amplifier can operate in both current mode and voltage mode, which provides flexibility. This project discusses implementation of lossless grounded negative inductor circuits (and application thereof), and oscillator circuit, using single CDBA. CDBA is designed using AD844 IC.

The reduction of the minimum feature size of an MOS transistor for digital VLSI circuits has been ongoing for the past few decades. As the channel length is scaled down into deep sub micrometer dimensions, the lower power supply voltage is required to ensure the device reliability. To be compatible with digital VLSI technologies, analogue integrated circuits, which can operate at low supply voltages, are also receiving significant attention. This has resulted in development of various current mode analog building blocks and operational transresistance amplifiers (OTRA) is one among those. The OTRA is high gain current input voltage output device, both the input and output terminals are characterized by low impedance. OTRA being a current mode building block inherits the advantages of current mode processing, the input terminals are virtually grounded leading to circuits that are insensitive to stray capacitances. Being a current processing device the OTRA has a bandwidth independent of the device gain and is also not slew limited in the same manner as an OP-AMP. Operational Transresistance Amplifiers are used in various type of applications namely filters, oscillators, multivibrators, multiplier and squarer etc. These all designs benefit from current mode approach of OTRA in this project a systematic review of the available literature on OTRA has been presented and are further studied and implemented. These OTRA based designs are best suited for the low power and high speed applications apart from its traditional field of application.

碩士
國立雲林科技大學
電子與光電工程研究所碩士班
100
In this paper, we present an innovative continuous-time light-emitting diodes (LED) dimming circuit , that is used to enhance performance and service life of the light-emitting diodes, and improve the resolution of the LED current . The method proposed in this paper the analog signal to digital signal by the Time-Division-Adder (TDA), and through the digital filter unfold of the number of bits. Finally, the weighted current quantitative digital signal is a current output. TDA is built on the pulse width modulation signal, through the delay of the average amount of finishing to get the digital signal output with a linear change. In order to improve the TDA output amount of data, add the digital filter with interpolation. After increasing the amount of data each time interval, the weighted current quantitative digital signal is a current output at last. To available LED current modulation results.

Delta-sigma modulators are currently a very popular technique for making high-resolution analog-to-digital and digital-to-analog converters. These oversampled data converters have several advantages over conventional Nyquist-rate converters, including an insensitivity to many analog component imperfections, a simpler antialiasing filter and reduced accuracy requirements in the sample and hold. Though the initial uses of delta-sigma modulators were in the audio field, the development of bandpass modulators opened up the application range to radar systems, digital communication systems and instruments which convert IF, or even RF, analog signals directly to digital form. This thesis presents a method used to analyze and synthesize continuous-time delta-sigma modulators for given specifications. A fourth-order prototype continuous-time bandpass delta-sigma modulator employing g[subscript m]-LC resonator structure is demonstrated on a PCB board and measurement results corroborate the theory. To allow the construction of very high performance delta-sigma modulators, this thesis presents an architecture for a multibit DAC constructed from unit elements which shapes element mismatches. Theoretical analysis and simulation shows that this architecture greatly increases the noise attenuation in the band-of-interest and facilitates the use of multibit quantization in delta-sigma modulators. The methods presented in this thesis will allow high-frequency wideband bandpass delta-sigma modulators to be constructed.
Graduation date: 1996

碩士
國立中山大學
電機工程學系研究所
97
This thesis presents an automatic tuning circuit that it is focused on compensation for the filter’s frequency error resulting from the variation of fabrication process, supply voltage and temperature. We utilize a tunable operational transconductance amplifier and a capacitor to form a single-time constant circuit (STC). When we input a reference signal to this circuit, the output of STC circuit can produce a controllable delay time clock. The tuning circuit uses the constant delay time to tune the frequency of the filter. The design of the STC circuit is simple and it has less chip area. All circuits are designed by using the parameters of TSMC 0.35um mixed signal process, and the supply voltage is 3V. The simulation result shows that the filter’s 3-dB frequency error can be controlled by less than 7% as the filter is under the condition of over a range of supply voltages(±10％), operating temperatures(-20 ℃to 70℃ ) and five models of SPICE model.

碩士
國立中山大學
電機工程學系研究所
96
In this thesis, a simple on-chip automatic frequency tuning circuit is presented. The tuning circuit is improved from voltage-controlled filter (VCF) frequency tuning circuit. We use a single time constant (STC) circuit to substitute the voltage-controlled filter. The STC circuit can produce a controllable delay time clock. The tuning circuit uses the constant delay time to tune the frequency of the filter. The design of a STC circuit is easy. Because the circuit is simple, the tuning circuit has less chip area and less power consumption. The circuit has been fabricated with 0.35μm CMOS technology. It operates with supply voltages ±1.5 V. The filter operates at a 3-dB frequency of 10MHz. In simulation, the frequency tuning circuit has a 3-dB frequency tuning error of less than 12% and the power consumption less than 9.05mW over a range of supply voltages (±10%), operating temperatures (-20℃ to 70℃) and five models of SPICE model.

This work investigates energy-efficient approximate computation for solving differential equations. It extends the analog computing techniques to a new paradigm: continuous-time hybrid computation, where both analog and digital circuits operate in continuous time. In this approach, the time intervals in the digital signals contain important information. Unlike conventional synchronous digital circuits, continuous-time digital signals offer the benefits of adaptive power dissipation and no quantization noise. Two prototype chips have been fabricated in 65 nm CMOS technology and tested successfully. The first chip is capable of solving nonlinear differential equations up to 4th order, and the second chip scales up to 16th order based on the first chip. Nonlinear functions are generated by a programmable, clockless, continuous-time 8-bit hybrid architecture (ADC+SRAM+DAC). Digitally-assisted calibration is used in all analog/mixed-signal blocks. Compared to the prior art, our chips makes possible arbitrary nonlinearities and achieves 16 times lower power dissipation, thanks to technology scaling and extensive use of class-AB analog blocks. Typically, the unit achieves a computational accuracy of about 0.5% to 5% RMS, solution times from a fraction of 1 micro second to several hundred micro seconds, and total computational energy from a fraction of 1 nJ to hundreds of nJ, depending on equation details. Very significant advantages are observed in computational speed and energy (over two orders of magnitude and over one order of magnitude, respectively) compared to those obtained with a modern MSP430 microcontroller for the same RMS error.

碩士
國立臺北大學
電機工程學系
101
The increasing demand for accelerometer-based gadgets has expanded way beyond from mere automotive and navigation application portfolio to biomedical, consumer electronics and even sports facilities for performance enhancement and safety monitoring. Higher sensing range and smaller sensing resolution are ideal requirement to minimize the noise floor. For low-capacitance sensing, noise floor is dominated by the sensing circuit input referred noise contribution. As such, this work presents a simple but robust continuous-time current sensing architecture using amplitude modulation technique to compensate the low-capacitance sensing environment. The front-end amplifier used has high linearity and wider flattened transconductance enhanced by its nonlinear auxiliary differential pair that ensures robustness to third-order nonideal effects. As a result, wider sensing range of ±60g at 16mV/g minimum detectable output response from a 1mV/g input in the presence of a few pico Farad input parasitic capacitance. The test chip will be implemented using TSMC 0.35μm 2P4M process with a chip area less than 0.5 0.5 mm2.

abstract: In this work, a high resolution analog-to-digital converter (ADC) for use in harsh environments is presented. The ADC is implemented in bulk CMOS technology and is intended for space exploration, mining and automotive applications with a range of temperature variation in excess of 250°C. A continuous time (CT) sigma delta modulator employing a cascade of integrators with feed forward (CIFF) architecture in a single feedback loop topology is used for implementing the ADC. In order to enable operation in the intended application environments, an RC time constant tuning engine is proposed. The tuning engine is used to maintain linearity of a 10 ksps 20 bit continuous time sigma delta ADC designed for spectroscopy applications in space. The proposed circuit which is based on master slave architecture automatically selects on chip resistors to control RC time constants to an accuracy range of ±5% to ±1%. The tuning range, tuning accuracy and circuit non-idealities are analyzed theoretically. To verify the concept, an experimental chip was fabricated in JAZZ .18µm 1.8V CMOS technology. The tuning engine which occupies an area of .065mm2; consists of only an integrator, a comparator and a shift register. It can achieve a signal to noise and distortion ratio (SNDR) greater than 120dB over a ±40% tuning range.
Dissertation/Thesis
Ph.D. Electrical Engineering 2011

Continuous-time (CT) Delta-Sigma Modulators (DSMs) have re-gained popularity recently for oversampling analog-to-digital conversion, because they are more suitable for low supply voltage implementation than their discrete-time (DT) counterparts, among other reasons. To the state of art at the low voltage front, a CT O.5-V audio-band DSM with a return-to-open feedback digital-to-analog converter has been reported. However, the O.5-V CT DSM has a limited performance of 74-dB SNDR due to clock jitters and other factors caused by the ultralow supply.
Finally, a O.5-V 2-1 cascaded CT DSM with SCR feedback is proposed. A new synthesis method is presented. Transistor-level simulations show that a 98dB SNDR is achieved over a 25-kHz signal bandwidth with a 6.4MHz sampling frequency and 350muW power consumption under a 0.5-V supply.
In this thesis, three novel ULV audio-band CT DSMs with high signal-to-noise-plus-distortion ratio (SNDR) are reported for a nominal supply of O.5V. The first one firstly realizes a switched-capacitor-resistor (SCR) feedback at O.5V, enabled by a fast amplifier at O.5V, for reduced clock jitter-sensitivity. Fabricated in a O.13mum CMOS process using only standard VT devices, the 3rd order modulator with distributed feedback occupies an active area of O.8mm2 . It achieves a measured SNDR of 81.2dB over a 25-kHz signal bandwidth while consuming 625muW at O.5-V. The measured modulator performance is consistent across a supply voltage range from O.5V to O.8V and a temperature range from -20°C to 90°C. Measurement results and thermal-noise calculation show that the peak SNDR is limited by thermal noise.
The scaling of the feature sizes of CMOS technologies results in a continuous reduction of supply voltage (VDD) to maintain reliability and to reduce the power dissipation per unit area for increasingly denser digital integrated circuits. The VDD for low-power digital circuits is predicted to drop to O.5V in about ten years. Ultra-low voltage (ULV) operation will also be required for the analog-to-digital converter, a universal functional block in mixed-signal integrated circuits, in situations where the benefits of using a single VDD out-weigh the overhead associated with multi-V DD solutions.
The second ULV CT DSM employs a feed-forward loop topology with SCR feedback. Designed in O.13mum CMOS process, the modulator achieves a post-layout simulation (thermal noise included) result of 89dB SNDR over a 25-kHz signal bandwidth. The 0.13mum CMOS chip consumes an active area of O.85mm2 and 682.5muW at O.5-V supply. It achieves an excellent measured performance of 87.8dB SNDR over a 25-kHz signal bandwidth and al02dB spurious-free dynamic range. To the best of our knowledge, this performance is the highest for DSMs in this supply voltage range. Thanks to the proposed adaptive biasing technique, the measured modulator performance is consistent across a supply voltage range from O.4V to O.75V and a temperature range from -20°C to 90°C.
Chen, Yan.
Adviser: Kong Pang Pun.
Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: .
Thesis (Ph.D.)--Chinese University of Hong Kong, 2011.
Includes bibliographical references (leaves 127-135).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract also in Chinese.

碩士
國立臺灣大學
電子工程學研究所
105
Real-time biomedical signal acquisition is very crucial in modern diagnostics. Thanks to the development of microelectronics, it is possible to integrate the bulky system into a single chip. In this thesis, we will discuss the design of an analog front-end (AFE) which converts the weak analog signal into digital signal for biomedical applications while maintains signal integrity. Since the target signal, offset and flicker noise are all in the low-frequency range, the signal is susceptible to these non-idealities. To solve this problem, we apply chopping technique in this thesis. Additionally, conventional AFE system is composed of a low-noise amplifier and an ADC, which makes it not power/area efficient and also increases the circuit complexity. Our solution to this problem is applying a voltage-controlled oscillator (VCO) -based continuous-time delta-sigma modulator (CTDSM). Two circuits are implemented and verified, both of them are fabricated in TSMC 40 nm process. The first one realizes a chopped open-loop VCO-based AFE that only takes the area of 0.0145 mm2 which is the smallest chip compared to the relative AFE references while maintains SNR of 50 dB (with the bandwidth of 5 kHz). However, due to the open-loop behavior, the dynamic range is limited by VCO non-linearity. In the second circuit, we apply a VCO-based integrator, chopper, and a capacitive-feedback DAC. With the capacitive-feedback DAC the amplitude of VCO input is decreased and the dynamic range is increased to 74.9 dB (with the bandwidth of 2 kHz). The figure of merits (FoM) FoMs = 150 dB and FoMw = 1.16 pJ/conv are shown respectively. Both of them reach the best FoM compared to the state-of-the-art of relative applications. These chips are not only suitable for biomedical applications but also reach great performances in power efficiency and chip area.

This work investigates two different digital signal processing (DSP) approaches that rely on signal-derived timing: continuous-time (CT) DSP and variable-rate DSP. Both approaches enable designs of energy-efficient signal processing systems by relating their operation rates to the input activity. The majority of this thesis focuses on CT-DSP, whose operations are completely digital in CT, without the use of a clock. The spectral features of CT digital signals are analyzed first, demonstrating a general pattern of the quantization noise spectrum added in CT amplitude quantization. Then the focus is narrowed to the investigations of the system characteristics and architecture of CT digital infinite-impulse-response (IIR) filters, which are barely studied in the previous work on this topic. This thesis discusses and addresses previously unreported stability issue in CT digital IIR filters with the presence of delay-line mismatches and proposes an innovative method to design high-order CT digital IIR filters with only two tap delays. Introducing an event detector allows the operation rate of a CT digital IIR filter to closely track the input activity even though it is a feedback system. For the first time, the filtered CT digital signal is converted to a synchronous digital signal. This facilitates integrating the CT digital filter and conventional discrete-time systems and expands the applications of the former. This discussion uses a computationally efficient interpolation filter to improve the signal accuracy of the synchronous digital output. On the circuit level, a new delay-cell design is introduced. It ensures low jitter, good matching, robust communication with adjacent circuits and event-independent delay. An integrated circuit (IC) with all these ideas adopted was fabricated in a TSMC 65 nm LP CMOS process. It is the first IC implementation of a CT digital IIR filter. It can process signals with a data rate up to 20 MHz. Thanks to the IIR response and the 16-bit resolution used in the system, the implemented filter can achieve a frequency response much more versatile and accurate than the CT digital filters in prior art. The implemented system features an agile power adaptive to input activity, varying from 2.32mW (full activity) to 40μW (idle) with no power-management circuitry. The second part of the thesis discusses a variable-rate DSP capable of processing samples with a variable sampling rate. The clock rate in the variable-rate DSP tracks the input sampling rate. Compared to a fixed-rate DSP, the proposed system has a lower output data rate and hence is more computationally efficient. A reconstruction filter with a variable cutoff frequency is used to reconstruct the output. The signal-to-noise ratio remains fixed when the sampling rate changes.

This work presents novel continuous-time delta-sigma modulator architectures with low-power consumption and improved signal transfer functions which are suitable for wideband A/D conversion in wireless applications, e.g., 3G and 4G receivers. The research has explored two routes for improving the overall performance of continuous-time delta-sigma modulator. The first part of this work proposes the use of the power efficient Successive-Approximations (SAR) architecture, instead of the conventional Flash ADC, as the internal quantizer of the delta-sigma modulator. The SAR intrinsic latency has been addressed by means of a faster clock for the quantizer as well as full-period delay compensation. The use of SAR quantizer allows for increasing the resolution while reducing the total power consumption and complexity. A higher resolution quantizer, made feasible by the SAR, would allow implementing more aggressive noise shaping to facilitate wideband delta-sigma A/D conversion at lower over-sampling-rates. As proof of concept, a first-order CT delta-sigma modulator with a 5-bit SAR quantizer is designed and implemented in a 130 nm CMOS process which achieves 62 dB dynamic range over 1.92 MHz signal bandwidth meeting the requirements of the WCDMA standard. The prototype modulator draws 3.1 mW from a single 1.2 V supply and occupies 0.36 mm2 of die area. The second part of this research addresses the issue of out-of-band peaking in the signal-transfer-function (STF) of the widely used feedforward structure. The STF peaking is harmful to the performance of the modulator as it allows an interferer to saturate the quantizer and result in severe harmonic distortion and instability. As a remedy to this problem a general low-pass and peaking-free STF design methodology has been proposed which allows for implementing an all-pole filter in the input signal path for any given NTF. Based on the proposed method, the STF peaking of any feedforward modulator can be eliminated using extra feed-in paths to all the integrator inputs. A major drawback of the conventional feedforward topology having low-pass STF is the large sensitivity of the STF to the coefficients. In particular, component mismatch, due to random errors in the relative values of individual resistors or capacitors, can significantly degrade the anti-aliasing of the CT modulator and give rise to the unwanted STF peaking. To solve this problem two new architectures, namely dual-feedback and dual-feed-in are proposed which allow us to synthesize a low-pass STF with a smaller number of coefficients than the feedforward structure. The dual-feedback structure which shows significantly lower sensitivity to coefficient mismatch is extensively analyzed and simulated. Also for proof of concept a third-order modulator is implemented in a 130 nm CMOS process which achieves 76 dB dynamic-range over 5 MHz signal bandwidth meeting, for example, the requirements of a DVB-H receiver standard. In addition the modulator shows 77 dB anti-aliasing and less than 0.1 dB worst-case STF peaking. The measured power consumption of the modulator is 6 mW from a single 1.2 V and the die area is 0.56 mm2.

碩士
國立臺灣大學
電子工程學研究所
106
Sensor systems are becoming more and more important with the progress of IOT and AI. Besides, we hope to integrate whole sensors system which includes sensor interface circuit and digital processor in one chip. Therefore, this thesis focuses on the power and area efficient analog front end (AFE) design. Conventional sensor interface circuit consists of a low noise amplifier and an analog to digital converter (ADC). It is inefficient on both power consumption and area, and also complex to design. To solve the above problem, this thesis uses two voltage control oscillator (VCO) based circuits as the integrator and quantizer to implement the 2nd-order continuous time delta-sigma modulator (CTDSM), merging an ADC with the AFE. This thesis implements and measures the CTDSM in TSMC 180 nm CMOS process. This work uses a VCO and a counter as an integrator. Furthermore, we add another VCO with frequency-to-digital converter as a quantizer. Due to the first-order noise shaping characteristic of the second-stage. The whole loop shows second-order noise shaping. The second-stage quantizes the signal as a digital thermometer code with dynamic element matching (DEM), we do not need the dynamic weighted averaging (DWA). The core area of the chip is 0.19 mm2. This chip using sampling frequency at 1 MHz, with supply voltage of 1.2 V. This chip achieves the signal-to-noise-and-distortion-ratio of 62.5 dB. The power consumption of this chip is 52.4 μW, and the FoMs of the work is 143.7 dB. This chip meets bio-AFE requirement and is outstanding on power consumption and chip area.

abstract: A dual-channel directional digital hearing aid (DHA) front-end using a fully differential difference amplifier (FDDA) based Microphone interface circuit (MIC) for a capacitive Micro Electro Mechanical Systems (MEMS) microphones and an adaptive-power analog font end (AFE) is presented. The Microphone interface circuit based on FDDA converts the capacitance variations into voltage signal, achieves a noise of 32 dB SPL (sound pressure level) and an SNR of 72 dB, additionally it also performs single to differential conversion allowing for fully differential analog signal chain. The analog front-end consists of 40dB VGA and a power scalable continuous time sigma delta ADC, with 68dB SNR dissipating 67u¬W from a 1.2V supply. The ADC implements a self calibrating feedback DAC, for calibrating the 2nd order non-linearity. The VGA and power scalable ADC is fabricated on 0.25 um CMOS TSMC process. The dual channels of the DHA are precisely matched and achieve about 0.5dB gain mismatch, resulting in greater than 5dB directivity index. This will enable a highly integrated and low power DHA
Dissertation/Thesis
Ph.D. Electrical Engineering 2011

Esta tese estuda o projecto e o comportamento de filtros em tempo contínuo de muito-alta-frequência. A motivação deste trabalho foi a investigação de soluções de filtragem para canais de leitura em sistemas de gravação e reprodução de dados em suporte magnético, com custos e consumo (tamanho total inferior a 1 mm2 e consumo inferior a 1mW/polo), inferiores aos circuitos existentes. Nesse sentido, tal como foi feito neste trabalho, o rápido desenvolvimento das tecnologias de microelectrónica suscitou esforços muito significativos a nível mundial com o objectivo de se investigarem novas técnicas de realização de filtros em circuito integrado monolítico, especialmente em tecnologia CMOS (Complementary Metal Oxide Semiconductor). Apresenta-se um estudo comparativo a diversos níveis hierárquicos do projecto, que conduziu à realização e caracterização de soluções com as características desejadas. Num primeiro nível, este estudo aborda a questão conceptual da gravação e transmissão de sinal bem como a escolha de bons modelos matemáticos para o tratamento da informação e a minimização de erro inerente às aproximações na conformidade aos princípios físicos dos dispositivos caracterizados. O trabalho principal da tese é focado nos níveis hierárquicos da arquitectura do canal de leitura e da realização em circuito integrado do seu bloco principal – o bloco de filtragem. Ao nível da arquitectura do canal de leitura, apresenta-se um estudo alargado sobre as metodologias existentes de adaptação de sinal e recuperação de dados em suporte magnético. Este desígnio aparece no âmbito da proposta de uma solução de baixo custo, baixo consumo, baixa tensão de alimentação e baixa complexidade, alicerçada em tecnologia digital CMOS, para a realização de um sistema DFE (Decision Feedback Equalization) com base na igualização de sinal utilizando filtros integrados analógicos em tempo contínuo. Ao nível do projecto de realização do bloco de filtragem e das técnicas de implementação de filtros e dos seus blocos constituintes em circuito integrado, concluiu-se que a técnica baseada em circuitos de transcondutância e condensadores, também conhecida como filtros gm-C (ou transcondutância-C), é a mais adequada para a realização de filtros adaptativos em muito-alta-frequência. Definiram-se neste nível hierárquico mais baixo, dois subníveis de aprofundamento do estudo no âmbito desta tese, nomeadamente: a pesquisa e análise de estruturas ideais no projecto de filtros recorrendo a representações no espaço de estados; e, o estudo de técnicas de realização em tecnologia digital CMOS de circuitos de transcondutância para a implementação de filtros integrados analógicos em tempo contínuo. Na sequência deste estudo, apresentam-se e comparam-se duas estruturas de filtros no espaço de estados, correspondentes a duas soluções alternativas para a realização de um igualador adaptativo realizado por um filtro contínuo passa-tudo de terceira ordem, para utilização num canal de leitura de dados em suporte magnético. Como parte constituinte destes filtros, apresenta-se uma técnica de realização de circuitos de transcondutância, e de realização de condensadores lineares usando matrizes de transístores MOSFET para processamento de sinal em muito-alta-frequência realizada em circuito integrado usando tecnologia digital CMOS submicrométrica. Apresentam-se métodos de adaptação automática capazes de compensar os erros face aos valores nominais dos componentes, devidos às tolerâncias inerentes ao processo de fabrico, para os quais apresentamos os resultados de simulação e de medição experimental obtidos. Na sequência deste estudo, resultou igualmente a apresentação de um circuito passível de constituir uma solução para o controlo de posicionamento da cabeça de leitura em sistemas de gravação/reprodução de dados em suporte magnético. O bloco proposto é um filtro adaptativo de primeira ordem, com base nos mesmos circuitos de transcondutância e técnicas de igualação propostos e utilizados na implementação do filtro adaptativo de igualação do canal de leitura. Este bloco de filtragem foi projectado e incluído num circuito integrado (Jaguar) de controlo de posicionamento da cabeça de leitura realizado para a empresa ATMEL em Colorado Springs, e incluído num produto comercial em parceria com uma empresa escocesa utilizado em discos rígidos amovíveis.
This thesis studies the design and behavior of continuous-time very-high-frequency filters. The motivation of this work was the search for filtering solutions for the readchannel in recording and reproduction of data on magnetic media systems, with costs and consumption (total size less than 1 mm2 and consumption under 1mW/pole), lower than the available circuits. Accordingly, as was done in this work, the rapid development of microelectronics technology raised very significant efforts worldwide in order to investigate new techniques for implementing such filters in monolithic integrated circuit, especially in CMOS technology (Complementary Metal Oxide Semiconductor). We present a comparative study on different hierarchical levels of the project, which led to the realization and characterization of solutions with the desired characteristics. In the first level, this study addresses the conceptual question of recording and transmission of signal and the choice of good mathematical models for the processing of information and minimization of error inherent in the approaches and in accordance with the principles of the characterized physical devices. The main work of this thesis is focused on the hierarchical levels of the architecture of the read channel and the integrated circuit implementation of its main block - the filtering block. At the architecture level of the read channel this work presents a comprehensive study on existing methodologies of adaptation and signal recovery of data on magnetic media. This project appears in the sequence of the proposed solution for a lowcost, low consumption, low voltage, low complexity, using CMOS digital technology for the performance of a DFE (Decision Feedback Equalization) based on the equalization of the signal using integrated analog filters in continuous time. At the project level of implementation of the filtering block and techniques for implementing filters and its building components, it was concluded that the technique based on transconductance circuits and capacitors, also known as gm-C filters is the most appropriate for the implementation of very-high-frequency adaptive filters. We defined in this lower level, two sub-levels of depth study for this thesis, namely: research and analysis of optimal structures for the design of state-space filters, and the study of techniques for the design of transconductance cells in digital CMOS circuits for the implementation of continuous time integrated analog filters. Following this study, we present and compare two filtering structures operating in the space of states, corresponding to two alternatives for achieving a realization of an adaptive equalizer by the use of a continuous-time third order allpass filter, as part of a read-channel for magnetic media devices. As a constituent part of these filters, we present a technique for the realization of transconductance circuits and for the implementation of linear capacitors using arrays of MOSFET transistors for signal processing in very-high-frequency integrated circuits using sub-micrometric CMOS technology. We present methods capable of automatic adjustment and compensation for deviation errors in respect to the nominal values of the components inherent to the tolerances of the fabrication process, for which we present the simulation and experimental measurement results obtained. Also as a result of this study, is the presentation of a circuit that provides a solution for the control of the head positioning on recording/playback systems of data on magnetic media. The proposed block is an adaptive first-order filter, based on the same transconductance circuits and equalization techniques proposed and used in the implementation of the adaptive filter for the equalization of the read channel. This filter was designed and included in an integrated circuit (Jaguar) used to control the positioning of the read-head done for ATMEL company in Colorado Springs, and part of a commercial product used in removable hard drives fabricated in partnership with a Scottish company.