Gotowe bibliografie tematyczne / Context Adaptive Binary Arithmetic Coding (CABAC)

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Gotowa bibliografia na temat „Context Adaptive Binary Arithmetic Coding (CABAC)”

Autor: Grafiati

Data publikacji: 6 września 2023

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Artykuły w czasopismach na temat "Context Adaptive Binary Arithmetic Coding (CABAC)"

Mrudula, S. T., K. E. Srinivasa Murthy i M. N. Giri Prasad. "Optimized Context-Adaptive Binary Arithmetic Coder in Video Compression Standard Without Probability Estimation". Mathematical Modelling of Engineering Problems 9, nr 2 (28.04.2022): 458–62. http://dx.doi.org/10.18280/mmep.090222.

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CABAC is a Context Adaptive Binary Arithmetic Coder utilized in novel AVC/H.264 of video standard. AC (arithmetic coding) permits important enhancement in the compression. However, the complexity of implementation is main drawback because of slowness and hardware cost. In this paper, we propose the implementation of MPEG4/H-264 AVC against M-decoder without PE (Probability Estimation). Furthermore, in order to estimate an algorithm, we have compared many existing methods, and the comparison takes place based on power dissipation and device utilization.

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Kim, Chung Hyo, Tae Sik Kong, Young Jun Lee, Hee Dong Kim i Young Ho Ju. "High Speed Decoding of Entropy Codes in H.264/AVC Based on a Symbol Prediction". Key Engineering Materials 321-323 (październik 2006): 1262–65. http://dx.doi.org/10.4028/www.scientific.net/kem.321-323.1262.

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H.264/AVC is adopted as a next generation moving picture compression standard. Context-based Adaptive Binary Arithmetic Coding (CABAC) is the major entropy coding algorithm employed in H.264/AVC. Although the performance gain of H.264/AVC is mostly resulted from CABAC, it is difficult to implement a high-throughput decoder due to its decoding complexity. Although CABAC excludes a multiplication, the algorithm is basically sequential and needs large computations to compute some important variables, which are range, offset and context variables. Therefore, it is difficult to achieve fast decoding performance. In this paper, a prediction scheme is proposed to decode maximally two bits at a time and thus to reduce overall decoding time. A CABAC decoder based on the proposed prediction scheme reduces total cycles by 24% compared to conventional decoders.

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Li, Wei, i Peng Ren. "Efficient CABAC Bit Estimation for H.265/HEVC Rate-Distortion Optimization". International Journal of Multimedia Data Engineering and Management 6, nr 4 (październik 2015): 40–55. http://dx.doi.org/10.4018/ijmdem.2015100103.

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The entropy coding of context-adaptive binary arithmetic coding (CABAC) has been utilized in the H.265/HEVC for higher coding efficiency. But the related complexity also causes a bottleneck for its low-delay applications, owing to the employment of inter-symbol dependency in CABAC. In this paper, a fast bit-rate estimation method is proposed to skip the actual entropy coding of CABAC in mode decision to meet the requirement of low-delay implementations. The presented scheme firstly parses the characteristics of syntax elements and then guided by the principle of CABAC, an efficient scheme is derived following. It is very beneficial for reducing the computational complexity and saving the encoding time in H.265/HEVC mode decision. Experimental results demonstrate that the proposed fast algorithm can reduce the CABAC encoding time by 68% in average with negligible degradation in the rate-distortion performance.

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Jiang, Hong Xu, Wei Zhao, Xiao Hong Zhang i Jin Yuan Lu. "Design and Implementation of CABAC Parallelization on Multicore DSP". Applied Mechanics and Materials 340 (lipiec 2013): 685–90. http://dx.doi.org/10.4028/www.scientific.net/amm.340.685.

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This work mainly focus on the design and implementation of context-based adaptive binary arithmetic coding (CABAC) parallelization on multicourse digital signal processor (DSP) platform. Syntax elements partitioning based on load balancing is proposed to achieve data parallelization of CABAC. On the multicourse DSP, a task-dispatch structure is proposed. Inter-core communication is achieved by combination of shared memory and interrupt. And inter-core synchronization is achieved by combination of shared variable and hardware semaphore. The above structure makes the overall system clearer and program control easier. A speedup of 2.77 is obtained.

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Tran, Dinh-Lam, Xuan-Tu Tran, Duy-Hieu Bui i Cong-Kha Pham. "An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder". Electronics 9, nr 4 (23.04.2020): 684. http://dx.doi.org/10.3390/electronics9040684.

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HEVC-standardized encoders employ the CABAC (context-based adaptive binary arithmetic coding) to achieve high compression ratios and video quality that supports modern real-time high-quality video services. Binarizer is one of three main blocks in a CABAC architecture, where binary symbols (bins) are generated to feed the binary arithmetic encoder (BAE). The residual video data occupied an average of 75% of the CABAC’s work-load, thus its performance will significantly contribute to the overall performance of whole CABAC design. This paper proposes an efficient hardware implementation of a binarizer for CABAC that focuses on low area cost, low power consumption while still providing enough bins for high-throughput CABAC. On the average, the proposed design can process upto 3.5 residual syntax elements (SEs) per clock cycle at the maximum frequency of 500 MHz with an area cost of 9.45 Kgates (6.41 Kgates for the binarizer core) and power consumption of 0.239 mW (0.184 mW for the binarizer core) with NanGate 45 nm technology. It shows that our proposal achieved a high overhead-efficiency of 1.293 Mbins/Kgate/mW, much better than the other related high performance designs. In addition, our design also achieved a high power-efficiency of 8288 Mbins/mW; this is important factor for handheld applications.

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Ramos, Fábio Luís Livi, Bruno Zatt, Marcelo Schiavon Porto i Sergio Bampi. "Novel Multiple Bypass Bin Scheme and Low-power Approach for HEVC CABAC Binary Arithmetic Encoder". Journal of Integrated Circuits and Systems 13, nr 3 (12.12.2018): 1–11. http://dx.doi.org/10.29292/jics.v13i3.3.

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HEVC is one of the most recent video coding standards, designed to face a new age of video processing challenges, such as higher video resolutions and limited traffic share bandwidth. The HEVC standard is divided into multiple steps, whereas the entropy encoding is the final stage before the coded bitstream generation. The CABAC (Context Adaptive Binary Arithmetic Coding) is the sole algorithm used for the entropy encoding at HEVC, providing reduced final bitstream generation, at the cost of increasing computational complexity and difficulties for parallelism opportunities. One of the novelties of the CABAC for the HEVC is the increase of certain types of input data (called bins), which have smaller dependencies among them (i.e. bypass bins), thus leading to the possibility to process multiples of them in parallel at once. The present work introduces a novel scheme for multiple bypass bins processing at once, leading to increasing bins-per-cycle throughput compared to related works. Moreover, the new technique is suitable for achieving a BAE (Binary Arithmetic Encoder) architecture (the CABAC critical part) able to process 8K UHD videos. Along with the multiple bypass bins technique, a low-power approach is achieved, based on statistical analysis of the recommended test video sequences, accomplishing around 15%of power savings.

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Kokare, Parmeshwar, i Dr MasoodhuBanu. N.M. "Review on using Region of interest for HEVC". International Journal of Engineering & Technology 7, nr 2.4 (10.03.2018): 93. http://dx.doi.org/10.14419/ijet.v7i2.4.11173.

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High efficiency video coding (HEVC) is the latest video compression standard. The coding efficiency of HEVC is 50% more than the preceding standard Advanced video coding (AVC). HEVC has gained this by introducing many advanced techniques such as adaptive block partitioning system known as quadtree, tiles for parallelization, improved entropy coding called Context-Adaptive Binary Arithmetic Coding (CABAC), 35 intra prediction modes (IPMs), etc. all these techniques have increased the complexity of encoding process due to which real time application of HEVC for video transfer is not yet convenient. The main objective of this paper is to provide a review of the recent developments in HEVC, particularly focusing on using region of interest (ROI) for reducing the encoding process time. Summaries of the different approaches to identify the ROI are discussed and a new method is explained.

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Huang, Kai, De Ma, Rong-jie Yan, Hai-tong Ge i Xiao-lang Yan. "High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding". Journal of Zhejiang University SCIENCE C 14, nr 6 (czerwiec 2013): 449–63. http://dx.doi.org/10.1631/jzus.c1200250.

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Fu, Chen, Heming Sun, Zhiqiang Zhang i Jinjia Zhou. "A Highly Pipelined and Highly Parallel VLSI Architecture of CABAC Encoder for UHDTV Applications". Sensors 23, nr 9 (26.04.2023): 4293. http://dx.doi.org/10.3390/s23094293.

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Recently, specifically designed video codecs have been preferred due to the expansion of video data in Internet of Things (IoT) devices. Context Adaptive Binary Arithmetic Coding (CABAC) is the entropy coding module widely used in recent video coding standards such as HEVC/H.265 and VVC/H.266. CABAC is a well known throughput bottleneck due to its strong data dependencies. Because the required context model of the current bin often depends on the results of the previous bin, the context model cannot be prefetched early enough and then results in pipeline stalls. To solve this problem, we propose a prediction-based context model prefetching strategy, effectively eliminating the clock consumption of the contextual model for accessing data in memory. Moreover, we offer multi-result context model update (MCMU) to reduce the critical path delay of context model updates in multi-bin/clock architecture. Furthermore, we apply pre-range update and pre-renormalize techniques to reduce the multiplex BAE’s route delay due to the incomplete reliance on the encoding process. Moreover, to further speed up the processing, we propose to process four regular and several bypass bins in parallel with a variable bypass bin incorporation (VBBI) technique. Finally, a quad-loop cache is developed to improve the compatibility of data interactions between the entropy encoder and other video encoder modules. As a result, the pipeline architecture based on the context model prefetching strategy can remove up to 45.66% of the coding time due to stalls of the regular bin, and the parallel architecture can also save 29.25% of the coding time due to model update on average under the condition that the Quantization Parameter (QP) is equal to 22. At the same time, the throughput of our proposed parallel architecture can reach 2191 Mbin/s, which is sufficient to meet the requirements of 8 K Ultra High Definition Television (UHDTV). Additionally, the hardware efficiency (Mbins/s per k gates) of the proposed architecture is higher than that of existing advanced pipeline and parallel architectures.

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Sjövall, Panu, Ari Lemmetti, Jarno Vanne, Sakari Lahti i Timo D. Hämäläinen. "High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications". ACM Transactions on Design Automation of Electronic Systems 27, nr 4 (31.07.2022): 1–34. http://dx.doi.org/10.1145/3491215.

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High Efficiency Video Coding (HEVC) is the key enabling technology for numerous modern media applications. Overcoming its computational complexity and customizing its rich features for real-time HEVC encoder implementations, calls for automated design methodologies. This article introduces the first complete High-Level Synthesis (HLS) implementation for HEVC intra encoder on FPGA. The C source code of our open-source Kvazaar HEVC encoder is used as a design entry point for HLS that is applied throughout the whole encoder design process, from data-intensive coding tools like intra prediction and discrete transforms to more control-oriented tools such as context-adaptive binary arithmetic coding (CABAC). Our prototype is run on Nokia AirFrame Cloud Server equipped with 2.4 GHz dual 14-core Intel Xeon processors and two Intel Arria 10 PCIe FPGA accelerator cards with 40 Gigabit Ethernet. This proof-of-concept system is designed for hardware-accelerated HEVC encoding and it achieves real-time 4K coding speed up to 120 fps. The coding performance can be easily scaled up by adding practically any number of network-connected FPGA cards to the system. These results indicate that our HLS proposal not only boosts development time, but also provides previously unseen design scalability with competitive performance over the existing FPGA and ASIC encoder implementations.

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Rozprawy doktorskie na temat "Context Adaptive Binary Arithmetic Coding (CABAC)"

Martins, André Luis Del Mestre. "Projeto da arquitetura de hardware para binarização e modelagem de contextos para o CABAC do padrão de compressão de vídeo H.264/AVC". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2011. http://hdl.handle.net/10183/28742.

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O codificador aritmético binário adaptativo ao contexto adotado (CABAC – Context-based Adaptive Binary Arithmetic Coding) pelo padrão H.264/AVC a partir de perfil Main é o estado-da-arte em termos de eficiência de taxa de bits. Entretanto, o CABAC ocupa 9.6% do tempo total de processamento e seu throughput é limitado pelas dependências de dados no nível de bit (LIN, 2010). Logo, atingir os requisitos de desempenho em tempo real nos níveis mais altos do padrão H.264/AVC se torna uma tarefa árdua em software, sendo necesário então, a aceleração do CABAC através de implementações em hardware. As arquiteturas de hardware encontradas na literatura para o CABAC focam no Codificador Aritmético Binário (BAE - Binary Arithmetic Encoder) enquanto que a Binarização e Modelagem de Contextos (BCM – Binarization and Context Modeling) fica em segundo plano ou nem é apresentada. O BCM e o BAE juntos constituem o CABAC. Esta dissertação descreve detalhadamente o conjunto de algoritmos que compõem o BCM do padrão H.264/AVC. Em seguida, o projeto de uma arquitetura de hardware específica para o BCM é apresentada. A solução proposta é descrita em VHDL e os resultados de síntese mostram que a arquitetura alcança desempenho suficiente, em FPGA e ASIC, para processar vídeos no nível 5 do padrão H.264/AVC. A arquitetura proposta é 13,3% mais rápida e igualmente eficiente em área que os melhores trabalhos relacionados nestes quesitos.
Context-based Adaptive Binary Arithmetic Coding (CABAC) adopted in the H.264/AVC main profile is the state-of-art in terms of bit-rate efficiency. However, CABAC takes 9.6% of the total encoding time and its throughput is limited by bit-level data dependency (LIN, 2010). Moreover, meeting real-time requirement for a pure software CABAC encoder is difficult at the highest levels of the H.264/AVC standard. Hence, speeding up the CABAC by hardware implementation is required. The CABAC hardware architectures found in the literature focus on the Binary Arithmetic Encoder (BAE), while the Binarization and Context Modeling (BCM) is a secondary issue or even absent in the literature. Integrated, the BCM and the BAE constitute the CABAC. This dissertation presents the set of algorithms that describe the BCM of the H.264/AVC standard. Then, a novel hardware architecture design for the BCM is presented. The proposed design is described in VHDL and the synthesis results show that the proposed architecture reaches sufficiently high performance in FPGA and ASIC to process videos in real-time at the level 5 of H.264/AVC standard. The proposed design is 13.3% faster than the best works in these items, while being equally efficient in area.

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Chen, Jian-Wen, i 陳建文. "A Hardware Context-Based Adaptive Binary Arithmetic Decoder for H.264 Advanced Video Coding". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/54034717558332274025.

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碩士
國立清華大學
資訊工程學系
93
We propose a hardware accelerator for Context-based Adaptive Binary Arithmetic decoding (CABAC) in H.264/AVC. We also propose an efficient memory system for easy integration with other components such as motion compensation and IDCT. For getting neighboring data, we propose a pipelined architecture to reduce clock cycles. We develop an efficient finite state machine so that our design can generate one bit every 2 to 3 clock cycles. Our design is verified in FPGA prototyping by using an ARM integrator. Experimental result shows that our design is capable of decoding main profile 720P (1280 x 720) video stream at 30 fps.

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Liu, Po-Sheng, i 劉普昇. "A Hardware Context-Based Adaptive Binary Arithmetic Encoder for H.264 Advanced Video Coding". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/39127786299837173975.

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碩士
國立清華大學
資訊工程學系
94
We propose a full hardware implementation of Context-Based Adaptive Binary Arithmetic Encoder. Our architecture includes a 14-way context pair generator composed of binarization and context modeling, a 3-stage pipelined circuit for getting neighboring data and a 3-mode 4-stage pipelined arithmetic encoder with forwarding logic for context update. Our arithmetic encoder architecture can process one bin per cycle. The whole encoder is able to process 0.77 bins per cycle on the average.

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Części książek na temat "Context Adaptive Binary Arithmetic Coding (CABAC)"

Karwowski, Damian, i Marek Domański. "Improved Context-Based Adaptive Binary Arithmetic Coding in MPEG-4 AVC/H.264 Video Codec". W Computer Vision and Graphics, 25–32. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-15907-7_4.

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Streszczenia konferencji na temat "Context Adaptive Binary Arithmetic Coding (CABAC)"

Lee, Szu-Wei, i C. C. Jay Kuo. "Complexity modeling for context-based adaptive binary arithmetic coding (CABAC) in H.264/AVC decoder". W Optical Engineering + Applications, redaktor Andrew G. Tescher. SPIE, 2007. http://dx.doi.org/10.1117/12.730962.

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Tang, Zhiwei. "One adaptive binary arithmetic coding system based on context". W 2011 International Conference on Computer Science and Service System (CSSS). IEEE, 2011. http://dx.doi.org/10.1109/csss.2011.5974482.

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Kirchhoffer, Heiner, Detlev Marpe, Karsten Muller i Thomas Wiegand. "Context-adaptive binary arithmetic coding for frame-based animated mesh compression". W 2008 IEEE International Conference on Multimedia and Expo (ICME). IEEE, 2008. http://dx.doi.org/10.1109/icme.2008.4607441.

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WANG, Shu, Zejie KUANG, Guohe ZHANG i Li SUN. "Fast Hardware Implementation of Renormalization for Context-based Adaptive Binary Arithmetic Coding". W 2019 IEEE International Conference of Intelligent Applied Systems on Engineering (ICIASE). IEEE, 2019. http://dx.doi.org/10.1109/iciase45644.2019.9074006.

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Chen, Renjie, Aaron Stillmaker i Bevan Baas. "Architecture and 28 nm CMOS Design of a 1886 MBin/sec Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder". W 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2022. http://dx.doi.org/10.1109/vlsi-soc54400.2022.9939655.

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Haase, Paul, Stefan Matlage, Heiner Kirchhoffer, Christian Bartnik, Heiko Schwarz, Detlev Marpe i Thomas Wiegand. "State-Based Multi-parameter Probability Estimation for Context-Based Adaptive Binary Arithmetic Coding". W 2020 Data Compression Conference (DCC). IEEE, 2020. http://dx.doi.org/10.1109/dcc47342.2020.00024.

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Shuguang Su, Yueming Su i Zhen Xiong. "An implement strategy of context-based adaptive binary arithmetic coding in H.264". W 2011 International Conference on Multimedia Technology (ICMT). IEEE, 2011. http://dx.doi.org/10.1109/icmt.2011.6002123.

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Liu, Po-Sheng, Jian-Wen Chen i Youn-Long Lin. "A Hardwired Context-Based Adaptive Binary Arithmetic Encoder for H. 264 Advanced Video Coding". W 2007 International Symposium on VLSI Design, Automation and Test. IEEE, 2007. http://dx.doi.org/10.1109/vdat.2007.373239.

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Su, Yan, i Xie Cheng Jun. "Application study of piecewise context-based adaptive binary arithmetic coding combined with modified LZC". W SPIE Optics + Photonics, redaktor Andrew G. Tescher. SPIE, 2006. http://dx.doi.org/10.1117/12.679317.

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Xiao, Guang, Xu-li Shi, Ping An, Zhao-yang Zhang, Ge Gao i Guo-wei Teng. "A optimized context-based adaptive binary arithmetic coding algorithm in progressive H.264 encoder". W Defense and Security Symposium, redaktorzy Zia-ur Rahman, Stephen E. Reichenbach i Mark A. Neifeld. SPIE, 2006. http://dx.doi.org/10.1117/12.665371.

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