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1
Poizat, Bruno. "A la recherche de la definition de la complexite d'espace pour le calcul des polynomes a la maniere de Valiant". Journal of Symbolic Logic 73, nr 4 (grudzień 2008): 1179–201. http://dx.doi.org/10.2178/jsl/1230396913.
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RésuméNous définissons une classe de suites de polynômes, calculés par des circuits de complexité polynomiale comprenant des additions, des soustractions. des multiplications et des sommations de Valiant. Nous montrons que cette classe est close pour la prise de la fonction-coefficient. définie au paragraphe 3 de cet article; nous en déduisons l'existence d'un circuit de complexité 72.n2, calculant le coefficient binomial de deux nombres de n chiffres, donnés en base 2. Il est par ailleurs facile de construire un circuit de complexité 17.n + 2 calculant la factorielle d'un nombre de n chiffres. La présence de 2.n sommations d'effet exponentiel dans chacun de ces circuits en affecte gravement l'intérêt pratique. II est peu probable, ou du moins peu souhaitable. qu'on puisse éliminer ces sommations sans explosion, car cela provoquerait la catastrophe cryptographique que redoutent tous les banquiers; néanmoins, nous ne savons pas séparer la classe définie ici de celle des suites de polynômes calculables en un nombre polynomial d'opérations arithmétiques. Cela n'a rien de surprenant, vu la très grande affinité qu'elle a avec la classe PSPACE: nous montrons en effet que cette classe est identique à la classe VPSPACE, définie antérieurement par Koiran et Perifel, qui apparaît ici sous une forme bien plus maniable que l'originale.
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Raton, Gwenaëlle. "Les circuits courts alimentaires". Multitudes 92, nr 3 (21.09.2023): 79–85. http://dx.doi.org/10.3917/mult.092.0079.
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Cet article illustre de façon concrète et détournée les relations villes-campagnes. Les circuits courts alimentaires sont considérés comme vertueux (réduction des intermédiaires et des distances, « locavorisme »), mais qu’en est-il vraiment de leur durabilité, compte-tenu de leur complexité logistique ? Pour le producteur, premier maillon de la chaîne, la commercialisation et le transport représentent travail et coûts supplémentaires. Les circuits courts ne sont pas moins énergivores : flux entre fermes et points de vente fragmentés en une multitude de petits volumes. L’auteur propose plusieurs formes d’organisation pour pallier à ces inconvénients : mutualiser le transport entre producteurs partenaires et promouvoir une coopération logistique territoriale, consolider le transfert de flux en le déléguant à un prestataire extérieur. L’enjeu de la logistique et le rôle des intermédiaires non commerciaux sont clé.
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Berthoz, Alain, Jean-Pierre Benoit i Alexandrine Saint-Cast. "Penser son corps : quand le cerveau simplifie la complexité". Enfances & Psy N° 97, nr 3 (30.10.2023): 15–28. http://dx.doi.org/10.3917/ep.097.0015.
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Comment le corps est-il intégré ? Les travaux des neurosciences et de la neurophysiologie révèlent aujourd’hui les circuits cérébraux qui permettent de passer du corps à sa pensée. Ces phénomènes pluriels d’une grande complexité se réalisent grâce à la simplexité qui intègre aussi l’inhibition et l’oubli. L’unification corps-cerveau participe à l’identité. Elle s’inscrit dans l’intersubjectivité par empathie et sympathie. La recherche, différentes expériences neurophysiologiques, confirment ces descriptions et permettent de mieux comprendre les troubles psychomoteurs.
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Basso Fossali, Pierluigi. "La complexité régulatrice des discours programmateurs. Circuits sociaux de la modalisation et instances critiques". Langue française N°206, nr 2 (2020): 45. http://dx.doi.org/10.3917/lf.206.0045.
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Clément, Camille. "Le lieu agricole périurbain : un analyseur de la complexité des constructions territoriales entre actions politiques, débats publics et pratiques spatiales". Nouvelles perspectives en sciences sociales 10, nr 1 (4.02.2015): 27–57. http://dx.doi.org/10.7202/1028436ar.
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Cet article a pour objectif d’éclairer la complexité des constructions et appropriations territoriales à partir de l’étude croisée des actions politiques, débats publics et pratiques spatiales de la communauté de communes du Pays de Lunel (Languedoc). En cours de périurbanisation, ce territoire mise sur son ancrage agricole et rural pour se différencier des agglomérations en expansion de Montpellier et de Nîmes. C’est donc par la thématique agricole qu’une étude qualitative du SCOT (Schéma de Cohérence Territoriale), d’un projet de circuits courts et d’un pôle oenotouristique (actions politiques) ont été étudiés afin de saisir cinq débats publics (étude de la presse régionale et intercommunautaire) qui sont directement en lien avec les choix politiques réalisés par cette instance territoriale. Au final, l’étude montre que ces actions politiques et débats publics doivent être mis en relation avec les pratiques spatiales observées dans le territoire. Ce n’est qu’à l’échelle du lieu agricole périurbain que ces trois notions s’alimentent mutuellement afin de montrer la complexité des appropriations territoriales, appropriations par le politique (actions politiques et débats publics) et appropriations par la pratique.
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Poizat, Bruno. "Une dualité entre fonctions booléennes". Journal of the Institute of Mathematics of Jussieu 9, nr 3 (26.04.2010): 633–52. http://dx.doi.org/10.1017/s1474748010000083.
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RésuméSi k est un corps fini, toute fonction f(x1, … , xm) de {0, 1}m dans k s'écrit de manière unique comme un polynôme, à coefficients dans k, de degré un ou zéro en chacune de ses variables ; on peut donc lui associer une fonction f*(x1, … , xm), sa duale inverse, qui exprime les coefficients de son polynôme canonique. Nous considérons l'improbable hypothèse que la classe P(k), formée des suites de fonctions calculables en un nombre d'opérations (additions et multiplications) de croissance polynomialement bornée, soit close par dualité ; nous montrons qu'elle équivaut à une hypothèse bien connue en Théorie de la Complexité sous le nom de P = #pP, où p est la caractéristique de k.Dans une première section, nous exposons ce résultat lorsque k = ℤ/2ℤ, c'est-à-dire dans le cadre des calculs booléens classiques ; sa démonstration évite l'emploi d'un polynôme universel comme le hamiltonien : ses ingrédients sont d'une part la réduction parcimonieuse des circuits aux termes, et d'autre part la constatation que les expressions arithmétiques ont une duale très facile à calculer.Dans la deuxième section, nous traitons le cas général, en introduisant une classe SP(k) obtenue par sommation à partir de la classe P(k) ; nous vérifierons dans la quatrième section l'équivalence des hypothèses SP(k) = P(k) et #pP = P. Nous y définissons également une notion de transformation, dont la dualité est un cas particulier. Les transformations forment un groupe isomorphe à GL2(k), avec un sous-groupe B(k) de transformations que nous qualifions de bénignes, car elles n'ont que peu d'effet sur la complexité des fonctions ; nous montrons que toutes les transformations non-bénignes ont à peu près la même influence sur la complexité des fonctions, sauf si k = F3 ou k = F5 ; dans ces deux cas exceptionnels, la transformation de Fourier joue un rôle particulier.Dans la troisième section, nous considérons des fonctions de km dans k ; nous n'y trouvons pas des classes de complexité vraiment nouvelles, mais seulement un groupe de transformations plus riche.La quatrième section introduit l'égalité #P = P dans le paysage ; quant à la cinquième et dernière, elle examine le lien entre nos résultats et ceux de Guillaume Malod concernant la clôture par fonction-coefficient de diverses classes de complexité pour le calcul des polynômes à la manière de Valiant.Nous nous sommes efforcés de rédiger cet article de manière à ce qu'il puisse être lu par des personnes non spécialisées en algorithmie.
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Coureau, Didier. "The Brain’s Cinematic Metaphors (Images of Thought, Thinking Forms)". IRIS, nr 36 (30.06.2015): 85–101. http://dx.doi.org/10.35562/iris.1574.
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Cet article s’inscrit dans le prolongement d’une recherche que je mène depuis une vingtaine d’années sur les rapports entre cinéma et pensée. En m’appuyant en particulier sur les réflexions de Gilles Deleuze, Félix Guattari, Edgar Morin, j’ai ainsi pu créer les concepts de « complexité esthétique », « noosphère filmique », « cinématographie des flux ». Suite à l’évocation de créateurs-penseurs du cinéma muet d’avant-garde (Epstein, Dulac, Artaud), sont ici abordés des films d’Amos Gitaï, Chris Marker, Jean-Luc Godard, Alain Resnais et Andreï Tarkovski. L’intitulé, « Les métaphores filmiques du cerveau » indique que l’approche de la relation cinéma-cerveau est d’ordre philosophique, mais également d’ordre poétique. Si le cinéma est à même de donner forme à la pensée, il invente aussi des circuits cérébraux — sonores et visuels — qui lui permettent de devenir forme « pensante ».
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Coureau, Didier. "The Brain’s Cinematic Metaphors (Images of Thought, Thinking Forms)". IRIS, nr 36 (30.06.2015): 85–101. http://dx.doi.org/10.35562/iris.1574.
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Cet article s’inscrit dans le prolongement d’une recherche que je mène depuis une vingtaine d’années sur les rapports entre cinéma et pensée. En m’appuyant en particulier sur les réflexions de Gilles Deleuze, Félix Guattari, Edgar Morin, j’ai ainsi pu créer les concepts de « complexité esthétique », « noosphère filmique », « cinématographie des flux ». Suite à l’évocation de créateurs-penseurs du cinéma muet d’avant-garde (Epstein, Dulac, Artaud), sont ici abordés des films d’Amos Gitaï, Chris Marker, Jean-Luc Godard, Alain Resnais et Andreï Tarkovski. L’intitulé, « Les métaphores filmiques du cerveau » indique que l’approche de la relation cinéma-cerveau est d’ordre philosophique, mais également d’ordre poétique. Si le cinéma est à même de donner forme à la pensée, il invente aussi des circuits cérébraux — sonores et visuels — qui lui permettent de devenir forme « pensante ».
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Hirata, Yuichi, Masaki Nakanishi, Shigeru Yamashita i Yasuhiko Nakashima. "An efficient conversion of quantum circuits to a linear nearest neighbor architecture". Quantum Information and Computation 11, nr 1&2 (styczeń 2011): 142–66. http://dx.doi.org/10.26421/qic11.1-2-10.
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Several promising implementations of quantum computation rely on a Linear Nearest Neighbor (LNN) architecture, which arranges quantum bits on a line, and allows neighbor interactions only. Therefore, several specific circuits have been designed on an LNN architecture. However, a general and efficient conversion method for an arbitrary circuit has not been established. Therefore, this paper gives an efficient conversion technique to convert quantum circuits to an LNN architecture. When a quantum circuit is converted to an LNN architecture, the objective is to reduce the size of the additional circuit added by the conversion and the time complexity of the conversion. The proposed method requires less additional circuitry and time complexity compared with naive techniques. To develop the method, we introduce two key theorems that may be interesting on their own. In addition, the proposed method also achieves less overhead than some known circuits designed from scratch on an LNN architecture.
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Uchizawa, Kei, Rodney Douglas i Wolfgang Maass. "On the Computational Power of Threshold Circuits with Sparse Activity". Neural Computation 18, nr 12 (grudzień 2006): 2994–3008. http://dx.doi.org/10.1162/neco.2006.18.12.2994.
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Circuits composed of threshold gates (McCulloch-Pitts neurons, or perceptrons) are simplified models of neural circuits with the advantage that they are theoretically more tractable than their biological counterparts. However, when such threshold circuits are designed to perform a specific computational task, they usually differ in one important respect from computations in the brain: they require very high activity. On average every second threshold gate fires (sets a 1 as output) during a computation. By contrast, the activity of neurons in the brain is much sparser, with only about 1% of neurons firing. This mismatch between threshold and neuronal circuits is due to the particular complexity measures (circuit size and circuit depth) that have been minimized in previous threshold circuit constructions. In this letter, we investigate a new complexity measure for threshold circuits, energy complexity, whose minimization yields computations with sparse activity. We prove that all computations by threshold circuits of polynomial size with entropy O(log n) can be restructured so that their energy complexity is reduced to a level near the entropy of circuit states. This entropy of circuit states is a novel circuit complexity measure, which is of interest not only in the context of threshold circuits but for circuit complexity in general. As an example of how this measure can be applied, we show that any polynomial size threshold circuit with entropy O(log n) can be simulated by a polynomial size threshold circuit of depth 3. Our results demonstrate that the structure of circuits that result from a minimization of their energy complexity is quite different from the structure that results from a minimization of previously considered complexity measures, and potentially closer to the structure of neural circuits in the nervous system. In particular, different pathways are activated in these circuits for different classes of inputs. This letter shows that such circuits with sparse activity have a surprisingly large computational power.
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Mohan, Navya, i J. P. Anita. "Early Detection of Clustered Trojan Attacks on Integrated Circuits Using Transition Delay Fault Model". Cryptography 7, nr 1 (28.01.2023): 4. http://dx.doi.org/10.3390/cryptography7010004.
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The chances of detecting a malicious reliability attack induced by an offshore foundry are grim. The hardware Trojans affecting a circuit’s reliability do not tend to alter the circuit layout. These Trojans often manifest as an increased delay in certain parts of the circuit. These delay faults easily escape during the integrated circuits (IC) testing phase, hence are difficult to detect. If additional patterns to detect delay faults are generated during the test pattern generation stage, then reliability attacks can be detected early without any hardware overhead. This paper proposes a novel method to generate patterns that trigger Trojans without altering the circuit model. The generated patterns’ ability to diagnose clustered Trojans are also analyzed. The proposed method uses only single fault simulation to detect clustered Trojans, thereby reducing the computational complexity. Experimental results show that the proposed algorithm has a detection ratio of 99.99% when applied on ISCAS’89, ITC’99 and IWLS’05 benchmark circuits. Experiments on clustered Trojans indicate a 46% and 34% improvement in accuracy and resolution compared to a standard Automatic Test Pattern Generator (ATPG)Tool.
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BIRGET, JEAN-CAMILLE. "FACTORIZATIONS OF THE THOMPSON–HIGMAN GROUPS, AND CIRCUIT COMPLEXITY". International Journal of Algebra and Computation 18, nr 02 (marzec 2008): 285–320. http://dx.doi.org/10.1142/s0218196708004457.
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We consider the subgroup lpGk,1 of length preserving elements of the Thompson–Higman group Gk,1 and we show that all elements of Gk,1 have a unique lpGk,1 · Fk,1 factorization. This applies to the Thompson–Higman group Tk,1 as well. We show that lpGk,1 is a "diagonal" direct limit of finite symmetric groups, and that lpTk,1 is a k∞ Prüfer group. We find an infinite generating set of lpGk,1 which is related to reversible boolean circuits. We further investigate connections between the Thompson–Higman groups, circuits, and complexity. We show that elements of Fk,1 cannot be one-way functions. We show that describing an element of Gk,1 by a generalized bijective circuit is equivalent to describing the element by a word over a certain infinite generating set of Gk,1; word length over these generators is equivalent to generalized bijective circuit size. We give some coNP-completeness results for Gk,1 (e.g., the word problem when elements are given by circuits), and [Formula: see text]-completeness results (e.g., finding the lpGk,1 · Fk,1 factorization of an element of Gk,1 given by a circuit).
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Upadhyay, Shipra, R. A. Mishra, R. K. Nagaria i S. P. Singh. "DFAL: Diode-Free Adiabatic Logic Circuits". ISRN Electronics 2013 (10.02.2013): 1–12. http://dx.doi.org/10.1155/2013/673601.
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The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been developed to explain the energy dissipation in the proposed circuit. Performance of the proposed logic is analyzed and compared with CMOS and reported adiabatic logic styles. Also the layout of proposed inverter circuit has been drawn. Subsequently proposed topology-based various logic gates, combinational and sequential circuits and multiplier circuit are designed and simulated. The simulations were performed by VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In proposed inverter the energy efficiency has been improved to almost 60% up to 100 MHz in comparison to conventional CMOS circuits. The present research provides low power high speed results up to 100 MHz, and proposal has proven to be used in power aware high-performance VLSI circuitry.
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Cai, Haoyuan, Qi Ye i Dong-Ling Deng. "Sample complexity of learning parametric quantum circuits". Quantum Science and Technology 7, nr 2 (1.03.2022): 025014. http://dx.doi.org/10.1088/2058-9565/ac4f30.
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Abstract Quantum computers hold unprecedented potentials for machine learning applications. Here, we prove that physical quantum circuits are probably approximately correct learnable on a quantum computer via empirical risk minimization: to learn a parametric quantum circuit with at most n c gates and each gate acting on a constant number of qubits, the sample complexity is bounded by O ~ ( n c + 1 ) . In particular, we explicitly construct a family of variational quantum circuits with O(n c+1) elementary gates arranged in a fixed pattern, which can represent all physical quantum circuits consisting of at most n c elementary gates. Our results provide a valuable guide for quantum machine learning in both theory and practice.
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Zandevakili, Hamed, Ali Mahani i Mohsen Saneei. "An accurate and fast reliability analysis method for combinational circuits". COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering 34, nr 3 (5.05.2015): 979–95. http://dx.doi.org/10.1108/compel-06-2014-0137.
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Purpose – One of the main issues which microelectronics industry encounter is reliability as feature sizes scale down to nano-design level. The purpose of this paper is to provide a probabilistic transfer matrix based to find the accurate and efficient method of finding circuit’s reliability. Design/methodology/approach – The proposed method provides a probabilistic description of faulty behavior and is well-suited to reliability and error susceptibility calculations. The proposed method offers accurate circuit reliability calculations in the presence of reconvergent fanout. Furthermore, a binary probability matrix is used to not only resolve signals correlation problem but also improve the accuracy of the obtained reliability in the presence of reconverging signals. Findings – The results provide the accuracy and computation time of reliability evaluation for ISCAS85 benchmark schemes. Also, simulations have been conducted on some digital circuits involving LGSynth’91 circuits. Simulation results show that proposed solution is a fast method with less complexity and gives an accurate reliability value in comparison with other methods. Originality/value – The proposed method is the only scheme giving the low calculation time with high accuracy compared to other schemes. The library-based method also is able to evaluate the reliability of every scheme independent from its circuit topology. The comparison exhibits that a designer can save its evaluation time in terms of performance and complexity.
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Gidney, Craig. "Stim: a fast stabilizer circuit simulator". Quantum 5 (6.07.2021): 497. http://dx.doi.org/10.22331/q-2021-07-06-497.
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This paper presents “Stim", a fast simulator for quantum stabilizer circuits. The paper explains how Stim works and compares it to existing tools. With no foreknowledge, Stim can analyze a distance 100 surface code circuit (20 thousand qubits, 8 million gates, 1 million measurements) in 15 seconds and then begin sampling full circuit shots at a rate of 1 kHz. Stim uses a stabilizer tableau representation, similar to Aaronson and Gottesman's CHP simulator, but with three main improvements. First, Stim improves the asymptotic complexity of deterministic measurement from quadratic to linear by tracking the inverse of the circuit's stabilizer tableau. Second, Stim improves the constant factors of the algorithm by using a cache-friendly data layout and 256 bit wide SIMD instructions. Third, Stim only uses expensive stabilizer tableau simulation to create an initial reference sample. Further samples are collected in bulk by using that sample as a reference for batches of Pauli frames propagating through the circuit.
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CHEN, XUE, GUANGDA HU i XIAOMING SUN. "THE COMPLEXITY OF WORD CIRCUITS". Discrete Mathematics, Algorithms and Applications 02, nr 04 (grudzień 2010): 483–92. http://dx.doi.org/10.1142/s1793830910000826.
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A word circuit [1] is a directed acyclic graph in which each edge holds a w-bit word (i.e., some x ∈ {0, 1}w) and each node is a gate computing some binary function g : {0, 1}w × {0, 1}w → {0, 1}w. The following problem was studied in [1]: How many binary gates are needed to compute a ternary function f : ({0, 1}w)3 → {0, 1}w. They proved that (2 + o(1))2w binary gates are enough for any ternary function, and there exists a ternary function which requires word circuits of size (1 - o(1))2w. One of the open problems in [1] is to get these bounds tight within a low order term. In this paper we solved this problem by constructing new word circuits for ternary functions of size (1 + o(1))2w. We investigate the problem in a general setting: How many k-input word gates are needed for computing an n-input word function f : ({0, 1}w)n → {0, 1}w (here n ≥ k). We show that for any fixed n, (1 - o(1))2(n - k)w basic gates are necessary and (1 + o(1))2(n - k)w gates are sufficient (assume w is sufficiently large). Since word circuit is a natural generalization of boolean circuit, we also consider the case when w is a constant and the number of inputs n is sufficiently large. We show that [Formula: see text] basic gates are necessary and sufficient in this case.
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Jiao, Su Min, Cai Hong Wang i Xue Mei Wang. "Large-Scale Analog Circuit Evolutionary Design Using a Real-Coded Scheme". Applied Mechanics and Materials 220-223 (listopad 2012): 2036–39. http://dx.doi.org/10.4028/www.scientific.net/amm.220-223.2036.
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Analog circuits are of great importance in electronic system design. Recent evolutionary design results are usually small-scale analog circuits. This paper proposes a real-coded mechanism and uses it in the large-scale analog circuit evolutionary design. The proposed scheme evolves the circuit topology and size to a uniformed continuous space, in which the circuit representation is closed and of causality. Experimental results show that the proposed scheme can work successfully on many analog circuits with different kinds of characteristics. Comparing with other evolutionary methods before, the proposed scheme performs better on large-scale problems of circuit synthesis with higher search efficiency, lower computational complexity, and less computing time.
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LAPPAS, G., R. J. FRANK i A. A. ALBRECHT. "A COMPUTATIONAL STUDY ON CIRCUIT SIZE VERSUS CIRCUIT DEPTH". International Journal on Artificial Intelligence Tools 15, nr 02 (kwiecień 2006): 143–61. http://dx.doi.org/10.1142/s0218213006002606.
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We investigate the circuit complexity of classification problems in a machine learning setting, i.e. we attempt to find some rule that allows us to calculate a priori the number of threshold gates that is sufficient to achieve a small error rate after training a circuit on sample data [Formula: see text]. The particular threshold gates are computed by a combination of the classical perceptron algorithm with a specific type of stochastic local search. The circuit complexity is analysed for depth-two and depth-four threshold circuits, where we introduce a novel approach to compute depth-four circuits. For the problems from the UCI Machine Learning Repository we selected and investigated, we obtain approximately the same size of depth-two and depth-four circuits for the best classification rates on test samples, where the rates differ only marginally for the two types of circuits. Based on classical results from threshold circuit theory and our experimental observations on problems that are not linearly separable, we suggest an upper bound of [Formula: see text] threshold gates as sufficient for a small error rate, where [Formula: see text].
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Huang, Chun, Xinya Zhang, Panlong Li, Junwei Sun, Xuncai Zhang i Yanfeng Wang. "Design of Sixteen-Input Priority Encoder with DNA Nano Switches". Journal of Nanoelectronics and Optoelectronics 17, nr 10 (1.10.2022): 1354–65. http://dx.doi.org/10.1166/jno.2022.3281.
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With the application of DNA computing in more and more fields, the tasks are becoming more and more complex, and the scale of DNA circuits is gradually increasing. However, the current investigation of largescale circuits of DNA molecules is still a challenge. So it is crucial to optimize the performance of large-scale DNA circuits. In this paper, a large-scale digital logic circuit 16-Input-5-Output Priority Encoder is realized by using the DNA nano switches for the first time. The simulation of the 16-Input-5-Output Priority Encoder circuit shows that this method solves the problems of NOT gate instability and optimizes the DNA circuit in terms of reaction time, circuit complexity, and experimental difficulty. This paper proves the feasibility and superiority of using DNA nano switches to realize large-scale circuits, provides a new idea for realizing large-scale DNA circuits, and brings new development for the application of DNA circuits in biosensor, DNA complex computing and other fields.
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Maslov, Dmitri. "Optimal and asymptotically optimal NCT reversible circuits by the gate types". Quantum Information and Computation 16, nr 13&14 (październik 2016): 1096–112. http://dx.doi.org/10.26421/qic16.13-14-2.
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We report optimal and asymptotically optimal reversible circuits composed of NOT, CNOT, and Toffoli (NCT) gates, keeping the count by the subsets of the gate types used. This study fine tunes the circuit complexity figures for the realization of reversible functions via reversible NCT circuits. An important consequence is a result on the limitation of the use of the T-count quantum circuit metric popular in applications.
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Kombarov, Yuri Anatol'evich. "Circuit complexity lower bound for parity function in one infinite basis". Mathematical Problems of Cybernetics, nr 20 (2022): 81–118. http://dx.doi.org/10.20948/mvk-2022-81.
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The paper is devoted to realization of parity functions by circuits consisting of generalized conjunctors of infinite fan-in. We present a new circuit complexity lower bound for parity function in this model.
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Rosati, Matteo. "A learning theory for quantum photonic processors and beyond". Quantum 8 (8.08.2024): 1433. http://dx.doi.org/10.22331/q-2024-08-08-1433.
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We consider the tasks of learning quantum states, measurements and channels generated by continuous-variable (CV) quantum circuits. This family of circuits is suited to describe optical quantum technologies and in particular it includes state-of-the-art photonic processors capable of showing quantum advantage. We define classes of functions that map classical variables, encoded into the CV circuit parameters, to outcome probabilities evaluated on those circuits. We then establish efficient learnability guarantees for such classes, by computing bounds on their pseudo-dimension or covering numbers, showing that CV quantum circuits can be learned with a sample complexity that scales polynomially with the circuit's size, i.e., the number of modes. Our results show that CV circuits can be trained efficiently using a number of training samples that, unlike their finite-dimensional counterpart, does not scale with the circuit depth.
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LI, XIAOYU, GUOWU YANG, CARLOS MANUEL TORRES, DESHENG ZHENG i KANG L. WANG. "A CLASS OF EFFICIENT QUANTUM INCREMENTER GATES FOR QUANTUM CIRCUIT SYNTHESIS". International Journal of Modern Physics B 28, nr 01 (11.12.2013): 1350191. http://dx.doi.org/10.1142/s0217979213501919.
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The quantum incrementer is one of the simplest quantum operators, which exhibits basic arithmetic operations such as addition, the propagation of carry qubits and the resetting of carry qubits. In this paper, three quantum incrementer gate circuit topologies are derived and compared based upon their total number of gates, the complexity of the circuits, the types of gates used and the number of carry or ancilla qubits implemented. The first case is a generalized n-qubit quantum incrementer gate with the notation of (n:0). Two other quantum incrementer topologies are proposed with the notations of (n:n-1: RE ) and (n:n-1: RD ). A general method is derived to decompose complicated quantum circuits into simpler quantum circuits which are easier to manage and physically implement. Due to the cancelation of intermediate unitary gates, it is shown that adding ancilla qubits slightly increases the complexity of a given circuit by the order of 3n, which pales in comparison to the complexity of the original circuit of the order n2 without reduction. Finally, a simple application of the generalized n-qubit quantum incrementer gate is introduced, which is related to quantum walks.
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TANAKA, YUJI, TSUBASA ICHIKAWA, MASAHITO TADA-UMEZAKI, YUKIHIRO OTA i MIKIO NAKAHARA. "QUANTUM ORACLES IN TERMS OF UNIVERSAL GATE SET". International Journal of Quantum Information 09, nr 06 (wrzesień 2011): 1363–81. http://dx.doi.org/10.1142/s0219749911008106.
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We present a systematic construction of quantum circuits implementing Grover's database search algorithm for arbitrary number of targets. We introduce a new operator which flips the sign of the targets and evaluate its circuit complexity. We find the condition under which the circuit complexity of the database search algorithm based on this operator is less than that of the conventional one.
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Noé, Nicolas, i Oana Panaïté. "“Le dépassement réalisé d’une différence”:". Journal of French and Francophone Philosophy 32, nr 1/2 (5.11.2024): 49–68. http://dx.doi.org/10.5195/jffp.2024.1069.
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“De l’information du poème” qui clôt la partie “Éléments” dans Poétique de la Relation, représente pour le lectorat habitué à l'écriture glissantienne un chapitre assez surprenant voire confondant tant au niveau de l’approche du sujet traité que de sa mise en forme rhétorique, car c’est autour de l’opposition entre poésie et informatique que démarre son propos. Tout d’abord, on a l’impression que Glissant s'écarte des riches lieux-communs qui rythment et structurent sa pensée puisque, après quelques pages consacrées au baroque, son attention se tourne ici de manière apparemment aléatoire vers l'antagonisme entre les nouvelles technologies et le parangon de la création littéraire. L'intérêt de Glissant pour la science et les nouvelles technologies n’est certes pas une anomalie lorsque l’on considère l’ensemble de son œuvre puisque cette dernière est en effet bâtie sur un éclectisme quasi programmatique qui se manifeste à travers la pensée du rhizome et le droit à l'opacité. Cependant, la dichotomie entre “ces deux ordres de la connaissance, le poétique et le scientifique” sur laquelle repose l'hypothèse de ce court chapitre semble trancher avec la rhétorique relationnelle qui caractérise son approche. Le penseur semble même souscrire aux poncifs d’un discours d'époque réduisant la complexité des nouvelles technologies et la magnitude de leurs effets sur la société contemporaine à une simple série d’oppositions entre, d’une part, une culture humaniste qui rassemblerait une communauté en présence autour de la parole poétique menacée, et, d’autre part, le pouvoir aliénant de l’information transmise à travers des circuits non-relationnels, impersonnels, sans voix et sans visage.
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Maheswari, K., M. L. Ravi Chandra, D. Srinivasulu Reddy i V. Vijaya Kishore. "Design of Three-valued Logic Based Adder and Multiplier Circuits using Pseudo N-type CNTFETs". International Journal of Electrical and Electronics Research 11, nr 2 (30.06.2023): 518–22. http://dx.doi.org/10.37391/ijeer.110238.
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This work presents a novel technique to develop the three-valued logic (TVL) circuit schematics for very large-scale integration (VLSI) applications. The TVL is better alternative technology over the two-valued logic because it provides decreased interconnect connections, fast computation speed and decreases the chip complexity. The TVL based complicated designs such as half-adder and multiplier circuits are designed utilizing the Pseudo N-type carbon nanotube field effect transistors (CNTFETs). The proposed TVL half adder multiplier schematics are developed in HSPICE tool. Additionally, the delay and circuit area for the half- adder and multiplier circuits are investigated and compared to the complementary circuits. The memory usage and CPU time for the proposed circuits are also analyzed. It is observed that the proposed circuit designs show the improved performance up to 43.03% on an average over the complementary designs.
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Arya, Namita, i Amit Prakash Singh. "Comparative Analysis of Time and Physical Redundancy Techniques for Fault Detection". Indonesian Journal of Electrical Engineering and Computer Science 6, nr 1 (1.04.2017): 66. http://dx.doi.org/10.11591/ijeecs.v6.i1.pp66-71.
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<p>The integration level in today’s world is continuously increasing in VLSI chips. VLSI circuit verification is a major challenge in these days. Integration capacity of VLSI circuits mimics the testing complexity of circuits. There is a significant chunk of the testing cost with respect to the whole fabrication prices. Hence it is important to cut down the verification cost. Time required during testing is a main factor for the cost of a chip. This time is directly proportional to the number of testing in the circuitry. So the test set should be very small. There is one way to generate a small test set is to compact a large test set parameters. The main drawback of the compaction results on the quality of the original test set. This aspect of compaction has motivated the work present here with some methods of fault detection and avoidance techniques via redundancy logic as Time redundancy and physical redundancy.</p>
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Bach, Bao Gia, Akash Kundu, Tamal Acharya i Aritra Sarkar. "Visualizing Quantum Circuit Probability: Estimating Quantum State Complexity for Quantum Program Synthesis". Entropy 25, nr 5 (7.05.2023): 763. http://dx.doi.org/10.3390/e25050763.
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This work applies concepts from algorithmic probability to Boolean and quantum combinatorial logic circuits. The relations among the statistical, algorithmic, computational, and circuit complexities of states are reviewed. Thereafter, the probability of states in the circuit model of computation is defined. Classical and quantum gate sets are compared to select some characteristic sets. The reachability and expressibility in a space-time-bounded setting for these gate sets are enumerated and visualized. These results are studied in terms of computational resources, universality, and quantum behavior. The article suggests how applications like geometric quantum machine learning, novel quantum algorithm synthesis, and quantum artificial general intelligence can benefit by studying circuit probabilities.
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He, Xinyu. "Design of CMOS circuits through transistor sizing techniques". Applied and Computational Engineering 12, nr 1 (25.09.2023): 1–12. http://dx.doi.org/10.54254/2755-2721/12/20230279.
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With the increasingly diverse functional requirements of contemporary electronic products, the complexity of CMOS circuits often used in chips becomes higher and the number of transistors used increases. To solve the resulting performance problems of CMOS circuits, researchers have searched for many transistor sizing technologies. This paper summarizes three methods of CMOS circuit optimization. The paper introduces these three methods in terms of principle, effect, and application scenarios, and compares them respectively. Through analysis and simulation, it can be found that the use of these methods in circuit design can effectively achieve the purpose of improving speed, reducing power consumption, and improving the overall performance of the circuit. This lays a solid foundation for finally being able to present a good product with excellent performance and enhance the market competitiveness of the product. CMOS circuits are widely used, and circuit optimization is of great importance to the overall circuit design, and better optimization methods can even promote the development of the entire electronics and chip manufacturing fields.
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Wu, Jian-Feng, Shang-Shang He, Feng Wang, Yu Wang, Xin-Gang Zhao i Qi Wang. "Improved resistance matrix approach for readout of the two-dimensional resistive sensor array". Transactions of the Institute of Measurement and Control 41, nr 3 (31.05.2018): 875–82. http://dx.doi.org/10.1177/0142331218774095.
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In the readout circuits of the two-dimensional (2-D) resistive sensor arrays, various auxiliary electrical components were used to reduce their crosstalk errors but resulted in increased circuit complexity. Readout circuits with low-complexity structures were necessary for wearable electronic applications. With only several resistors and a microcontroller, readout circuit based on resistance matrix approach (RMA) achieved low complexity but suffered from small resistance range and large measurement error caused by the output ports’ internal resistances of the microcontroller. For suppressing those negative effects, we firstly proposed an improved resistance matrix approach (IRMA) by additionally sampling the voltages on all driving row electrodes in the RMA. Then the effects of the output ports’ internal resistances and the analog-to-digital converter’s accuracy for the RMA and the IRMA were simulated respectively with NI Multisim 12. Moreover, a prototype readout circuit based on the IRMA was designed and tested in actual experiments. The experimental results demonstrated that the IRMA, though it required more sampling channels and more computations, could be used in those applications needing low complexity, small measurement error and wide resistance range.
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Redkin, Nikolay P. "The generalized complexity of linear Boolean functions". Discrete Mathematics and Applications 30, nr 1 (25.02.2020): 39–44. http://dx.doi.org/10.1515/dma-2020-0004.
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AbstractWe study generalized (in terms of bases) complexity of implementation of linear Boolean functions by Boolean circuits in arbitrary functionally complete bases; the complexity of a circuit is defined as the number of gates. Let L*(n) be the minimal number of gates sufficient for implementation of an arbitrary linear Boolean function of n variables in an arbitrary functionally complete basis. We show that L*(0) = L*(1) = 3 and L*(n) = 7(n – 1) for any natural n ≥ 2.
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Kuraedov, V. I. "Applying Genetic Algorithm for test pattern generation process optimization". Herald of Dagestan State Technical University. Technical Sciences 51, nr 1 (17.04.2024): 113–22. http://dx.doi.org/10.21822/2073-6185-2024-51-1-113-122.
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Objective. Comprehensive integrated circuit (IC) verification plays a crucial role in preventing costly errors and delays in product development cycle. It includes testing interaction and compatibility of different system elements, such as central processing unit, memory and various peripheral devices. Validating IC’s compliance to the functional requirements list may take up to 70% of the design process duration. This proportion grows with complexity and size of the device under development. Consequently, the essential tasks that integrated circuit developers face are research and development of methods for cutting design complexity and reducing implementation time.Method. Conducted research regarding usage of genetic algorithm for error discovery, which could lead to a failure in the end product.Result. Collected data regarding the amounts of victims and target errors for each fault of types stuck-at-0 and stuck-at-1 for circuits from ISCAS’85 and ISCAS’89 benchmarks. It has been discovered that the proposed method is more effective in comparison to random vector generation to an extent of target errors amount for every benchmark.Conclusions. Accumulated results allow for the algorithm usage during IC design in order to reduce time consumption for circuitry validation and improve on test kits quality.
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Shibata, Tadashi, i Tadahiro Ohmi. "Implementing Intelligence in Silicon Integrated Circuits Using Neuron-Like High-Functionality Transistors". Journal of Robotics and Mechatronics 8, nr 6 (20.12.1996): 508–15. http://dx.doi.org/10.20965/jrm.1996.p0508.
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The primary objective of this article is not to present integrated circuit implementation of neural networks in the sense that neurophysiological models are constructed in electronic circuits, but to describe new-architecture intelligent electronic circuits built using a neuron-like high-functionality transistor as a basic circuit element. This has greatly reduced the VLSI hardware/software burden in carrying out intelligent data processing and would find promising applications in robotics. The transistor is a multiple-input-gate thresholding device called a neuron MOSFET (neuMOS or νMOS) due to its functional similarity to a simple neuron model. vMOS circuits are characterized by a high degree of parallelism in hardware computation, large flexibility in the hardware configuration, and a dramatic reduction in circuit complexity compared to conventional integrated circuits. As a result, a number of new-concept circuits has been developed. Examples include a real-time reconfigurable logic circuit called flexware and associative memory conducting a fully parallel search for the most similar targets. A simple hardware model for self-learning systems is also presented. The enhancement in functionality at a very elemental transistor level is critical to building human-like intelligent systems on silicon.
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Sallem, Amin, Mourad Fakhfakh, Esteban Tlelo-Cuautle i Mourad Loulou. "SODAC". International Journal of Applied Metaheuristic Computing 3, nr 4 (październik 2012): 64–83. http://dx.doi.org/10.4018/jamc.2012100104.
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It is of common use that analog designers start by optimizing the basic building bloc forming an active circuit in order to ‘optimally’ size the latter. Even though it is known a priori that the overall circuit performances will differ from the expected ones, due to the fact that the performances of the basic cells will (considerably) change because of the surrounding circuitry, such approach is very widely used. This is mainly due to the complexity of these ‘complex’ circuits. It has recently been shown that the simulation based sizing technique is a very interesting spare solution, since it allows avoiding the (very) ‘complex’ modeling task. In this paper the authors propose a simulation based optimizing tool that can handle both mono-objective and multi-objective optimization sizing problems. Viability and benefits of this tool are highlighted through some examples. Obtained results are compared to the ideal expected ones and to the ones that are obtained using the conventional approaches.
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Tan, Aaron, Rui Toh, Alfred Lim, Yongfu Li i Zhi Kong. "A Simplified Methodology to Evaluate Circuit Complexity: Doherty Power Amplifier as a Case Study". Electronics 8, nr 3 (12.03.2019): 313. http://dx.doi.org/10.3390/electronics8030313.
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This paper analyzes the circuit complexity using Doherty power amplifier (DPA) as a case study and proposes a simplistic model to characterize the design complexity of a DPA circuit. Various fundamental building blocks of the DPA circuit are discussed and modeled to formulate the model. In one of our experiments, it is observed that a reduction of up to 400% in the normalized complexity factor (NCF) could enhance the gain performance by approximately up to 40% for UHF applications. This work can be used as a common benchmarking tool to compare various types of DPA architecture and allow design teams to optimize their building blocks in the DPA circuit. This model can also potentially become a platform for the improvement of many integrated circuit design components, allowing ready integration on a wide range of next generation applications, not only limited to DPA circuits.
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Fadaei, Mohammadreza. "Designing ALU using GDI method". International Journal of Reconfigurable and Embedded Systems (IJRES) 8, nr 3 (1.11.2019): 151. http://dx.doi.org/10.11591/ijres.v8.i3.pp151-161.
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<p>As CMOS technology is continuously becoming smaller and smaller in nanoscale regimes, and circuit resistance to changes in the process for the design of the circuit is a major obstacle. Storage elements such as memory and flip-flops are particularly vulnerable to the change process. Power consumption is also another challenge in today's Digital IC Design. In modern processors, there are a large number of transistors, more than a billion transistors, which increases the temperature and the breakdown of its performance. Therefore, circuit design with low power consumption is a critical need for integrated circuits today. In this study, we deal with GDI techniques for designing logic and arithmetic circuits. We show that this logic in addition to low power consumption has little complexity so that arithmetic and logic circuits can be implemented with fewer transistors. Various circuits such as adders, differentiation and multiplexers, etc. have been designed and implemented using these techniques, and published in various articles. In this study, we review and evaluate the advantages and disadvantages of these circuits.</p>
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Sharma, Ritvik, i Sara Achour. "Compilation of Qubit Circuits to Optimized Qutrit Circuits". Proceedings of the ACM on Programming Languages 8, PLDI (20.06.2024): 272–95. http://dx.doi.org/10.1145/3656388.
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Quantum computers are a revolutionary class of computational platforms that are capable of solving computationally hard problems. However, today’s quantum hardware is subject to noise and decoherence issues that together limit the scale and complexity of the quantum circuits that can be implemented. Recently, practitioners have developed qutrit-based quantum hardware platforms that compute over 0, 1, and 2 states, and have presented circuit depth reduction techniques using qutrits’ higher energy 2 states to temporarily store information. However, thus far, such quantum circuits that use higher order states for temporary storage need to be manually crafted by hardware designers. We present , an optimizing compiler for qutrit circuits that implement qubit computations. deploys a qutrit circuit decomposition algorithm and a rewrite engine to construct and optimize qutrit circuits. We evaluate against hand-optimized qutrit circuits and qubit circuits, and find delivers up to 65% depth improvement over manual qutrit implementations, and 43-75% depth improvement over qubit circuits. We also perform a fidelity analysis and find -optimized qutrit circuits deliver up to 8.9× higher fidelity circuits than their manually implemented counterparts.
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Narayanappa, Manjula, i Siva S. Yellampalli. "An efficient floating point adder for low-power devices". International Journal of Reconfigurable and Embedded Systems (IJRES) 13, nr 2 (1.07.2024): 253. http://dx.doi.org/10.11591/ijres.v13.i2.pp253-261.
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With an increasing demand for power hungry data intensive computing, design methodologies with low power consumption are increasingly gaining prominence in the industry. Most of the systems operate on critical and noncritical data both. An attempt to generate a precision result results in excessive power consumption and results in a slower system. An attempt to generate a precision result results in excessive power consumption and results in a slower system. For non-critical data, approximate computing circuits significantly reduce the circuit complexity and hence power consumption. For non-critical data, approximate computing circuits significantly reduce the circuit complexity and hence power consumption. In this paper, a novel approximate single precision floating point adder is proposed with an approximate mantissa adder. The mantissa adder is designed with three 8-bit full adder blocks.
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Lukac, Martin, i Marek Perkowski. "Inductive learning of quantum behaviors". Facta universitatis - series: Electronics and Energetics 20, nr 3 (2007): 561–86. http://dx.doi.org/10.2298/fuee0703561l.
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In this paper studied are new concepts of robotic behaviors - deterministic and quantum probabilistic. In contrast to classical circuits, the quantum circuit can realize both of these behaviors. When applied to a robot, a quantum circuit controller realizes what we call quantum robot behaviors. We use automated methods to synthesize quantum behaviors (circuits) from the examples (examples are cares of the quantum truth table). The don't knows (minterms not given as examples) are then converted not only to deterministic cares as in the classical learning, but also to output values generated with various probabilities. The Occam Razor principle, fundamental to inductive learning, is satisfied in this approach by seeking circuits of reduced complexity. This is illustrated by the synthesis of single output quantum circuits, as we extended the logic synthesis approach to Inductive Machine Learning for the case of learning quantum circuits from behavioral examples.
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Bardales, Andrea C., Quynh Vo i Dmitry M. Kolpashchikov. "Singleton {NOT} and Doubleton {YES; NOT} Gates Act as Functionally Complete Sets in DNA-Integrated Computational Circuits". Nanomaterials 14, nr 7 (28.03.2024): 600. http://dx.doi.org/10.3390/nano14070600.
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A functionally complete Boolean operator is sufficient for computational circuits of arbitrary complexity. We connected YES (buffer) with NOT (inverter) and two NOT four-way junction (4J) DNA gates to obtain IMPLY and NAND Boolean functions, respectively, each of which represents a functionally complete gate. The results show a technological path towards creating a DNA computational circuit of arbitrary complexity based on singleton NOT or a combination of NOT and YES gates, which is not possible in electronic computers. We, therefore, concluded that DNA-based circuits and molecular computation may offer opportunities unforeseen in electronics.
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Haghparast, Majid, i Neda Dousttalab. "Design of new reversible quaternary flip-flops". International Journal of Quantum Information 15, nr 04 (22.05.2017): 1750024. http://dx.doi.org/10.1142/s0219749917500241.
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Multi-valued quantum operations have several advantages over binary operators. They decrease the number of essential data sending lines dramatically, which reduces the internal connections and thus can improve the circuit efficiency. In this paper, new reversible quaternary flip-flops are proposed which decrease the number of internal connectors and complexity of the circuits. So, the speed of circuits is increased. The implementation of synchronous sequential circuits requires memory elements. The proposed flip-flops need solely one memory element.
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Lozhkin, Sergei A., i Vadim S. Zizov. "Asymptotically sharp estimates for the area of multiplexers in the cellular circuit model". Discrete Mathematics and Applications 34, nr 2 (1.04.2024): 103–15. http://dx.doi.org/10.1515/dma-2024-0009.
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Abstract A general cellular circuit of functional and switching elements (CCFSE) is a mathematical model of integral circuits (ICs), which takes into account peculiarities of their physical synthesis. A principal feature of this model distinguishing it from the well-known classes of circuits of gates (CGs) is the presence of additional requirements on the geometry of the circuit which ensure the accounting of the necessary routing resources for IC creation. The complexity of implementation of a multiplexer function of Boolean algebra (FBA) in different classes of circuits has been extensively studied. In the present paper, we give asymptotically sharp upper and lower estimates for the area of a CCFSE implementing a multiplexer FBA of order n. We construct a family of circuit multiplexers of order n of area equal to the halved upper estimate, and provide a method of delivering the corresponding lower estimate.
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Rajeswaran, N., T. Madhu i M. Suryakalavathi. "Hardware Testable Design of Genetic Algorithm for VLSI Circuits". Applied Mechanics and Materials 367 (sierpień 2013): 245–49. http://dx.doi.org/10.4028/www.scientific.net/amm.367.245.
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Accurate and fast testing of digital circuits is very much essential in real time applications. Hardware analysis of digital circuits, which is otherwise very tedious and time consuming, is attempted using the artificial intelligence technique: Genetic Algorithms (GA). GA is used to find an input sequence to a digital circuit for testing, as it reduces the hardware utilization, complexity and computational time of the circuits. All the GA processes are simulated and implemented by using Xilinx 10.1 and SPARTAN 3E.
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Morell, William, i Jin-Woo Choi. "Design and Analysis of Self-Tanked Stepwise Charging Circuit for Four-Phase Adiabatic Logic". Journal of Low Power Electronics and Applications 14, nr 3 (27.06.2024): 34. http://dx.doi.org/10.3390/jlpea14030034.
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Adiabatic logic has been proposed as a method for drastically reducing power consumption in specialized low-power circuits. They often require specialized clock drivers that also function as the main power supply, in contrast to standard CMOS logic, and these power clocks are often a point of difficulty in the design process. A novel, stepwise charging driver circuit for four-phase adiabatic logic is proposed and validated through a simulation study. The proposed circuit consists of two identical driver circuits each driving two opposite adiabatic logic phases. Its performance relative to ideal step-charging and a standard CMOS across mismatched phase loads is analyzed, and new best practices are established. It is compared to a reference circuit consisting of one driver circuit for each phase along with a paired on-chip tank capacitor. The proposed driver uses opposite logic phases to act as the tank capacitor for each other in a “self-tanked” fashion. Each circuit was simulated in 15 nm FinFET across a variety of frequencies for an arbitrary logic operation. Both circuits showed comparable power consumption at all frequencies tested, yet the proposed driver uses fewer transistors and control signals and eliminates the explicit tank capacitors entirely, vastly reducing circuit area, complexity, and development time.
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Singh, N. S. S., N. H. Hamid i V. S. Asirvadam. "Reliability Programmed Tool and its Application for Fault Tolerance Computation". Advanced Materials Research 909 (marzec 2014): 397–404. http://dx.doi.org/10.4028/www.scientific.net/amr.909.397.
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With the continuous scaling of CMOS technology, reliability of nanobased electronic circuits is endlessly becoming a major concern. Due to this phenomenon, several computational approaches have been developed for the reliability assessment of modern logic integrated circuits. However, these analytical methodologies have a computational complexity that increases exponentially with the circuit dimension, making the whole reliability assessment process of large circuits becoming very time consuming and intractable. Therefore, to speed up the reliability assessment of large circuits, this paper firstly looks into the development of a programmed reliability tool. The Matlab-based tool is developed based on the generalization of Probabilistic Transfer Matrix (PTM) model as one of the existing reliability assessment approaches. Users have to provide description of the desired circuit in the form of Netlist that becomes the input to the programmed tool. For illustration purpose, in this paper, C17 has been used as the benchmark test circuit for its reliability computation. Secondly, reliability of a desired circuit does not only depend on its faulty gates, but it also depends on the maximum error threshold of these faulty gates above which no reliable computation is possible. For this purpose, the developed tool is employed again to find the exact error thresholds for faulty gates.
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SHIL’NIKOV, LEONID P. "CHUA’S CIRCUIT: RIGOROUS RESULTS AND FUTURE PROBLEMS". International Journal of Bifurcation and Chaos 04, nr 03 (czerwiec 1994): 489–519. http://dx.doi.org/10.1142/s021812749400037x.
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Mathematical problems arising from the study of complex dynamics in Chua’s circuit are discussed. An explanation of the extreme complexity of the structure of attractors of Chua’s circuit is given. This explanation is based upon recent results on systems with homoclinic tangencies. A number of new dynamical phenomena is predicted for those generalizations of Chua’s circuits which are described by multidimensional systems of ordinary differential equations.
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Jahandideh, Vahid, Bart Mennink i Lejla Batina. "An Algebraic Approach for Evaluating Random Probing Security With Application to AES". IACR Transactions on Cryptographic Hardware and Embedded Systems 2024, nr 4 (5.09.2024): 657–89. http://dx.doi.org/10.46586/tches.v2024.i4.657-689.
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We employ an algebraic approach to estimate the success rate of a sidechannel adversary attacking secrets of a masked circuit within the Random Probing Model (RPM), where intermediate variables of the implementation leak with a probability p. Our method efficiently handles masked linear circuits, enabling security bound estimation for practically large masking orders. For non-linear circuits, we employ a linearization technique. To reason about the security of complex structures like an S-box, we introduce a composition theorem, reducing the RPM security of a circuit to that of its constituent gadgets. Moreover, we lower the complexity of the multiplication gadget of CHES 2016 from O(n2 log(n)) to O(n2) while demonstrating its conjectured RPM security. Collectively, these novel methods enable the development of a practical masking scheme with O(n2) complexity for AES, maintaining security for a considerably high leakage rate p ≤ 0.02 ≈ 2−5.6.
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Moreno Bravo, J. A. "Development of bilateral circuits of the nervous system: From molecular mechanisms to the cerebellum and its implication in neurodevelopmental disorders". ANALES RANM 139, nr 139(03) (2023): 229–35. http://dx.doi.org/10.32440/ar.2022.139.03.rev02.
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The brain is the most complex organ we have, and it is the one that defines us as human beings. It is the basis of intelligence, of our thoughts and memories. In addition, it interprets the world through the senses, initiates movement and controls our behaviors. The correct functioning of this organ is based on the correct establishment of connectivity patterns between the millions of neurons which enable a precise and efficient communication between them. These neural networks emerge during embryonic and postnatal development. The formation of proper neuronal circuitry relies on diverse and very precisely orchestrated events controlled by specific molecular mechanisms. Therefore, failures in these early events will lead to brain pathologies and complex disorders. In the last decades, remarkable progress has been made in identifying and in understanding the mechanisms of action of the molecular that direct axon and neural circuitry development. However, their role in vivo in many aspects of neural circuit formation remains largely unknown, particularly how the impairment of this initial connectivity derives in complex neurodevelopmental pathologies. Here, I highlight part of my contributions and recent advances that shed light on the complexity of mechanisms that regulate axon guidance and the wiring of the bilateral circuits of the central nervous system. Furthermore, I discuss about how understanding the development of bilateral circuits of the cerebellum is essential to understand the emergence of diverse neurodevelopmental pathologies.
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Zulkifli, Nur Shahirah, Nooraida Samsudin, Suzanna Ridzuan Aw, Wan Farah Hanan Wan Osman, Shahreen Kasim i Tole Sutikno. "Centroidal-polygon: a new modified Euler to improve speed of resistor-inductor circuit equation". Indonesian Journal of Electrical Engineering and Computer Science 24, nr 3 (1.12.2021): 1399. http://dx.doi.org/10.11591/ijeecs.v24.i3.pp1399-1404.
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Two types of first-order circuits are resistor-capacitor (RC) and resistorinductor (RL). This paper focuses on the RL circuit equation. The centroidalpolygon (CP) scheme will be tested using SCILAB 6.0 software. This new scheme (CP scheme) is addressed to improve the speed. For the first order circuit equation, the complexity is focused on the time complexity, which is speed of the time taken to complete the simulation in the electrical part. The CP scheme is compared with the previous studies, polygon (P) and harmonic-polygon (HP). The result shows that the CP scheme is less computational and an alternative to solve the first order circuit equation, and get the result quickly compared with the previous research.