Rozprawy doktorskie na temat „Combinatorial circuits”
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Agnihotri, Ameya Ramesh. "Combinatorial optimization techniques for VLSI placement". Diss., Online access via UMI:, 2007.
Znajdź pełny tekst źródłaCox, Robert Sidney Sternberg Paul W. Sternberg Paul W. "Transcriptional regulation and combinatorial genetic logic in synthetic bacterial circuits /". Diss., Pasadena, Calif. : California Institute of Technology, 2008. http://resolver.caltech.edu/CaltechETD:etd-03042008-130011.
Pełny tekst źródłaRinderknecht, William John. "A power reduction algorithm for combinatorial CMOS circuits using input disabling". Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/36543.
Pełny tekst źródłaIncludes bibliographical references (p. 61-62).
by William John Rinderknecht.
M.S.
Hacker, Charles Hilton, i n/a. "WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design". Griffith University. School of Engineering, 2001. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20050915.172404.
Pełny tekst źródłaHacker, Charles. "WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design". Thesis, Griffith University, 2001. http://hdl.handle.net/10072/367209.
Pełny tekst źródłaThesis (Masters)
Master of Philosophy (MPhil)
School of Engineering
Science, Environment, Engineering and Technology
Full Text
Coward, Bob. "Genroute : a genetic algorithm (printed wire board (PWB) router) /". Online version of thesis, 1991. http://hdl.handle.net/1850/10711.
Pełny tekst źródłaDuran, Arqué Berta. "Combinatorial perspective on the gene expression circuits established by the CPEB-family of RNA binding proteins". Doctoral thesis, Universitat de Barcelona, 2020. http://hdl.handle.net/10803/673591.
Pełny tekst źródłaLa maduración meiótica y la embriogénesis temprana de Xenopus se dan en ausencia de transcripción. Hasta la transición materno-cigótica – después de la 12ª división embrionaria - la transcripción no se re-inicia y todos los cambios en expresión génica ocurren por mecanismos post- transcripcionales, entre los cuales destaca la poliadenilación citoplasmática. Durante su crecimiento, el oocito produce grandes cantidades de mRNA que mantiene silenciados, con una cola de poly(A) corta. En la maduración y embriogénesis, ciertos mRNAs son poliadenilados y traducidos. Cuando y cuanto cada mRNA es movilizado depende de la combinación de señales presentes en su 3’UTR y de las proteínas de unión al RNA que las reconocen. En la maduración meiótica se dan, al menos, tres olas secuenciales de poliadenilación. La primera es iniciada en respuesta a progesterona. Concretamente, la fosforilación por Aurora quinasa A causa la remodelación del complejo de represión de CPEB1 a complejo de activación, permitiendo la expresión de genes necesarios para la progresión meiótica, como Cdk1. Seguidamente, Cdk1 participa en la degradación de CPEB1 generando una segunda ola que es necesaria para la interkinesis. Por último, CPEB4, producida en la primera ola de poliadenilación y activada por fosforilación por Cdk1 abandera una tercera ola que posibilita la expresión de proteínas que mantienen el arresto en metafase-II. A diferencia de sus homólogos CPEB1 y CPEB4, los papeles de CPEB2 y CPEB3 en maduración meiótica siguen sin caracterizar. Por ello y para entender como esta familia de proteínas de unión al RNA se coordina para dictar la expresión génica hemos realizado una investigación sistemática y comparativa de las CPEBs en maduración meiótica.
Goulart, Sobrinho Edilton Furquim [UNESP]. "Uma ferramenta alternativa para síntese de circuitos lógicos usando a técnica de circuito evolutivo". Universidade Estadual Paulista (UNESP), 2007. http://hdl.handle.net/11449/87253.
Pełny tekst źródłaCoordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
Neste trabalho descreve-se uma metodologia para síntese e otimização de circuitos digitais, usando a teoria de algoritmos evolutivos e como plataforma os dispositivos reconfiguráveis, denominada Hardware Evolutivo do inglês- Evolvable Hardware - EHW. O EHW, tornou-se viável com o desenvolvimento em grande escala dos dispositivos reconfiguráveis, Programmable Logic Devices (PLD s), cuja arquitetura e função podem ser determinadas por programação. Cada circuito pode ser representado como um indivíduo em um processo evolucionário, evoluindo-o através de operações genéticas para um resultado desejado. Como algoritmo evolutivo, aplicou-se o Algoritmo Genético (AG), uma das técnicas da computação evolutiva que utiliza os conceitos da genética e seleção natural. O processo de síntese aplicado neste trabalho, inicia por uma descrição do comportamento do circuito, através de uma tabela verdade para circuitos combinacionais e a tabela de estados para os circuitos seqüenciais. A técnica aplicada busca o arranjo correto e minimizado do circuito que desempenhe uma função proposta. Com base nesta metodologia, são implementados alguns exemplos em duas diferentes representações (mapas de fusíveis e matriz de portas lógicas).
In this work was described a methodology for optimization and synthesis of digital circuits, which consist of evolving circuits through evolvable algorithms using as platforms reconfigurable devices, denominated Evolvable Hardware (EHW). It was became viable with the large scale development of reconfigurable devices, whose architecture and function can be determined by programming. Each circuit can be represented as an individual within an evolutionary process, evolving through genetic operations to desire results. Genetic Algorithm (GA) was applied as evolutionary algorithm where this technique evolvable computation as concepts of genetics and natural selection. The synthesis process applied in this work starts from a description from the circuits behavior. Trust table for combinatorial circuits and state transition table for sequential circuits were used for synthesis process. This technic applied search the correct arrange and minimized circuit which response the propose function. Based on this methodology, some examples are implemented in two different representations (fuse maps and logic gate matrices).
Nafkha, Amor. "A geometrical approach detector for solving the combinatorial optimisation problem : application in wireless communication systems". Lorient, 2006. http://www.theses.fr/2006LORIS067.
Pełny tekst źródłaThe demand for mobile communication systems with high data rates and improved link quality for a variety of applications has dramatically increased in recent years. New concepts and methods are necessary in order to cover this huge demand, which counteract or take advantage of the impairments of the mobile communication channel and optimally exploit the limited resources such as bandwidth and power. The problem of finding the least-squares solution to a system of linear equations where the unknown vector is comprised of integers, but the matrix coefficients and given vector are comprised of real numbers, arise in many applications: communications, cryptography, MC-CDMA, MIMO, to name a few. The Maximum Likelihood (ML) decoding is equivalent to finding the closest lattice point in an n-dimensional real space. In general, this problem is known to be non deterministic NP hard. In this thesis, a polynomial-time approximation method called Geometrical Intersection and Selection Detector (GISD) is applied to the MLD problem. Moreover, the proposed approach is based on two complementary "real time" operational research methods: intensification and diversification. Our approach has three important characteristics that make it very attractive for for VLSI implementation. First, It will be shown that the performance of GISD receiver is superior as compared to other sub-optimal detection methods and it provides a good approximation to the optimal detector. Second, the inherent parallel structure of the proposed method leads to a very suitable hardware implementation. Finaly, The GISD allows a near optimal performance with constant polynomial-time, O(n3), computational complexity (unlike the sphere decoding that has exponential-time complexity for low SNR). The proposed Detector can be efficiently employed in most wireless communications systems: MIMO, MC-CDMA, MIMO-CDMA etc. .
Goulart, Sobrinho Edilton Furquim. "Uma ferramenta alternativa para síntese de circuitos lógicos usando a técnica de circuito evolutivo /". Ilha Solteira : [s.n.], 2007. http://hdl.handle.net/11449/87253.
Pełny tekst źródłaBanca: José Raimundo de Oliveira
Banca: Nobuo Oki
Resumo: Neste trabalho descreve-se uma metodologia para síntese e otimização de circuitos digitais, usando a teoria de algoritmos evolutivos e como plataforma os dispositivos reconfiguráveis, denominada Hardware Evolutivo do inglês- Evolvable Hardware - EHW. O EHW, tornou-se viável com o desenvolvimento em grande escala dos dispositivos reconfiguráveis, Programmable Logic Devices (PLDs), cuja arquitetura e função podem ser determinadas por programação. Cada circuito pode ser representado como um indivíduo em um processo evolucionário, evoluindo-o através de operações genéticas para um resultado desejado. Como algoritmo evolutivo, aplicou-se o Algoritmo Genético (AG), uma das técnicas da computação evolutiva que utiliza os conceitos da genética e seleção natural. O processo de síntese aplicado neste trabalho, inicia por uma descrição do comportamento do circuito, através de uma tabela verdade para circuitos combinacionais e a tabela de estados para os circuitos seqüenciais. A técnica aplicada busca o arranjo correto e minimizado do circuito que desempenhe uma função proposta. Com base nesta metodologia, são implementados alguns exemplos em duas diferentes representações (mapas de fusíveis e matriz de portas lógicas).
Abstract: In this work was described a methodology for optimization and synthesis of digital circuits, which consist of evolving circuits through evolvable algorithms using as platforms reconfigurable devices, denominated Evolvable Hardware (EHW). It was became viable with the large scale development of reconfigurable devices, whose architecture and function can be determined by programming. Each circuit can be represented as an individual within an evolutionary process, evolving through genetic operations to desire results. Genetic Algorithm (GA) was applied as evolutionary algorithm where this technique evolvable computation as concepts of genetics and natural selection. The synthesis process applied in this work starts from a description from the circuits behavior. Trust table for combinatorial circuits and state transition table for sequential circuits were used for synthesis process. This technic applied search the correct arrange and minimized circuit which response the propose function. Based on this methodology, some examples are implemented in two different representations (fuse maps and logic gate matrices).
Mestre
Mohamed, Mohamed Hassan Wahba Ayman. "Diagnostic des erreurs de conception dans les circuits digitaux : le cas des erreurs simples". Grenoble 1, 1997. http://www.theses.fr/1997GRE10086.
Pełny tekst źródłaDuvillié, Guillerme. "Approximation, complexité paramétrée et stratégies de résolution de problèmes d'affectation multidimensionnelle". Thesis, Montpellier, 2016. http://www.theses.fr/2016MONTT321/document.
Pełny tekst źródłaIn this thesis, we focused in the Wafer-to-Wafer integration problems. These problems come from IC manufacturing. During the production of three-dimensional processors, dies have to be superimposed. Until recent, the dies were engraved on a silicon disk called wafer, then were cut, tested and sorted to suppress faulty dies and lastly superimposed one to each other.However superimposing wafers instead of dies presents several technical and financial advantages. Since faulty dies can only be dismissed when cutting the wafer, superimpose two wafers can lead to superimpose a faulty die with a viable one. In this case, the resulting stack of dies is considered as faulty. It follows that a bad assignment between the wafers can lead to a disastrous yield.In order to minimize the number of faulty dies stacks, a "failure map" of each wafer is generated during a test phase. This map gives location of the faulty dies on the wafers. The objective is then to take advantage of this map to define an assignment of the wafers to each other in order to match as many failures as possible.This problem can be modelized with Multidimensional Assignment problems. Each wafer can be seen as a vector with as many dimensions as the number of dies engraved on it. A coordinate set to zero marks a faulty die while a coordinate set to one indicates a viable one. Each seat of wafers is represented by a set of vector. Formally, an instance of a Wafer-to-Wafer integration problem is represented by m sets of n p-dimensional vectors. The objective is then to partition the vectors into n disjoint m-tuples, each tuple containing exactly one vector per set. An m-tuple represents a stack of wafers. Every m-tuple can be represented by a p-dimensional vector. Each coordinate is computed by performing the bitwise AND between the corresponding coordinates of the vectors that compose the m-tuple. In other words, a coordinate of the representative vector is equal to one if and only if this coordinate is equal to one in every vector composing the tuple. It follows that a dies stack is viable if and only if all the dies composing the stack are viable. The objective is then to maximize the overall number of ones of to minimize the overall number of zeros.The first part of the thesis is a theoretical one. We study the complexity of the considered versions of the problem with regards to natural parameters such as m, n, p or the number of zeros per vector. We show that these problems can encode more classical problems such as Maximum Clique, Minimum Vertex Cover or k-Dimensional Matching. This leads to several negative results from computational complexity, approximability or even parameterized complexity point of view. We also provide several positive results for some specific cases of the problem.In a second part, we focus on the practical solving of the problem. We provide and compare several Integer Linear Programming formulations. We also focus on performances of some approximation algorithms that we detailed in the theoretical part
Bastos, Antonio Josefran de Oliveira. "Circuitos hamiltonianos em hipergrafos e densidades de subpermutações". Universidade de São Paulo, 2016. http://www.teses.usp.br/teses/disponiveis/45/45134/tde-06092017-192427/.
Pełny tekst źródłaThe study of asymptotic behavior of densities of some substructures is one of the main areas in combinatorics. In Permutation Theory, fixed permutations ?1 and ?2 and an integer n > 0, we are interested in the behavior of densities of ?1 and ?2 among the permutations of size n. Thus, there are two natural directions we can follow. In the first direction, we are interested in finding the permutation of size n that maximizes the density of the permutations ?1 and ?2 simultaneously. We explicit the maximum density of a family of permutations between all the permutations of size n. In the second direction, we are interested in finding the permutation of size n that minimizes the density of ?1 and ?2 simultaneously. When ?1 is the identity permutation with l elements and ?2 is the reverse permutation with k elements, Myers conjectured that the minimum is achieved when we take the minimum among the permutations which do not have the occurrence of ?1 or ?2. We show that if we restrict the search space only to set of layered permutations and k > l, then the Myers\' Conjecture is true. On the other hand, in Graph Theory, the problem of finding a Hamiltonian cycle is a NP-complete problem and it is among the 21 Karp problems. Thus, one approach to attack this problem is to find conditions that a graph must meet to ensure the existence of a Hamiltonian cycle on it. The celebrated result of Dirac shows that a graph G of order n that has minimum degree at least n/2 has a Hamiltonian cycle. Following the line of Dirac, we show that give integers 1 6 l 6 k/2 and gamma > 0 there is an integer n0 > 0 such that if a hypergraph k-Uniform H of order n satisfies ?k-2(H) > ((4(k-l)-1)/(4(k-l)2)+?) (n 2), then H has a Hamiltonian l-cycle.
Dias, Mauricio Araujo. "Um sistema criptografico para curvas elipticas sobre GF(2m) implementado em circuitos programaveis". [s.n.], 2007. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260923.
Pełny tekst źródłaTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-09T13:54:55Z (GMT). No. of bitstreams: 1 Dias_MauricioAraujo_D.pdf: 794928 bytes, checksum: a328a640d35118ea7fb606ac9f4ab2b2 (MD5) Previous issue date: 2007
Resumo: Este trabalho propõe um sistema criptográfico para Criptografia baseada em Curvas Elípticas (ECC). ECC é usada alternativamente a outros sistemas criptográficos, como o algoritmo RSA (Rivest-Shamir-Adleman), por oferecer a menor chave e a maior segurança por bit. Ele realiza multiplicação de pontos (Q = kP) para curvas elípticas sobre corpos finitos binários. Trata-se de um criptosistema programável e configurável. Graças às propriedades do circuito programável (FPGA) é possível encontrar soluções otimizadas para diferentes curvas elípticas, corpos finitos e algoritmos. A característica principal deste criptosistema é o uso de um circuito combinacional para calcular duplicações e adições de pontos, por meio da aritmética sobre corpos finitos. Os resultados deste trabalho mostram que um programa de troca de chaves fica aproximadamente 20.483 vezes mais rápido com a ajuda do nosso sistema criptográfico. Para desenvolver este projeto, nós consideramos que o alto desempenho tem prioridade sobre a área ocupada pelos seus circuitos. Assim, nós recomendamos o uso deste circuito para os casos em que não sejam impostas restrições de área, mas seja exigido alto desempenho do sistema
Abstract: This work proposes a cryptosystem for Elliptic Curve Cryptography (ECC). ECC has been used as an alternative to other public-key cryptosystems such as the RSA (Rivest-Shamir-Adleman algorithm) by offering the smallest key size and the highest strength per bit. The cryptosystem performs point multiplication (Q = kP) for elliptic curves over binary polynomial fields (GF(2m)). This is a programmable and scalable cryptosystem. It uses the abilities of reconfigurable hardware (FPGA) to make possible optimized circuitry solutions for different elliptic curves, finite fields and algorithms. The main feature of this cryptosystem is the use of a combinatorial circuit to calculate point doublings and point additions, through finite field arithmetic. The results of this work show that the execution of a key-exchange program is, approximately, 20,483 times faster with the help of our cryptosystem. To develop this project we considered that high-performance has priority over area occupied by its circuit. Thus, we recommend the use of this circuit in the cases for which no area constraints are imposed but high performance systems are required.
Doutorado
Engenharia de Computação
Doutor em Engenharia Elétrica
Gwellem, Chrys. "Decompositions, Packings, and Coverings of Complete Directed Gaphs with a 3-Circuit and a Pendent Arc". Digital Commons @ East Tennessee State University, 2007. https://dc.etsu.edu/etd/2029.
Pełny tekst źródłaPonnuswami, Ashok Kumar. "Intractability Results for some Computational Problems". Diss., Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24638.
Pełny tekst źródłaRombach, Michaela Puck. "Colouring, centrality and core-periphery structure in graphs". Thesis, University of Oxford, 2013. http://ora.ox.ac.uk/objects/uuid:7326ecc6-a447-474f-a03b-6ec244831ad4.
Pełny tekst źródłaAhmad, Mumtaz. "Stratégies d'optimisation de la mémoire pour le calcul d'applications linéaires et l'indexation de document partagés". Phd thesis, Université Henri Poincaré - Nancy I, 2011. http://tel.archives-ouvertes.fr/tel-00641866.
Pełny tekst źródłaBrassard, Serge. "Méthodologie et modélisation floues des connaissances dans l'activité de conception en électrotechnique : application à la réalisation d'un système expert d'aide à la conception de l'appareillage électrique". Grenoble INPG, 1989. http://www.theses.fr/1989INPG0093.
Pełny tekst źródłahuang, yungyi, i 黃勇益. "A Heuristic Algorithm for Synthesizing Combinatorial QuantumBoolean Circuits". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/12393400231914102397.
Pełny tekst źródła國立中興大學
電機工程學系
93
For a quantum computer, the synthesis of quantum Boolean circuits is an essential aim. In addition, it seems that constructing a circuit with an n-bit Toffoli gatewith n 3 is neither practical nor economical. In this paper, we introduce a heuristic algorithm for synthesizing any combinational quantum Boolean circuit with a gate library containing only Not, CNot and Toffoli gates. Our algorithm mainly adopts the primary linking rule and secondary linking rule to simplify a circuit. Moreover, we propose a method for selecting a path with lower cost during the simplification process. Finally, we propose another method, which analyzes the simplified circuit and finds out common terms, to further reduce the circuit cost. In the context, we employ some examples, in company with the Karnaugh map presentation, to explain our algorithm.
Han, Benjamin, i 韓定中. "Diagnosis of Combinatorial Digital Circuits from First Principles". Thesis, 1996. http://ndltd.ncl.edu.tw/handle/33163737562788836207.
Pełny tekst źródła國立中山大學
電機工程研究所
84
The diagnostic problem arises when the observed behavior of a system deviates from the expectation. Assuming that the design of the system is correct in the sense that it is con- sistent with its specification, a diagnosis is a hypothesis of faults within the system under the observations obtained so far which can explain the discrepancies between the expected and the actual behavior of the system. The reason to perform diag- nosis is that by replacing only the faulty components of a mal- functioning system, one can repair the system instead of re- placing it, and the former solution is usually more economical and practical. In this thesis we focus on model-based diagnosis, in par- ticular, the theory of diagnosis from first principles. We augment and clarify Hou's theory of measurement with supplementary proofs, and revise the incomplete method for minimal conflict set derivation with a complete, efficient and proved derivation approach using a CS-tree (conflict set tree) with mark set. A measurement selection strategy using the ge- netic algorithm (MSSGA) is proposed to select the best next mea- surement in a diagnostic process, and the results of a series of experiments show that this approach is promising. Finally a complete diagnostic system for combinatorial digital circuits (DSDC) is proposed and implemented. DSDC receives a circuit specification in DSDC Language (DSDCL), and automatically locates the culprits within the circuit. In addition, it is capable of improving its performance online by incorporating MSSGA as its measurement selection strategy.
Cox, Robert Sidney III. "Transcriptional Regulation and Combinatorial Genetic Logic in Synthetic Bacterial Circuits". Thesis, 2008. https://thesis.library.caltech.edu/871/1/cox_thesis_final_cover.pdf.
Pełny tekst źródłaWe engineered several synthetic regulatory circuits to study transcriptional regulation in bacteria. We developed a new technique for DNA construction, built and characterized in vivo a library of genetic logic gates, examined the role of genetic noise transcriptional regulation using a fluorescent multi-reporter system, and characterized a synthetic circuit for the control of population density.
We used synthetic duplex DNA fragments and very short cohesive overhangs to direct ordered assemblies of diverse combinatorial libraries. Multiple DNA fragments were simultaneously ligated in a single step to produce random concatemers, without the need for amplification or product purification. We characterized the assembly process to identify optimal cohesive overhangs. We showed that the method was 97% efficient for assembling 100 base-pair concatemers from three duplex fragments.
We constructed a library of 10,000 prokaryotic promoters, containing over 1,000 unique 100 base-pair sequences. These promoters responded to up to three inputs, and contained diverse architectural arrangements of regulatory sequences. We characterized the logical input functions of 288 promoters in Escherichia coli, and analyzed the relationship between promoter function and architecture. We defined promoter function in terms of regulatory range, logic type, and input symmetry; and identified general rules for combinatorial programming of gene expression.
We built a synthetic three-color fluorescent reporter framework. This construct was non-toxic and extensible for synthetic and systems biology applications. Three spectrally distinct and genetically isolated reporter proteins allowed independent monitoring of genetic signals at the single-cell level. We showed that the simultaneous measurement of multiple genes can exploit genetic noise to sensitively detect transcriptional co-regulation.