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Artykuły w czasopismach na temat "Combinatorial circuits"
Tsuiki, Shigeya, i Takahiro Haga. "AND-inverse detecting circuit for the combinatorial logic circuits". Electronics and Communications in Japan (Part III: Fundamental Electronic Science) 73, nr 11 (1990): 51–60. http://dx.doi.org/10.1002/ecjc.4430731106.
Pełny tekst źródłaMatsushima, Ayano, i Ann M. Graybiel. "Combinatorial Developmental Controls on Striatonigral Circuits". Cell Reports 38, nr 2 (styczeń 2022): 110272. http://dx.doi.org/10.1016/j.celrep.2021.110272.
Pełny tekst źródłaMatsushima, Ayano, i Ann M. Graybiel. "Combinatorial Developmental Controls on Striatonigral Circuits". Cell Reports 31, nr 11 (czerwiec 2020): 107778. http://dx.doi.org/10.1016/j.celrep.2020.107778.
Pełny tekst źródłaDonovan, Zola, Gregory Gutin, Vahan Mkrtchyan i K. Subramani. "Clustering without replication in combinatorial circuits". Journal of Combinatorial Optimization 38, nr 2 (21.02.2019): 481–501. http://dx.doi.org/10.1007/s10878-019-00394-1.
Pełny tekst źródłaFang, K. Y., i A. S. Wojcik. "Modular decomposition of combinatorial multiple-values circuits". IEEE Transactions on Computers 37, nr 10 (1988): 1293–301. http://dx.doi.org/10.1109/12.5993.
Pełny tekst źródłaChen, Ethan, i Vanessa Chen. "Statistical RF/Analog Integrated Circuit Design Using Combinatorial Randomness for Hardware Security Applications". Mathematics 8, nr 5 (20.05.2020): 829. http://dx.doi.org/10.3390/math8050829.
Pełny tekst źródłaURAHAMA, KIICHI, i SHIN-ICHIRO UENO. "A GRADIENT SYSTEM SOLUTION TO POTTS MEAN FIELD EQUATIONS AND ITS ELECTRONIC IMPLEMENTATION". International Journal of Neural Systems 04, nr 01 (marzec 1993): 27–34. http://dx.doi.org/10.1142/s0129065793000043.
Pełny tekst źródłaWróblewski, Artur, Christian V. Schimpfle, Otto Schumacher i Josef A. Nossek. "Minimizing Spurious Switching Activities with Transistor Sizing". VLSI Design 15, nr 2 (1.01.2002): 537–45. http://dx.doi.org/10.1080/1065514021000012156.
Pełny tekst źródłaZhu, Enqiang, Congzhou Chen, Yongsheng Rao i Weicheng Xiong. "Biochemical Logic Circuits Based on DNA Combinatorial Displacement". IEEE Access 8 (2020): 34096–103. http://dx.doi.org/10.1109/access.2020.2974024.
Pełny tekst źródłaFujiwara, Yuichiro, i Charles J. Colbourn. "A Combinatorial Approach to X-Tolerant Compaction Circuits". IEEE Transactions on Information Theory 56, nr 7 (lipiec 2010): 3196–206. http://dx.doi.org/10.1109/tit.2010.2048468.
Pełny tekst źródłaRozprawy doktorskie na temat "Combinatorial circuits"
Agnihotri, Ameya Ramesh. "Combinatorial optimization techniques for VLSI placement". Diss., Online access via UMI:, 2007.
Znajdź pełny tekst źródłaCox, Robert Sidney Sternberg Paul W. Sternberg Paul W. "Transcriptional regulation and combinatorial genetic logic in synthetic bacterial circuits /". Diss., Pasadena, Calif. : California Institute of Technology, 2008. http://resolver.caltech.edu/CaltechETD:etd-03042008-130011.
Pełny tekst źródłaRinderknecht, William John. "A power reduction algorithm for combinatorial CMOS circuits using input disabling". Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/36543.
Pełny tekst źródłaIncludes bibliographical references (p. 61-62).
by William John Rinderknecht.
M.S.
Hacker, Charles Hilton, i n/a. "WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design". Griffith University. School of Engineering, 2001. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20050915.172404.
Pełny tekst źródłaHacker, Charles. "WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design". Thesis, Griffith University, 2001. http://hdl.handle.net/10072/367209.
Pełny tekst źródłaThesis (Masters)
Master of Philosophy (MPhil)
School of Engineering
Science, Environment, Engineering and Technology
Full Text
Coward, Bob. "Genroute : a genetic algorithm (printed wire board (PWB) router) /". Online version of thesis, 1991. http://hdl.handle.net/1850/10711.
Pełny tekst źródłaDuran, Arqué Berta. "Combinatorial perspective on the gene expression circuits established by the CPEB-family of RNA binding proteins". Doctoral thesis, Universitat de Barcelona, 2020. http://hdl.handle.net/10803/673591.
Pełny tekst źródłaLa maduración meiótica y la embriogénesis temprana de Xenopus se dan en ausencia de transcripción. Hasta la transición materno-cigótica – después de la 12ª división embrionaria - la transcripción no se re-inicia y todos los cambios en expresión génica ocurren por mecanismos post- transcripcionales, entre los cuales destaca la poliadenilación citoplasmática. Durante su crecimiento, el oocito produce grandes cantidades de mRNA que mantiene silenciados, con una cola de poly(A) corta. En la maduración y embriogénesis, ciertos mRNAs son poliadenilados y traducidos. Cuando y cuanto cada mRNA es movilizado depende de la combinación de señales presentes en su 3’UTR y de las proteínas de unión al RNA que las reconocen. En la maduración meiótica se dan, al menos, tres olas secuenciales de poliadenilación. La primera es iniciada en respuesta a progesterona. Concretamente, la fosforilación por Aurora quinasa A causa la remodelación del complejo de represión de CPEB1 a complejo de activación, permitiendo la expresión de genes necesarios para la progresión meiótica, como Cdk1. Seguidamente, Cdk1 participa en la degradación de CPEB1 generando una segunda ola que es necesaria para la interkinesis. Por último, CPEB4, producida en la primera ola de poliadenilación y activada por fosforilación por Cdk1 abandera una tercera ola que posibilita la expresión de proteínas que mantienen el arresto en metafase-II. A diferencia de sus homólogos CPEB1 y CPEB4, los papeles de CPEB2 y CPEB3 en maduración meiótica siguen sin caracterizar. Por ello y para entender como esta familia de proteínas de unión al RNA se coordina para dictar la expresión génica hemos realizado una investigación sistemática y comparativa de las CPEBs en maduración meiótica.
Goulart, Sobrinho Edilton Furquim [UNESP]. "Uma ferramenta alternativa para síntese de circuitos lógicos usando a técnica de circuito evolutivo". Universidade Estadual Paulista (UNESP), 2007. http://hdl.handle.net/11449/87253.
Pełny tekst źródłaCoordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
Neste trabalho descreve-se uma metodologia para síntese e otimização de circuitos digitais, usando a teoria de algoritmos evolutivos e como plataforma os dispositivos reconfiguráveis, denominada Hardware Evolutivo do inglês- Evolvable Hardware - EHW. O EHW, tornou-se viável com o desenvolvimento em grande escala dos dispositivos reconfiguráveis, Programmable Logic Devices (PLD s), cuja arquitetura e função podem ser determinadas por programação. Cada circuito pode ser representado como um indivíduo em um processo evolucionário, evoluindo-o através de operações genéticas para um resultado desejado. Como algoritmo evolutivo, aplicou-se o Algoritmo Genético (AG), uma das técnicas da computação evolutiva que utiliza os conceitos da genética e seleção natural. O processo de síntese aplicado neste trabalho, inicia por uma descrição do comportamento do circuito, através de uma tabela verdade para circuitos combinacionais e a tabela de estados para os circuitos seqüenciais. A técnica aplicada busca o arranjo correto e minimizado do circuito que desempenhe uma função proposta. Com base nesta metodologia, são implementados alguns exemplos em duas diferentes representações (mapas de fusíveis e matriz de portas lógicas).
In this work was described a methodology for optimization and synthesis of digital circuits, which consist of evolving circuits through evolvable algorithms using as platforms reconfigurable devices, denominated Evolvable Hardware (EHW). It was became viable with the large scale development of reconfigurable devices, whose architecture and function can be determined by programming. Each circuit can be represented as an individual within an evolutionary process, evolving through genetic operations to desire results. Genetic Algorithm (GA) was applied as evolutionary algorithm where this technique evolvable computation as concepts of genetics and natural selection. The synthesis process applied in this work starts from a description from the circuits behavior. Trust table for combinatorial circuits and state transition table for sequential circuits were used for synthesis process. This technic applied search the correct arrange and minimized circuit which response the propose function. Based on this methodology, some examples are implemented in two different representations (fuse maps and logic gate matrices).
Nafkha, Amor. "A geometrical approach detector for solving the combinatorial optimisation problem : application in wireless communication systems". Lorient, 2006. http://www.theses.fr/2006LORIS067.
Pełny tekst źródłaThe demand for mobile communication systems with high data rates and improved link quality for a variety of applications has dramatically increased in recent years. New concepts and methods are necessary in order to cover this huge demand, which counteract or take advantage of the impairments of the mobile communication channel and optimally exploit the limited resources such as bandwidth and power. The problem of finding the least-squares solution to a system of linear equations where the unknown vector is comprised of integers, but the matrix coefficients and given vector are comprised of real numbers, arise in many applications: communications, cryptography, MC-CDMA, MIMO, to name a few. The Maximum Likelihood (ML) decoding is equivalent to finding the closest lattice point in an n-dimensional real space. In general, this problem is known to be non deterministic NP hard. In this thesis, a polynomial-time approximation method called Geometrical Intersection and Selection Detector (GISD) is applied to the MLD problem. Moreover, the proposed approach is based on two complementary "real time" operational research methods: intensification and diversification. Our approach has three important characteristics that make it very attractive for for VLSI implementation. First, It will be shown that the performance of GISD receiver is superior as compared to other sub-optimal detection methods and it provides a good approximation to the optimal detector. Second, the inherent parallel structure of the proposed method leads to a very suitable hardware implementation. Finaly, The GISD allows a near optimal performance with constant polynomial-time, O(n3), computational complexity (unlike the sphere decoding that has exponential-time complexity for low SNR). The proposed Detector can be efficiently employed in most wireless communications systems: MIMO, MC-CDMA, MIMO-CDMA etc. .
Goulart, Sobrinho Edilton Furquim. "Uma ferramenta alternativa para síntese de circuitos lógicos usando a técnica de circuito evolutivo /". Ilha Solteira : [s.n.], 2007. http://hdl.handle.net/11449/87253.
Pełny tekst źródłaBanca: José Raimundo de Oliveira
Banca: Nobuo Oki
Resumo: Neste trabalho descreve-se uma metodologia para síntese e otimização de circuitos digitais, usando a teoria de algoritmos evolutivos e como plataforma os dispositivos reconfiguráveis, denominada Hardware Evolutivo do inglês- Evolvable Hardware - EHW. O EHW, tornou-se viável com o desenvolvimento em grande escala dos dispositivos reconfiguráveis, Programmable Logic Devices (PLDs), cuja arquitetura e função podem ser determinadas por programação. Cada circuito pode ser representado como um indivíduo em um processo evolucionário, evoluindo-o através de operações genéticas para um resultado desejado. Como algoritmo evolutivo, aplicou-se o Algoritmo Genético (AG), uma das técnicas da computação evolutiva que utiliza os conceitos da genética e seleção natural. O processo de síntese aplicado neste trabalho, inicia por uma descrição do comportamento do circuito, através de uma tabela verdade para circuitos combinacionais e a tabela de estados para os circuitos seqüenciais. A técnica aplicada busca o arranjo correto e minimizado do circuito que desempenhe uma função proposta. Com base nesta metodologia, são implementados alguns exemplos em duas diferentes representações (mapas de fusíveis e matriz de portas lógicas).
Abstract: In this work was described a methodology for optimization and synthesis of digital circuits, which consist of evolving circuits through evolvable algorithms using as platforms reconfigurable devices, denominated Evolvable Hardware (EHW). It was became viable with the large scale development of reconfigurable devices, whose architecture and function can be determined by programming. Each circuit can be represented as an individual within an evolutionary process, evolving through genetic operations to desire results. Genetic Algorithm (GA) was applied as evolutionary algorithm where this technique evolvable computation as concepts of genetics and natural selection. The synthesis process applied in this work starts from a description from the circuits behavior. Trust table for combinatorial circuits and state transition table for sequential circuits were used for synthesis process. This technic applied search the correct arrange and minimized circuit which response the propose function. Based on this methodology, some examples are implemented in two different representations (fuse maps and logic gate matrices).
Mestre
Książki na temat "Combinatorial circuits"
Lengauer, T. Combinatorial algorithms for integrated circuit layout. Stuttgart: B.G. Teubner, 1990.
Znajdź pełny tekst źródłaLengauer, Thomas. Combinatorial algorithms for integrated circuit layout. Chichester: Wiley, 1990.
Znajdź pełny tekst źródłaEngineering genetic circuits. Boca Raton: Chapman & Hall/CRC, 2010.
Znajdź pełny tekst źródłaLengauer, Thomas. Combinatorial Algorithms for Integrated Circuit Layout. Wiesbaden: Vieweg+Teubner Verlag, 1990. http://dx.doi.org/10.1007/978-3-322-92106-2.
Pełny tekst źródłaLengauer, T. Combinatorial Algorithms for Integrated Circuit Layout. Wiesbaden: Vieweg+Teubner Verlag, 1992.
Znajdź pełny tekst źródłaInternational Conference on Microreaction Technology (1st 1997). Microreaction technology: Proceedings of the First International Conference on Microreaction Technology. Berlin: Springer, 1998.
Znajdź pełny tekst źródłaBraun, Jaromír. Kombinatorické metody v analýze a modelování elektronických soustav. Praha: Academia, 1990.
Znajdź pełny tekst źródłaBarg, Alexander, i O. R. Musin. Discrete geometry and algebraic combinatorics. Providence, Rhode Island: American Mathematical Society, 2014.
Znajdź pełny tekst źródłaMyasnikov, Alexei G. Non-commutative cryptography and complexity of group-theoretic problems. Providence, R.I: American Mathematical Society, 2011.
Znajdź pełny tekst źródłaMorse, Robert Fitzgerald, editor of compilation, Nikolova-Popova, Daniela, 1952- editor of compilation i Witherspoon, Sarah J., 1966- editor of compilation, red. Group theory, combinatorics and computing: International Conference in honor of Daniela Nikolova-Popova's 60th birthday on Group Theory, Combinatorics and Computing, October 3-8, 2012, Florida Atlantic University, Boca Raton, Florida. Providence, Rhode Island: American Mathematical Society, 2013.
Znajdź pełny tekst źródłaCzęści książek na temat "Combinatorial circuits"
Tietze, Ulrich, Christoph Schenk i Eberhard Gamm. "Combinatorial Circuits". W Electronic Circuits, 635–58. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-78655-9_8.
Pełny tekst źródłaAdam, Hans-Joachim, i Mathias Adam. "Combinatorial Circuits with PLC". W PLC Programming In Instruction List According To IEC 61131-3, 69–87. Berlin, Heidelberg: Springer Berlin Heidelberg, 2022. http://dx.doi.org/10.1007/978-3-662-65254-1_5.
Pełny tekst źródłaDonovan, Zola, K. Subramani i Vahan Mkrtchyan. "Disjoint Clustering in Combinatorial Circuits". W Lecture Notes in Computer Science, 201–13. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-25005-8_17.
Pełny tekst źródłaGroote, Jan Friso, Rolf Morel, Julien Schmaltz i Adam Watkins. "Basic components and combinatorial circuits". W Logic Gates, Circuits, Processors, Compilers and Computers, 1–22. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-68553-9_1.
Pełny tekst źródłaMankowski, Michal, i Mikhail Moshkov. "Circuits and Cost Functions". W Dynamic Programming Multi-Objective Combinatorial Optimization, 17–27. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-63920-4_2.
Pełny tekst źródłaDonovan, Zola, Vahan Mkrtchyan i K. Subramani. "On Clustering Without Replication in Combinatorial Circuits". W Combinatorial Optimization and Applications, 334–47. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-26626-8_25.
Pełny tekst źródłaEllis, Samuel J., Titus H. Klinge i James I. Lathrop. "Robust Combinatorial Circuits in Chemical Reaction Networks". W Theory and Practice of Natural Computing, 178–89. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-71069-3_14.
Pełny tekst źródłaHoory, Shlomo, Avner Magen i Toniann Pitassi. "Monotone Circuits for the Majority Function". W Approximation, Randomization, and Combinatorial Optimization. Algorithms and Techniques, 410–25. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11830924_38.
Pełny tekst źródłaGupta, Meenakshi, Vikram Kumar Kamboj i R. K. Sharma. "A novel hybrid GWO-PS based solution approach for combinatorial unit commitment problem". W Intelligent Circuits and Systems, 417–24. London: CRC Press, 2021. http://dx.doi.org/10.1201/9781003129103-65.
Pełny tekst źródłaKlivans, Adam R. "On the Derandomization of Constant Depth Circuits". W Approximation, Randomization, and Combinatorial Optimization: Algorithms and Techniques, 249–60. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-44666-4_28.
Pełny tekst źródłaStreszczenia konferencji na temat "Combinatorial circuits"
Wirth, Gilson I., Michele G. Vieira, Egas Henes Neto i F. G. L. Kastensmidt. "Single event transients in combinatorial circuits". W the 18th annual symposium. New York, New York, USA: ACM Press, 2005. http://dx.doi.org/10.1145/1081081.1081115.
Pełny tekst źródłaWirth, Gilson I., Michele G. Vieira, Egas Henes Neto i F. G. L. Kastensmidt. "Single Event Transients in Combinatorial Circuits". W 2005 18th Symposium on Integrated Circuits and Systems Design. IEEE, 2005. http://dx.doi.org/10.1109/sbcci.2005.4286843.
Pełny tekst źródłaKiselyov, Oleg, Kedar N. Swadi i Walid Taha. "A methodology for generating verified combinatorial circuits". W the fourth ACM international conference. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/1017753.1017794.
Pełny tekst źródłaSerlet, B. P. "Fast, small, and static combinatorial CMOS circuits". W 24th ACM/IEEE conference proceedings. New York, New York, USA: ACM Press, 1987. http://dx.doi.org/10.1145/37888.37955.
Pełny tekst źródłaStrukov, Dmitri. "Solving Combinatorial Optimization Problems with Nanoelectronic Neuromorphic Circuits". W Neuromorphic Materials, Devices, Circuits and Systems. València: FUNDACIO DE LA COMUNITAT VALENCIANA SCITO, 2023. http://dx.doi.org/10.29363/nanoge.neumatdecas.2023.006.
Pełny tekst źródłaOraon, Neha, i Madhav Rao. "Delay approximation for nanomagnetic logic based combinatorial circuits". W 2019 IEEE 14th International Conference on Nano/Micro Engineered and Molecular Systems (NEMS). IEEE, 2019. http://dx.doi.org/10.1109/nems.2019.8915607.
Pełny tekst źródłaSrivastava, Atul K., i Hariom Gupta. "Cluster growth technique for combinatorial evolvable digital circuits". W 2014 Seventh International Conference on Contemporary Computing (IC3). IEEE, 2014. http://dx.doi.org/10.1109/ic3.2014.6897189.
Pełny tekst źródłaGuindi, R. S. "Gate-leakage estimation and minimization in CMOS combinatorial circuits". W Proceedings of the 15th International Conference on Microelectronics. IEEE, 2003. http://dx.doi.org/10.1109/icm.2003.238361.
Pełny tekst źródłaKechichian, Al-Khalili i Al-Khalili. "Optimizing CMOS combinatorial circuits using multiple attribute decision making techniques". W Proceedings of Canadian Conference on Electrical and Computer Engineering CCECE-94. IEEE, 1994. http://dx.doi.org/10.1109/ccece.1994.405810.
Pełny tekst źródłaKitamichi, J., H. Kageyama i N. Funabiki. "Formal verification method for combinatorial circuits at high level design". W Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198). IEEE, 1999. http://dx.doi.org/10.1109/aspdac.1999.760023.
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