Artykuły w czasopismach: „CMOS VOLTAGE FOLLOWER”

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Tanno, K., H. Matsumoto, O. Ishizuka i Zheng Tang. "Simple CMOS voltage follower with resistive-load drivability". IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 46, nr 2 (1999): 172–77. http://dx.doi.org/10.1109/82.752947.

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Kasemsuwan, Varakorn, i Weerachai Nakhlo. "A simple rail‐to‐rail CMOS voltage follower". Microelectronics International 26, nr 1 (23.01.2009): 17–21. http://dx.doi.org/10.1108/13565360910923124.

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Ramírez-Angulo, Jaime, Anindita Paul, Manaswini Gangineni, Jose Maria Hinojo-Montero i Jesús Huerta-Chua. "Class AB Voltage Follower and Low-Voltage Current Mirror with Very High Figures of Merit Based on the Flipped Voltage Follower". Journal of Low Power Electronics and Applications 13, nr 2 (24.04.2023): 28. http://dx.doi.org/10.3390/jlpea13020028.

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The application of the flipped voltage follower to implement two high-performance circuits is presented: (1) The first is a class AB cascode flipped voltage follower that shows an improved slew rate and an improved bandwidth by very large factors and that has a higher output range than the conventional flipped voltage follower. It has a small signal figure of merit FOMSS = 46 MHz pF/µW and a current efficiency figure of merit FOMCE = 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 GΩ output resistance, 1 V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary amplifiers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180 nm CMOS (Complementary Metal Oxide Semiconductor) technology.

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Thanapitak, Surachoke, Prajuab Pawarangkoon i Chutham Sawigun. "A Flipped Voltage Follower Second-Order Bandpass Filter". Journal of Circuits, Systems and Computers 26, nr 07 (17.03.2017): 1750112. http://dx.doi.org/10.1142/s0218126617501122.

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This paper presents a compact second-order bandpass filter developed by combining the well-known flipped voltage follower circuit as a transconductance network with two capacitors. Operated in the subthreshold region, the filter’s center frequency can be adjusted linearly by varying the bias current. Post-layout simulation using a 0.35-[Formula: see text]m CMOS process confirms the suitability of the proposed filter in low-voltage, low-power environment.

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Ocampo-Hidalgo, J. J., J. Alducín-Castillo, I. Vázquez-Álvarez, L. N. Oliva-Moreno i J. E. Molinar-Solís. "A CMOS Low-Voltage Super Follower Using Quasi-Floating Gate Techniques". Journal of Circuits, Systems and Computers 27, nr 07 (26.03.2018): 1850111. http://dx.doi.org/10.1142/s0218126618501116.

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A quasi-floating gate (QFG) “super-follower” is presented. The high resistance used by the QFG transistor is constructed by two diodes connected back-to-back, leading to a simple-, temperature-stable- and small-area solution. Expressions for the behavior of the follower are introduced and verified by circuit simulations in LTSPICE using 0.5[Formula: see text][Formula: see text]m CMOS process models, which show an improved performance of the proposed circuit with respect to the original super-follower. To prove the principle, a test cell was fabricated in the same 0.5[Formula: see text][Formula: see text]m CMOS technology and characterized. Measurement results show a gain-bandwidth product of 10[Formula: see text]MHz and power consumption of 120[Formula: see text][Formula: see text]W with a 1.5[Formula: see text]V single supply.

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Rajesh, Durgam, Subramanian Tamil, Nikhil Raj i Bharti Chourasia. "Low-voltage bulk-driven flipped voltage follower-based transconductance amplifier". Bulletin of Electrical Engineering and Informatics 11, nr 2 (1.04.2022): 765–71. http://dx.doi.org/10.11591/eei.v11i2.3306.

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A low voltage high performance design of operational transconductance amplifier is proposed in this paper. The proposed architecture is based on bulk driven quasi-floating gate metal oxide semiconductor field effect transistor (MOSFET) which supports low voltage operation and improves the gain of the amplifier. Besides to this the tail current source requirement of operational transconductance amplifier (OTA) is removed by using the flipped voltage follower structure at the input pair along with bulk driven quasi-floating gate MOSFET. The proposed operational transconductance amplifier shows a five-fold increase in direct current (DC) gain and 3-fold increase in unity gain bandwidth when compared with its conventional bulk driven architecture. The metal oxide semiconductor (MOS) model used for amplifier design is of 0.18 um complementary metal oxide semiconductor (CMOS) technology at supply of 0.5 V.

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SAKUL, CHAIWAT, i KOBCHAI DEJHAN. "FLIPPED VOLTAGE FOLLOWER ANALOG NONLINEAR CIRCUITS". Journal of Circuits, Systems and Computers 21, nr 03 (maj 2012): 1250024. http://dx.doi.org/10.1142/s0218126612500247.

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This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.

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Ocampo-Hidalgo, Juan Jesus, Iván Vázquez-Álvarez, Sergio Sandoval-Perez, Rodolfo Garcia-Lozano, Marco Gurrola-Navarro i Jesus Ezequiel Molinar-Solis. "A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique". Ingeniería e Investigación 37, nr 2 (1.05.2017): 82–88. http://dx.doi.org/10.15446/ing.investig.v37n2.62625.

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This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the “Flipped” Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 μm CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 μW. Measurement and experimental results show a gain bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz.

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Tripathi, S. K., Mohd Samar Ansari i Amit M. Joshi. "Carbon Nanotubes-Based Digitally Programmable Current Follower". VLSI Design 2018 (17.01.2018): 1–10. http://dx.doi.org/10.1155/2018/1080817.

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The physical constraints of ever-shrinking CMOS transistors are rapidly approaching atomistic and quantum mechanical limits. Therefore, research is now directed towards the development of nanoscale devices that could work efficiently in the sub-10 nm regime. This coupled with the fact that recent design trend for analog signal processing applications is moving towards current-mode circuits which offer lower voltage swings, higher bandwidth, and better signal linearity is the motivation for this work. A digitally controlled DVCC has been realized using CNFETs. This work exploited the CNFET’s parameters like chirality, pitch, and numbers of CNTs to perform the digital control operation. The circuit has minimum number of transistors and can control the output current digitally. A similar CMOS circuit with 32 nm CMOS parameters was also simulated and compared. The result shows that CMOS-based circuit requires 418.6 μW while CNFET-based circuit consumes 352.1 μW only. Further, the proposed circuit is used to realize a CNFET-based instrumentation amplifier with digitally programmable gain. The amplifier has a CMRR of 100 dB and ICMR equal to 0.806 V. The 3 dB bandwidth of the amplifier is 11.78 GHz which is suitable for the applications like navigation, radar instrumentation, and high-frequency signal amplification and conditioning.

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Ajayan, K. R., i Navakanta Bhat. "Linear transconductor with flipped voltage follower in 130 nm CMOS". Analog Integrated Circuits and Signal Processing 63, nr 2 (13.10.2009): 321–27. http://dx.doi.org/10.1007/s10470-009-9396-5.

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Yang, Yintang, Liang Zhang, Zhangming Zhu i Ruixue Ding. "A low-distortion CMOS analogue voltage follower for high-speed ADCs". Microelectronics Journal 54 (sierpień 2016): 67–71. http://dx.doi.org/10.1016/j.mejo.2016.05.011.

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Elwan, H. O., i M. Ismail. "Digitally controlled CMOS current follower for low voltage low power applications". Electronics Letters 34, nr 24 (1998): 2297. http://dx.doi.org/10.1049/el:19981591.

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de la Cruz-Alejo, Jesús, i L. Noe Oliva-Moreno. "Low Voltage FGMOS Four Quadrants Analog Multiplier". Advanced Materials Research 918 (kwiecień 2014): 313–18. http://dx.doi.org/10.4028/www.scientific.net/amr.918.313.

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In this paper a low voltage FGMOS analog multiplier is proposed that uses a follower voltage flipped (FVF), which dominates its operation. In order to reduce the power supply of the multiplier, floating gate CMOS transistors (FGMOS) are used. Theoretical steps of the FVF design are presented together with its simulation. The output of the FVF is insensitive to the device parameters and is loaded with a resistive load. The multiplier design consists of two FVF cells, two current sensors FVF and one Gilbert cell multiplier. The results show that the proposed multiplied in a 0.13μm CMOS process exhibits significant benefits in terms of linearity, insensibility to device parameters, bandwidth and output impedance. The power supply is 0.8V and a power consumption of 181μW.

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ARSLAN, EMRE, SHAHRAM MINAEI i AVNI MORGUL. "ON THE REALIZATION OF HIGH PERFORMANCE CURRENT CONVEYORS AND THEIR APPLICATIONS". Journal of Circuits, Systems and Computers 22, nr 03 (marzec 2013): 1350015. http://dx.doi.org/10.1142/s0218126613500151.

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In this work, a wideband and high-performance CMOS implementation of 2nd-generation current conveyor (CCII) is proposed. The proposed circuit is composed of a high performance voltage follower stage which is based on differential pairs to provide high voltage swings on input and output ports and a current follower stage. It is shown that the proposed voltage follower stage can be used to implement high performance 1st and 3rd-generation current conveyors (CCI and CCIII, respectively) that have very small equivalent impedances on ports X, high equivalent impedances on ports Y and Z and also high-valued voltage and current transfer bandwidths. 2nd and 3rd order filter circuits as well as a half-wave rectifier circuit are given to show the performance and usefulness of the proposed current conveyor circuits. The simulation and experimental results are given to verify the theoretical analyses.

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Achigui, Hugues J., Christian Fayomi, Daniel Massicotte i Mounir Boukadoum. "Low-voltage, high-speed CMOS analog latched voltage comparator using the “flipped voltage follower” as input stage". Microelectronics Journal 42, nr 5 (maj 2011): 785–89. http://dx.doi.org/10.1016/j.mejo.2011.01.006.

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Lu, Yange, Ming Chen, Kunyu Wang, Yanjun Yang i Haiyong Wang. "A Capacitorless Flipped Voltage Follower LDO with Fast Transient Using Dynamic Bias". Electronics 11, nr 19 (22.09.2022): 3009. http://dx.doi.org/10.3390/electronics11193009.

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The output capacitorless low-dropout regulator (OCL-LDO) has developed rapidly in recent years. This paper presents a flipped voltage follower (FVF) OCL-LDO with fast transient response. By adding a dynamic bias circuit to the FVF circuit, the proposed LDO has the ability to quickly adjust the gate voltage of the power transistor, without extra power consumption. The proposed LDO was designed in 0.18 μm CMOS process. The simulation results show that the recovery time is 52 ns when the load changes from 0.1 mA to 20 mA with a slew rate of 20 mA/ps, while the quiescent current is 92 μA with 1 V regulated output. The undershoot and overshoot voltage are 242 mV and 250 mV, respectively.

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Yesil, Abdullah, Shahram Minaei i Costas Psychalinos. "± 0.45 V CMOS Second-Generation Voltage Conveyor Based on Super Source Follower". Circuits, Systems, and Signal Processing 41, nr 4 (23.10.2021): 1819–33. http://dx.doi.org/10.1007/s00034-021-01867-7.

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Bui, Tuan A., Geoffrey K. Reeves, Patrick W. Leech, Anthony S. Holland i Geoffrey Taylor. "TCAD simulation of a single Monolithic Active Pixel Sensors based on High Voltage CMOS technology". MRS Advances 3, nr 51 (2018): 3053–59. http://dx.doi.org/10.1557/adv.2018.417.

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ABSTRACTA model of a High Voltage CMOS (HV-CMOS) Monolithic Active Pixel Sensor (MAPS) has been modelled using Technology Computer Aided Design (TCAD). The model has incorporated both the active region and the on-pixel readout circuits which were comprised of a source follower amplifier and an integrated charge amplifier. The simulation has examined the electrical characteristics and response output of a HV-CMOS MAPS sensor using typical dimensions, levels of doping in the structural layers and bias conditions for this sensor. The performance of two alternate designs of amplifier have been examined as a function of the operating parameters. The response of the sensor to the incidence of Minimum Ionizing Particles (MIPs) at different energies has been included in the model.

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Bae, Seung Yong, Jong Do Lee, Eun Ju Choe i Gil Cho Ahn. "Low Distortion Analog Front-End for Digital Electret Microphone". Applied Mechanics and Materials 475-476 (grudzień 2013): 1633–37. http://dx.doi.org/10.4028/www.scientific.net/amm.475-476.1633.

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This paper presents a low distortion analog front-end (AFE) circuit to process electret microphone output signal. A source follower is employed for the input buffer to interface electret microphone directly to the IC with level shifting. A single-ended to differential converter with output common-mode control is presented to compensate the common-mode variation resulted from gate to source voltage variation in the source follower. A replica stage is adopted to control the output bias voltage of the single-ended to differential converter. The prototype AFE circuit fabricated in a 0.35μm CMOS technology achieves 68.2dB peak SNDR and 79.9dB SFDR over an audio signal bandwidth of 20kHz with 2.5V supply while consuming 1.05mW.

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Caffey i Rishikesh Pandey. "High Performance CMOS Current Mirror Using Class-AB Level Shifted Bulk Driven Flipped Voltage Follower Cell". Journal of Circuits, Systems and Computers 28, nr 08 (lipiec 2019): 1950140. http://dx.doi.org/10.1142/s0218126619501408.

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This paper presents a novel current mirror structure based on level shifted class-AB flipped voltage follower cell, which operates at the supply voltage of 1.2[Formula: see text]V. The level shifted class-AB flipped voltage follower cell and regulated cascode structure are used at the input and the output stages to achieve low input resistance and very high output resistance, respectively. A comparison of performance parameters of the proposed current mirror with existing structures shows that the proposed current mirror has a very less current tracking error of 0.99%, high output resistance of 18.7[Formula: see text]M[Formula: see text], wide bandwidth of 239.245[Formula: see text]MHz and low power dissipation of 104[Formula: see text][Formula: see text]W. The proposed circuit has been simulated in Cadence virtuoso analog design environment and layout of the proposed circuit has been designed in Cadence virtuoso layout XL editor using BSIM3V3 180[Formula: see text]nm CMOS technology. The post-layout simulation results have also been presented to demonstrate the effectiveness of the proposed circuit.

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Kadlcik, Libor, i Pavel Horsky. "A CMOS Follower-Type Voltage Regulator With a Distributed-Element Fractional-Order Control". IEEE Transactions on Circuits and Systems I: Regular Papers 65, nr 9 (wrzesień 2018): 2753–63. http://dx.doi.org/10.1109/tcsi.2018.2808879.

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Lee, Jun-Hee, Mun-Kyo Lee i Jung-Dong Park. "A Direct Feedback FVF LDO for High Precision FMCW Radar Sensors in 65-nm CMOS Technology". Sensors 22, nr 24 (10.12.2022): 9672. http://dx.doi.org/10.3390/s22249672.

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A direct feedback flipped voltage follower (FVF) LDO for a high-precision frequency-modulated continuous-wave (FMCW) radar is presented. To minimize the effect of the power supply ripple on the FMCW radar sensor’s resolution, a folded cascode error amplifier (EA) was connected to the outer loop of the FVF to increase the open-loop gain. The direct feedback structure enhances the PSRR while minimizing the power supply ripple path and not compromising a transient response. The flipped voltage follower with a super source follower forms a fast feedback loop. The stability and parameter variation sensitivity of the multi-loop FVF LDO were analyzed through the state matrix decomposition. We implemented the FVF LDO in TSMC 65 nm CMOS technology. The fabricated FVF LDO supplied a maximum load current of 20 mA with a 1.2 V power supply. The proposed FVF LDO achieved a full-spectrum PSR with a low-frequency PSRR of 66 dB, unity-gain bandwidth of 469 MHz, and 20 ns transient settling time with a load current step from 1 mA to 20 mA.

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Gupta, Maneesha, Urvashi Singh i Richa Srivastava. "High-Frequency and Low-Power Output Stages Based on FGMOS Flipped Voltage Follower". ISRN Electronics 2013 (10.02.2013): 1–7. http://dx.doi.org/10.1155/2013/914058.

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Two new high-performance output stages are proposed. These output stages are basically designed by using a flipped voltage follower (FVF). The proposed low-power and low-voltage output stages have utilized the advantages of the FGMOS technology. They are characterized by low-power dissipation, reduced power supply requirement, and larger bandwidth. By using FGMOS-based FVF in place of conventional FVF, the linearity of the output stages has been highly improved. The small-signal analysis of FGMOS-based FVF is done to show the bandwidth enhancement of conventional FVF. The circuits are simulated to demonstrate the effectiveness using SPICE, in TSMC 0.25-micron CMOS device models. The simulation results show that the power supply requirement of the proposed output stages is highly reduced and bandwidths are extremely higher than the conventional circuits.

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POPA, COSMIN. "LOGARITHMICAL CURVATURE-CORRECTED VOLTAGE REFERENCES WITH IMPROVED TEMPERATURE BEHAVIOR". Journal of Circuits, Systems and Computers 18, nr 03 (maj 2009): 519–34. http://dx.doi.org/10.1142/s0218126609005253.

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Two voltage reference circuits will be presented. For the first circuit, the linear compensation of V GS (T) for an MOS transistor in subthreshold region will be realized using an original offset voltage follower block as PTAT voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. A new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier for compensating the logarithmic temperature dependent term from V GS (T). Because of the operation in weak inversion of all MOS transistors, the circuit will have a very small current consumption, making it compatible with low-power low-voltage designs. The simulated temperature coefficient of the reference voltage for V DD = 2.5 V and a temperature range 0 < t < 30° C is 36.5 ppm/K, confirming the theoretical estimations. The variation of the reference voltage with respect to the supply voltage is 1.5 mV/V for 2–4 V. The circuit current consumption is about 1 μA and the minimal supply voltage is 2 V. The main goal of the second proposed voltage reference is to improve the temperature behavior of a previous reported bipolar voltage reference, by replacing the bipolar transistors with MOS transistors working in weak inversion, with the advantage of obtaining the compatibility with CMOS technology. The new proposed curvature-correction technique will be based on the compensation of the nonlinear temperature dependence of the gate-source voltage for a subthreshold operated MOS transistor by a correction current obtained by taking the difference between two gate-source voltages for MOS transistors biased at drain currents with different temperature dependencies. The circuit is implemented in 0.35 μm CMOS technology. The SPICE simulation confirms the theoretical estimated results, reporting a temperature coefficient of 4.23 ppm/K for the commercial temperature range, 0 < t < 70° C and a small supply voltage, V DD = 2.5 V . The variation of the reference voltage with respect to the supply voltage is 0.9 mV/V for 2–4 V.

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Zamora-Mejia, Gregorio, Dario Edwin Gomez-Garcia, Huber Giron-Nieto, Jaime Martinez-Castillo, Luis Armando Moreno-Coria, Jose Miguel Rocha-Perez i Alejandro Diaz-Sanchez. "A 0.18 μm CMOS capacitor-less Low-Drop Out Voltage Regulator Compensated via the Bootstrap Flipped-Voltage Follower". Microelectronics Journal 101 (lipiec 2020): 104809. http://dx.doi.org/10.1016/j.mejo.2020.104809.

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Bansal, Urvashi, Maneesha Gupta i Urvashi Singh. "Frequency compensation of two stage CMOS circuit using negative capacitance and flipped voltage follower". Analog Integrated Circuits and Signal Processing 90, nr 1 (8.09.2016): 175–88. http://dx.doi.org/10.1007/s10470-016-0857-3.

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Lee, Seung-Wook, Seungwon Cha, Dongyoung Jang, Mihye Kim, Haewon Lee, Nakyung Lee, Seonok Kim i in. "A Low-Voltage 0.7 µm Pixel with 6000 e- Full-Well Capacity for a Low-Power CMOS Image Sensor". Electronic Imaging 2021, nr 7 (18.01.2021): 91–1. http://dx.doi.org/10.2352/issn.2470-1173.2021.7.iss-091.

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A low-voltage pixel with 0.7 µm pitch was designed for a low-power CMOS image sensor. By reducing a pixel power supply voltage (Vpix), power consumption for pixel was reduced, but full-well capacity (FWC) was also decreased. However, by lowering the conversion gain (CG) and applying a negative voltage to the ground (NGND) of the pixel, FWC of 6000 e- was achieved without any degradation of both charge transfer lags and backflow noise. In addition, the signal linearity in the reduced analog-to-digital (ADC) range was improved by optimizing the source follower (SF). For dark performances, white spots and dark current worsened by NGND were significantly improved by forcing more negative voltage to the transfer gate (TG) when it was turned off.

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KASEMSUWAN, VARAKORN, i WEERACHAI NAKHLO. "A SIMPLE 1.5 V RAIL-TO-RAIL CMOS CURRENT CONVEYOR". Journal of Circuits, Systems and Computers 16, nr 04 (sierpień 2007): 627–39. http://dx.doi.org/10.1142/s021812660700385x.

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A simple 1.5 V rail-to-rail CMOS current conveyor is presented. The circuit is developed based on a complementary source follower with a common-source output stage. The circuit is designed using a 0.13 μm CMOS technology and HSPICE is used to verify the circuit performance. The current conveyor exhibits low impedance at terminal X (7.2 Ω) and can drive ± 0.6 V to the 300 Ω with the total harmonic distortion of 0.55% at the operating frequency of 3 MHz. The voltage transfer error (between the Y and X terminals) and current transfer error (between the X and Y terminals) are small (-0.2 dB). The power dissipation and bandwidth are 532 μW and over 300 MHz, respectively.

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Noh, Chang-Kyun, Hyun-Yeop Lee, Ho-Jin Kang, Seong-Tae Kim, Ho-Seon Park i Young-Jin Kim. "CMOS Wideband Low-Pass Filter Using Complementary Structured OPAMP for Wideband System Applications". Journal of Electromagnetic Engineering and Science 23, nr 1 (31.01.2023): 27–37. http://dx.doi.org/10.26866/jees.2023.1.r.141.

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In this paper, a CMOS wideband low-pass filter is proposed. In the wide band active filter design, the unit gain frequency (GBW) of OPAMP should be larger than GHz. The GBW of the proposed OPAMP is around 2.3 GHz. Additionally, the OPAMP with a complementary structure in signal and common mode feedback is proposed and has a wide operating voltage range at the input and output. The 1-dB gain compression point (P1dB) at the output is 4.9 dBm. A source follower is employed for driving 50 Ω output impedance without degrading the bandwidth and linearity of the filter. The power consumption is 27 mW from a 1-V supply voltage. The 3 dB bandwidth of the filter ranges from 330 MHz to 660 MHz with 3-bit cap tuning. This work is implemented in a 65-nm CMOS process, with a chip area of 0.18 mm<sup>2</sup>.

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Khaneshan, Tohid Moradi, Mojde Nematzade, Khayrollah Hadidi i Abdollah Khoei. "Analysis and Design of a Precise Voltage Buffer". Journal of Circuits, Systems and Computers 24, nr 04 (4.03.2015): 1550058. http://dx.doi.org/10.1142/s0218126615500589.

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An open loop voltage buffer with an exact unity gain using a positive local feedback technique with a conventional source follower is proposed. Stability of the buffer is determined by evaluating the location of the poles and zeros and its linearity is studied using Volterra series expansion. The proposed buffer is laid out in 0.35-μm standard CMOS technology. Post layout simulations demonstrate that the buffer gain is close to unity with less than 0.2% error. The power consumption is 10 mw from a 3.3 V power supply and the achieved total harmonic distortion is -78 dB for a 10 MHz input frequency. Also Monte-Carlo simulations are carried out to investigate effects of random mismatches on the circuit operation.

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Pankiewicz, B. "Multiple output CMOS current amplifier". Bulletin of the Polish Academy of Sciences Technical Sciences 64, nr 2 (1.06.2016): 301–6. http://dx.doi.org/10.1515/bpasts-2016-0034.

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Abstract In this paper the multiple output current amplifier basic cell is proposed. The triple output current mirror and current follower circuit are described in detail. The cell consists of a split nMOS differential pair and accompanying biasing current sources. It is suitable for low voltage operation and exhibits highly linear DC response. Through cell devices scaling, not only unity, but also any current gains are achievable. As examples, a current amplifier and bandpass biquad section designed in CMOS TSMC 90nm technology are presented. The current amplifier is powered from a 1.2V supply. MOS transistors scaling was chosen to obtain output gains equal to -2, 1 and 2. Simulated real gains are -1.941, 0.966 and 1.932 respectively. The 3dB passband obtained is above 20MHz, while current consumption is independent of input and output currents and is only 7.77μA. The bandpass biquad section utilises the previously presented amplifier, two capacitors and one resistor, and has a Q factor equal to 4 and pole frequency equal to 100 kHz.

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SHAN, WEIWEI, YAN LIANG i DONGMING JIN. "CMOS CIRCUIT DESIGN OF A TAKAGI-SUGENO FUZZY LOGIC CONTROLLER". Journal of Circuits, Systems and Computers 18, nr 04 (czerwiec 2009): 841–56. http://dx.doi.org/10.1142/s0218126609005009.

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This paper presents a low power CMOS analog integrated circuit of a Takagi–Sugeno fuzzy logic controller with voltage/voltage interface, small chip area, relatively high accuracy and medium speed, which is composed of several improved functional blocks. Z-shaped, Gaussian and S-shaped membership function circuits with compact structures are designed, performing well with low power, high speed and small areas. A current minimization circuit is provided with high accuracy and high speed. A follower-aggregation defuzzification block composed of several multipliers for center of gravity (COG) defuzzification is presented without using a division circuit. Based on these blocks, a two-input one-output singleton fuzzy controller with nine rules is designed under a CMOS 0.6 μm standard technology provided by CSMC. HSPICE simulation results show that this controller reaches an accuracy of ±3% with power consumption of only 3.5 mW (at ±2.5 V). The speed of this controller goes up to 0.625M Fuzzy Logic Inference per Second (FLIPS), which is fast enough for real-time control.

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Diaz-Sanchez, Alejandro, Juan Carlos Mateus-Ardila, Gregorio Zamora-Mejia, Alejandra Diaz-Armendariz, Jose Miguel Rocha-Perez i Luis Armando Moreno-Coria. "A four quadrant high-speed CMOS analog multiplier based on the flipped voltage follower cell". AEU - International Journal of Electronics and Communications 130 (luty 2021): 153582. http://dx.doi.org/10.1016/j.aeue.2020.153582.

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Muñiz-Montero, C., L. A. Sánchez-Gaspariano, J. J. Camacho-Escoto, L. A. Villa-Vargas, H. Molina-Lozano i J. E. Molinar-Solís. "A class-AB CMOS differential flipped voltage follower with output driving capability up to 100pF". Microelectronics Journal 44, nr 10 (październik 2013): 930–40. http://dx.doi.org/10.1016/j.mejo.2013.03.002.

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Zamora-Mejía, Gregorio, Jaime Martínez-Castillo, José Miguel Rocha-Pérez i Alejandro Díaz-Sánchez. "A current mode instrumentation amplifier based on the flipped voltage follower in 0.50 µm CMOS". Analog Integrated Circuits and Signal Processing 87, nr 3 (12.04.2016): 389–98. http://dx.doi.org/10.1007/s10470-016-0731-3.

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Li, Shuo, Xiaomeng Zhang i Saiyu Ren. "High Frequency Unity Gain Buffer in 90-nm CMOS Technology". Journal of Circuits, Systems and Computers 25, nr 07 (22.04.2016): 1650071. http://dx.doi.org/10.1142/s0218126616500717.

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A new unity gain buffer architecture is presented for on-chip CMOS mixed signal applications. The proposed two-stage common source active load (CSAL) buffer with source feedback offers improved performance compared to previously published source follower and source-coupled differential-pair-based unity gain buffers. A 90-nm CMOS design ([Formula: see text] equals 1.2[Formula: see text]V) of the buffer has the following performance parameters. With [Formula: see text]/[Formula: see text] of 10 fF/250 fF, [Formula: see text] is 4.4[Formula: see text]GHz, low frequency gain is 0.16[Formula: see text]dB, maximum input range within 2% gain variation is 260[Formula: see text]mV, total harmonic distortion (THD) is [Formula: see text]63.3[Formula: see text]dB, offset error (input offset minus output offset) is 26[Formula: see text]mV, and 1.06[Formula: see text]mW power consumption. The active load, low gain amplifiers eliminate stability issues and any need for compensation capacitors. The architecture facilitates a relatively large input/output voltage swing while keeping transistors operating in the saturation region, making it suitable for submicron technologies with low rail voltages.

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Zhong, Yi, Faming Yang, Wanjun Yin i Qing Liu. "A Time-Interleaved Charge Pump Internal Power Supply Generation Circuit". Journal of Physics: Conference Series 2356, nr 1 (1.10.2022): 012015. http://dx.doi.org/10.1088/1742-6596/2356/1/012015.

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A charge pump internal power supply generation circuit for rail-to-rail operational amplifier is proposed, which combines a non-overlapping clock signal and a time-interleaved boost charge pump to achieve an internal power supply which is higher than the power supply voltage. A voltage follower is used to avoid glitch during time-interleaving switching. The charge pump internal power supply circuit is realized by 0.5μm CMOS process. The simulation results show that the internal power supply circuit of the charge pump can generate an internal power supply signal which is 1.8V higher than the power supply voltage. After applying this internal power supply to the PMOS input folded cascode operational amplifier, the operational amplifier achieves the rail-to-rail input, and the unity gain bandwidth and phase margin are stable.

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CHO, YONG-SOO, SIE YOUNG CHOI, H. TAKAO, K. SAWADA i M. ISHIDA. "LOW VOLTAGE SOI CMOS IMAGE SENSOR WITH PINNED PHOTODIODE ON HANDLE WAFER". International Journal of Modern Physics B 20, nr 25n27 (30.10.2006): 4207–12. http://dx.doi.org/10.1142/s0217979206041100.

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We have fabricated 32 × 32 SOI CMOS active pixel image sensor with pinned photodiode on handle wafer in order to reduce dark current, transfer charge completely, and improve spectral response. The four transistor type active pixel image sensor is comprised of reset and source follower transistors on SOI seed wafer, while the pinned photodiode, transfer gate, and floating diffusion are fabricated on SOI handle wafer. The pinned photodiode could be optimized because the process of the photodiode on SOI handle wafer is independent of the transistor process on SOI seed wafer. The optimized pinned photodiode is simulated in order to understand complete charge transfer at 3.3 V and 2.5 V of transfer gate voltage, respectively. We also investigated the optical response of fabricated active pixel image sensor under different illumination density conditions from He - Ne laser source at 3.3 V and 2.5 V of transfer gate voltage.

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Chao, Calvin Yi-Ping, Shang-Fu Yeh, Meng-Hsu Wu, Kuo-Yu Chou, Honyih Tu, Chih-Lin Lee, Chin Yin, Philippe Paillet i Vincent Goiffon. "Random Telegraph Noises from the Source Follower, the Photodiode Dark Current, and the Gate-Induced Sense Node Leakage in CMOS Image Sensors". Sensors 19, nr 24 (10.12.2019): 5447. http://dx.doi.org/10.3390/s19245447.

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In this paper we present a systematic approach to sort out different types of random telegraph noises (RTN) in CMOS image sensors (CIS) by examining their dependencies on the transfer gate off-voltage, the reset gate off-voltage, the photodiode integration time, and the sense node charge retention time. Besides the well-known source follower RTN, we have identified the RTN caused by varying photodiode dark current, transfer-gate and reset-gate induced sense node leakage. These four types of RTN and the dark signal shot noises dominate the noise distribution tails of CIS and non-CIS chips under test, either with or without X-ray irradiation. The effect of correlated multiple sampling (CMS) on noise reduction is studied and a theoretical model is developed to account for the measurement results.

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Zhang, Jianyu, i Pak Kwong Chan. "A CMOS PSR Enhancer with 87.3 mV PVT-Insensitive Dropout Voltage for Sensor Circuits". Sensors 21, nr 23 (25.11.2021): 7856. http://dx.doi.org/10.3390/s21237856.

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A new power supply rejection (PSR) based enhancer with small and stable dropout voltage is presented in this work. It is implemented using TSMC-40 nm process technology and powered by 1.2 V supply voltage. A number of circuit techniques are proposed in this work. These include the temperature compensation for Level-Shifted Flipped Voltage Follower (LSFVF) and the Complementary-To-Absolute Temperature (CTAT) current reference. The typical output voltage and dropout voltage of the enhancer is 1.1127 V and 87.3 mV, respectively. The Monte-Carlo simulation of this output voltage yields a mean T.C. of 29.4 ppm/°C from −20 °C and 80 °C. Besides, the dropout voltage has been verified with good immunity against Process, Temperature and Process (PVT) variation through the worst-case simulation. Consuming only 4.75 μA, the circuit can drive load up to 500 μA to yield additional PSR improvement of 36 dB and 20 dB of PSR at 1 Hz and 1 MHz, respectively for the sensor circuit of interest. This is demonstrated through the application of an enhancer on the instrumentation Differential Difference Amplifier (DDA) for sensing floating bridge sensor signal. The comparative Monte-Carlo simulation results on a respective DDA circuit have revealed that the process sensitivity of output voltage of this work has achieved 14 times reduction in transient metrics with respect to that of the conventional counterpart over the operation temperature range in typical operation condition. Due to simplicity without voltage reference and operational amplifier(s), low power and small consumption of supply voltage headroom, the proposed work is very useful for supply noise sensitive analog or sensor circuit applications.

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Thakur, Diksha, Kulbhushan Sharma i Rajnish Sharma. "Design of a Low-Noise Low-Power Fourth Order Complementary Super Source Follower Filter for EEG Applications". ECS Transactions 107, nr 1 (24.04.2022): 10969–75. http://dx.doi.org/10.1149/10701.10969ecst.

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Design of a filter for biomedical application is a challenging task owing to its low-power and low-noise values introduced at low frequencies. This paper describes the design of a Complementary Super Source Follower (CSSF-C) Low Pass Filter (LPF) circuit and the same has been compared with Complementary Source Follower (CSF-C) LPF targeted for the detection of EEG signals. Simulated results obtained in Cadence Analog Design Environment using CMOS 0.18 µm technology node shows the CSSF-C LPF circuit emulates gain of -528 mdB, bandwidth of 100 Hz, power consumption of 12.6 nW from 0.5 V supply voltage. Further, the proposed LPF circuit is capable of achieving Dynamic Range (DR) of 63 dB with an Input Referred Noise (IRN) of 36 µVrms. The proposed CSSF-C LPF is expected to improve the quality of acquired EEG signals.

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Sotner, R., J. Jerabek, N. Herencsar, K. Vrba, A. Lahiri i T. Dostal. "Study of Small-signal Model of Simple CMOS Amplifier with Instability Compensation of Positive Feedback Loop". Measurement Science Review 15, nr 3 (1.06.2015): 139–51. http://dx.doi.org/10.1515/msr-2015-0021.

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AbstractThe paper deals with precise analysis of simple AC variable gain CMOS amplifier. The circuit can be used as a simple voltage follower (6 MOS transistors are required) or amplifier. The main attention of this work is focused on a small-signal model of the proposed block and effects of additional passive network leading to compensation of its instability. The continuous gain adjusting in range from 1.1 to 10 (0.8 – 20 dB and with bandwidth 4.9 - 90 MHz at 5 pF load capacitance) is possible and the proposed amplifier is suitable for implementation in systems, where lower range of gain adjusting and large dynamical range is required. Theoretical analyses are supported by PSpice simulations (TSMC 0.18 um technological models) and experimental measurements with commercially available CMOS transistor fields (ALD1106/7) also confirm the discussed behavior of the amplifier.

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Corbacho, Israel, Juan M. Carrillo, José L. Ausín, Miguel Á. Domínguez, Raquel Pérez-Aloe i J. Francisco Duque-Carrillo. "A Fully-Differential CMOS Instrumentation Amplifier for Bioimpedance-Based IoT Medical Devices". Journal of Low Power Electronics and Applications 13, nr 1 (30.12.2022): 3. http://dx.doi.org/10.3390/jlpea13010003.

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The implementation of a fully-differential (FD) instrumentation amplifier (IA), based on indirect current feedback (ICF) and aimed to electrical impedance measurements in an Internet of Things (IoT) biomedical scenario, is presented. The IA consists of two FD transconductors, to process the input signal and feed back the output signal, a summing stage, used to add both contributions and generate the correcting current feedback signal, and a common-mode feedback network, which controls the DC level at the output nodes of the circuit. The transconductors are formed by a voltage-to-current conversion resistor and two voltage buffers, which are based on a super source follower cell in order to improve the overall response of the circuit. As a result, a compact single-stage structure, suitable for achieving a high bandwidth and a low power consumption, is obtained. The FD ICF IA has been designed and fabricated in 180 nm CMOS technology to operate with a 1.8-V supply and provide a nominal gain of 4 V/V. Experimental results show a voltage gain of 3.78 ± 0.06 V/V, a BW of 5.83 MHz, a CMRR at DC around 70 dB, a DC current consumption of 266.4 μA and a silicon area occupation of 0.0304 mm2.

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Yen, Chen, Wei i Chung. "A CMOS Transmitter Analog Baseband for 5G Mobile Communication". Electronics 8, nr 11 (8.11.2019): 1319. http://dx.doi.org/10.3390/electronics8111319.

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CMOS analog baseband circuits including a low-pass filter (LPF) and a programmable gain amplifier (PGA) are designed and implemented for the fifth-generation (5G) mobile communication. The super source follower topology is adopted to achieve a wideband LPF with good linearity, while the constant current density gain control technique is used to implement gain cells of the PGA. The circuits are integrated as an analog baseband for a 5G transmitter (TX) and fabricated using TSMC 90-nm CMOS technology. The analog baseband exhibits the bandwidth from 1.03 to 1.05 GHz when the voltage gain is varied from −18.9 dB to 3.8 dB in 1-dB steps. The gain step errors are within −0.7 dB to 0.9 dB. In the highest gain mode, the analog baseband achieves the IP1dB of −10 dBv and the IIP3 of −0.2 dBv. Over the band of interest, the NF of the analog baseband is 24.4–40.0 dB.

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Hadi, D. A., A. Z. Jidin, N. Ab Wahab, Madiha Z., Nurliyana Abd Mutalib, Siti Halma Johari, Suziana Ahmad i M. Nuzaimah. "CMOS ring oscillator delay cell performance: a comparative study". International Journal of Electrical and Computer Engineering (IJECE) 9, nr 3 (1.06.2019): 1757. http://dx.doi.org/10.11591/ijece.v9i3.pp1757-1764.

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A common voltage-controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator (RO). RO consist of number of inverters cascaded together as the input of the first stage connected to the output of the last stage. It is important to design the RO to be work at desired frequency depend on application with low power consumption. This paper presents a review the performance evaluation of different delay cell topologies the implemented in the ring oscillator. The various topologies analyzed includes current starved delay cell, differential delay cell and current follower cell. Performance evaluation includes frequency range, frequency stability, phase noise and power consumption had been reviewed and comparison of different topologies has been discussed. It is observed that starved current delay cell have lower power consumption and the different of the frequency range is small as compared to other type of delay cell.

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Hirunporm, Jirawat, i Montree Siripruchyanun. "A Low-voltage Current-mode Electronically Controllable Four-quadrant Zero/span Circuit". ECTI Transactions on Electrical Engineering, Electronics, and Communications 18, nr 1 (28.02.2020): 61–69. http://dx.doi.org/10.37936/ecti-eec.2020181.218761.

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A low-voltage four-quadrant current-mode current-controllable zero/span circuit is discussed. The circuit structure is based on CMOS current follower with adjustable current gain and 4 diodes, without any resistor. The proposed circuit has advantage in such low-voltage architecture biased with as low as ±0.5V power supply. It can generate four-quadrant outputs, without any changing circuit topology. Additionally, its zero and span levels can be independently tuned by electronic method though relative bias currents, where a low-offset output current can be achieved. The total power consumption is approximately 10µW, much lower than a traditional one. Simulation results are shown; it offers good performances of the proposed circuit as depicted. Furthermore, to extend the workability of the proposed zero/span circuit, its application in current-mode Wheatstone bridge to alleviate the offset problem.

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Bhatia, Veepsa, i Neeta Pandey. "Modified Tang and Pun’s Current Comparator and Its Application to Full Flash and Two-Step Flash Current Mode ADCs". Journal of Electrical and Computer Engineering 2017 (2017): 1–12. http://dx.doi.org/10.1155/2017/8245181.

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A modification to an existing current comparator proposed by Tang and Pun has been presented. The circuit introduces a flipped voltage follower (FVF) which replaces the source follower input stage of the existing current comparator of Tang and Pun. This modification culminates into higher speed especially at lower currents and lower power dissipation. The application of the proposed current comparator has also been put forth by implementing a 3-bit current mode (CM) ADC and a two-step 3-bit CM ADC. The theoretical propositions are verified through spice simulation using 0.18 μm TSMC CMOS technology at a power supply of 1.8 V. Propagation delay, power dissipation, and power delay product (PDP) have been calculated for the proposed current comparator and process parameter variation has been studied. For both the implementations of ADCs, performance parameters, namely, DNL, INL, missing codes, monotonicity, offset, and gain errors, have been evaluated.

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Hwan, Wong How, i Yusmeeraz Binti Yusof. "Monolithic Biosensor for Gene-Based Disease Detection". Advanced Materials Research 925 (kwiecień 2014): 519–23. http://dx.doi.org/10.4028/www.scientific.net/amr.925.519.

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In this paper, charge-modulated field effect transistor based detection circuit is presented for the purpose of electrical detection of DNA hybridization. The readout circuit consists of a drain follower and a compensated differential amplifier. It is able to achieve a voltage gain of 56.94 dB in the frequency range up to 6.79 kHz using 0.18μm Silterra CMOS process. The compensation technique is used in the detection circuit in order to improve the phase margin to 52.66o. The proposed potentiometric biosensor eliminates the need for a reference electrode which can offer great potential for miniaturized sensor array that would enable a massive parallel detection of DNA assay.

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Park, Jihoon, Woong-Joon Ko, Dong-Seok Kang, Yoonmyung Lee i Jung-Hoon Chun. "An Output Capacitor-Less Low-Dropout Regulator with 0–100 mA Wide Load Current Range". Energies 12, nr 2 (10.01.2019): 211. http://dx.doi.org/10.3390/en12020211.

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An output capacitor-less low-dropout (OCL-LDO) regulator with a wide range of load currents is proposed in this study. The structure of the proposed regulator is based on the flipped-voltage-follower LDO regulator. The feedback loop of the proposed regulator consists of two stages. The second stage is turned on or off depending on the variation in the output load current. Hence, the regulator can retain a phase margin at a wide range of load currents. The proposed regulator exhibits a better regulation performance compared to the ones in previous studies. The test chip is fabricated using a 65-nm CMOS process.

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Kim, K. H., i S. J. Kim. "Noise characteristic design of CMOS source follower and voltage amplifier for active semiconductor microelectrodes for neural signal recording". Medical & Biological Engineering & Computing 38, nr 4 (lipiec 2000): 469–72. http://dx.doi.org/10.1007/bf02345018.

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